A.
Behavioural Modelling Basics (Initial &
Always Blocks)
1. Write a module that toggles a 1-bit signal using initial and always blocks.
module toggle(input clk, output reg tog); module test;
reg tog,clk;
initial begin
toggle t1(.clk(clk),.tog(tog));
tog=0; initial begin
end $monitor("time=%t tog=%b clk=%b",$time,tog,clk);
clk=0;
always@(posedge clk) begin
#5 clk=1;
tog=~tog; #5clk=0;
end #5clk=1;
#5 $finish;
endmodule end
endmodule
2. Simulate a 16-bit register being initialized and incremented inside an always
block
module inc_16bit(input clk,output reg [15:0]inc); module test;
initial begin reg clk;
inc=16'h0000; wire [15:0]inc;
end integer i;
always@(posedge clk) inc_16bit u1(.clk(clk),.inc(inc));
begin initial begin
inc=inc+1; clk=0;
end forever #5 clk=~clk;
endmodule end
initial begin
$monitor("time=%t inc=%b decimal=%0d clk=%b",$time,inc,inc,clk);
#50 $finish;
end
endmodule
3. Use multiple always blocks in a module and simulate how they execute in parallel.
module parallel_binary ( input wire clk, input wire
rst, output reg flag, output reg [3:0] count);
always @(posedge clk or posedge rst) begin
if (rst)
flag <= 1'b0;
else
flag <= ~flag;
end
always @(posedge clk or posedge rst) begin
if (rst)
count <= 4'b0000;
else
count <= count + 4'b0001;
end
endmodule
module tb_parallel_binary;
reg clk, rst;
wire flag;
wire [3:0] count;
parallel_binary uut ( .clk(clk), .rst(rst), .flag(flag), .count(count)
always #5 clk = ~clk;
initial begin
clk = 1'b0; rst = 1'b1;
#12 rst = 1'b0; #100 $finish;
end
initial begin
$monitor("Time: %0t|clk=%b | flag: %b | count: %b ",
$time,clk, flag, count);
end
endmodule
4. Explain the functional difference between initial and always with simulation
output.
module initial_vs_always;
reg clk = 0;
reg [3:0] counter = 0;
always #5 clk = ~clk;
initial begin
$display("Time=%0t | Initial block started",
$time);
#100;
$display("Time=%0t | Initial block ended",
$time); initial Block
•Executes only once, at the start of simulation
$finish; time (t=0).
end •Used mainly for testbenches, initialization, or one-
time activities like stimulus generation.
always @(posedge clk) begin
counter = counter + 1; always Block
•Executes repeatedly throughout the simulation.
$display("Time=%0t | Counter incremented to •Starts at t=0 and runs forever based on a sensitivity
%0d", $time, counter); list or a timing control.
•Used to describe hardware behavior, such as
end sequential or combinational logic.
endmodule
5. Design a clock generator using initial and forever loop.
module clock_generator ( output reg clk ); module tb_clock_generator;
initial begin wire clk;
clk = 0; clock_generator uut ( .clk(clk) );
forever #5 clk = ~clk; initial begin
end $display("Time\tclk");
endmodule $monitor("%0t\t%b", $time, clk);
#50;$finish;
end
endmodule
6. Implement a module that uses initial for setup and always for functional
updates.
module counter_with_init ( input wire clk, module tb_counter_with_init;
input wire reset, output reg [3:0] count); reg clk,reset;
initial begin wire [3:0] count;
count = 4'b0000; counter_with_init uut ( .clk(clk), .reset(reset),
.count(count) );
end
initial begin
always @(posedge clk) begin clk = 0;
if (reset) forever #5 clk = ~clk;
count <= 4'b0000; end
else initial begin
$dumpfile("waveform.vcd");
count <= count + 1;
$dumpvars(0, tb_counter_with_init);
end $display("Time\tReset\tCount");
endmodule $monitor("%0t\t%b\t%0d", $time, reset, count);
reset = 1; #12; reset = 0; #50;reset = 1;#10;reset = 0;
#30; $finish;
end
endmodule
7. What happens if you use multiple initial blocks in the same module?
Demonstrate.
module multiple_initial_blocks; reg [3:0] x;
reg [3:0] y;
initial begin
x = 4'b0001;
$display("Time: %0t | Initial Block 1 sets x = %b",
$time, x);
end
initial begin
y = 4'b0010;
$display("Time: %0t | Initial Block 2 sets y = %b",
$time, y);
end
initial begin
#10; $display("Time: %0t | Initial Block 3 reads x =
%b, y = %b", $time, x, y);
end
endmodule
8. Simulate two always blocks modifying different signals—observe timing.
module always_block_demo;
reg clk;
reg [3:0] counter_a;
reg [3:0] counter_b;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
always @(posedge clk) begin
counter_a <= counter_a + 1;
$display("Time: %0t | counter_a = %0d", $time,
counter_a);
end
always @(negedge clk) begin
counter_b <= counter_b + 2;
$display("Time: %0t | counter_b = %0d", $time,
counter_b);
end
initial begin
counter_a = 0; counter_b = 0;
#50 $finish;
end
endmodule
