UNIT - II

Introduction of Computer Organization:

• The organization of the computer is defined by its internal
registers, the timing and control structure and the set of
instructions that it uses.
• A computer instruction is a binary code that specifies a
sequence of micro-operations.
• The Computer reads cash instruction from memory and
places it in a control register.
• The Control then interprets the binary code of the instruction
and proceeds to execute it by issuing a sequence of micro-
operations.
• Every computer has its own unique instruction set.
• The ability to store and execute instructions, is the most
important property of a general – purpose computer.
2) Basic Computer architecture:

• Control processing Unit (CPU) This is the brain of the

computer. It controls the other components by deciding
what to do next.
• Memory This is the part of the program that
temporarily stores data & instructions for the CPU.
• 1/0 subsystem  This is the part of the computer that
interacts with the outside world. If the computer did not
have an 1/0 system then it would not be useful for
anything.
• Bus  This is the part or the “wires” the connect the
other three parts of the computer together.
Buses are collection of wires that are individually either
on or off (0 or 1)
Everything connected to the bus sees the same status
for each wire.
• A computer instruction is a binary code that
specifies a sequence oof micro operations for
the computer.
• Instruction code together with the data are
stored in memory.
• The computer reads each instruction from the
memory and places it in the control register.
• Control then interprets the binary code of the
instruction and proceeds to execute it by issuing
a sequence of micro-operations.
3) Basic fetch execute cycle:

4) Computer Instructions:
• The basic computer has three instruction code formats
& each format has 16 bits.
• A memory reference instruction uses 12 bits to specify
the address and one bit to specify the addressing mode
1.
Where I=0 for direct address
I=1 for indirect.
• If the 3 op code bits in position 12 through 14 are not
equal to 111, the instruction is a memory – reference
type.
• If the 3 – bit op code is equal to 111, Control inspects
the bit in position 15.
• If this bit = 0
then, instruction is register reference type
 if bit = 1,
instruction is an i/p – o/p type.

a) Memory – reference instruction

b) Register – Reference instruction

c) I/P – o/p instruction

5) Instruction – Codes:
• Program: A set of instruction’s that specifies the
operations, operands, and sequence by which
processing has to occur.
• Instruction Code: A grp of bits that tells the computer
to perform a specific operation.
• Micro – operation is divided into:
a) operation code
b) operand
c) address
d) addressing mode
6) Timing and Control:
• The timing for all the registers in the Computer is
controlled by master clock generator (MCG).
• The clock pulses are applied to all the flip flops &
registers.
• The clock pulses do not change the state of a register
unless the register is enabled by a control signal.
 There are two types of control organization:
1) Hard wired control
2) Micro-programmed control.
1) Hard-wired organization:
 The control logic is implemented with gates, flip-flops,
decoders, and other digital circuits.
• Advantage:
 It can be optimized to produce a fast mode of
operations.
2) Micro-programmed organization:
 Control info. Is stored in control memory.
 The control memory is programmed to initiate the
required sequence of micro-operations.
• A hard wired control requires changes in the wiring
among various components if design is modified or
changed.
• In micro-programmed control any required changes
or modifications can be done by updating the micro-
program in control memory.
7 )TIMING AND CONTROL

For Example:
 Consider the case when S.C is incremented to provide
timing signals To, T1, T2, T3, & T4 and in sequence at time
T4, S.C is cleared is cleared O if decoder o/p D3 is
active.
Symbolically:
D3 T4 : SC  0
 Timing diagram shows the relationship b/w control
signals.
 The S.C responds to the transition of the clock.
Fig. from morris
mano
 From the figure, last the wave forms show how S.C is
cleared when D3 T4 = 1.
 o/p D3 from the operation decoder becomes active at the
end of timing signal T2.
 when timing signal T4 becomes active, the o/p of the
AND gate that implements the control function D3 T4
become active.
 This signal is applied to CLR i/p S.C.
 On the next the cycle transition the counter is cleared to
O.
 This causes the timing signal T0 to become active
instead of T5 that would have been active if S.C were
incremented instead of cleared.
 To is active during one clock cycle.
 Initially, CLR i/p of SC is active.
 The first the transition of the clock clears SC to O which
in turn activate the timing signal To.
 The clock transition To in the diagram will trigger only
those registers whose control i/p's are connected to
timing signal To.
 OFFLINE CLASSES
8) Instruction Cycle:
• A program residing in the memory unit of
the computer consists of a sequence of
instructions.
• The program is executed in the computer
by going through a cycle for each
instructions.
 Each cycle is sub-divided in sequence of sub-cycles.
1. Fetch the instruction for memory.
2. Decode the instruction.
3. Read the effective address from memory if the
instruction has an indicate address.
4. Execute the instruction.
 After the completion of step 4, the control goes back to
step 1, decode, and execute the next instruction.
From: morris mano
9) Fetch & Decode

• The Program counter pc loaded with the address of the

first instruction in the program.
• The sequence counter SC is cleared to O, providing a
decoded timing signal To.
• After each clock pulse, SC is incremented by one, so
that the timing signals go through a sequence T0, T1, T2
and so on.
• the micro-operations for the fetch and decode phases
can be specified by the following register transfer
statements:
T0 : AR PC

T1 : IR M [AR], PC PC + 1

T2 : DO - - - D7 Decode IR (12-14),

AR IR (0-11), I IR (15)
 Since, only AR is conned to the address i/p’s of the
memory, it is necessary to transfer the address from PC
to AR during clock transition associated with timing
signal To.
 The instruction read from memory is then placed in the
instruction Register (IR) with the clock transition
associated with timing signal T1.
 At the same time, PC is incremented by one to prepare it
for the address of the next instruction in the program.
 At time T2, the operation code in IR is decoded, the
indirect bit is transferred to flip flop I, and the address
part of instruction is transferred .
FLOWCHART OF THE INSTRUCTION CYCLE
10 ) REGISTER -REFERENCE INSTRUCTION:
11) Input - output and interrupt

• A computer is useless unless it communicates with

external environment.
• Instructions & data stored in the money must come from
some i/p devices.
• Computational results must be transmitted o the user
through o/p devices.
• Computer uses many types of i/p - o/p devices.
Fig.: I/p – o/p Configuration
Computer Registers
I/p – o/p & Flip - flop
terminal Serial Communication
interface
Receiver
Printer interface OUTR

AC
bits
8

Transmitter INPR
Keyboard interface

-f l l
ip ro
op
Fl nt
Co
FGI
• The terminal sends and receives serial information. Each
quantity of information has 8 bits of an alphaneumeric
code.
• The serial information from keyboard is shifted into i/p
register INPR.
• The serial information for the printer is stored in the o/p
register OUTR.
• These two registers - communicate with a
communication interface serially and with the AC in
parallel.
 Input Register:
• The input register INPR consists 8 bits. The 1 - bit i/p
flag FGI is a control flip - flop.
• The flag is 1 when new information is available in i/p
device.
• The flag is 0 when information is accepted by the AC.
• The information transfer is as follows:
 Initially FGI is set to O.
 When Key is stuck in the keyboard 8 bit alphaneumeric
code is shifted into INPR and FGI is set to 1.
 As long as flag is set, information of INPR cannot be
changed.
 Now, information from INPR is transferred in parallel
into AC and FGI is cleared to O.
 One the flag is cleared, new information can be shifted
into INPR by striking another key.
 o/p Register:
• FGO is O because this condition indicates that o/p
device is in the process of printing.
• The output Register OUTR works similarly but the
direction of information flow is reversed.
• Initially, the output flag FGO is set to 1.
• The computer checks if the flag bit is 1, the information
from AC is transferred in parallel to OUTR and FGO is
cleared to O.
• The o/p device accepts the coded information, prints the
corresponding character.
• When the operation is completed, it sets FGO to 1.
12) I/p - O/p Instructions:

• I/p and o/p instructions are needed for transferring

information to and from AC register and for checking the
flag bits.
• i/p - o/pin instructions have operation code
(op - code) = IIII
and are Recognized D7 = 1 and I = 1 of instruction.
• Control functions & micro - operations for i/p - o/p
instructions are :
From: morris mano
• These instructions are executed with clock transition
associated with timing signal T3.
• Each CONTROL FUNCTION needs a Boolean relation
D7 IT3, which is designated as P.
• The control function is distinguished by one of the bit in
IR ( 6 - II).
• By assigning the symbol Bi, to bit i of IR, all the control
function can be denoted by pBi, for i = 6 through II.
• The sequence counter, SC is cleared to 0 when p =D7
IT3 = I.
• The OUT instruction transfers the eight les significant bit
of AC into the o/p register OUTR and clears o/p flag to o.
• The next two instructions in table check the status of the
flags and cause a skip of the next instruction if flag is 1.
• The instruction that is skipped will normally be a branch
instruction to return & check the flag again.
• The branch instruction is skipped and i/p or o/p
instruction is executed.
• The last two instruction set and clear as interupt enable
flip - flop IEN.
13) Memory - Reference Instruction:

Table of memory reference instruction

Operation Decoder
Di for i = 0 - - - 6
Symbol Symbolic description
Decoder that belongs to
each instruction
1. AND DO AC  AC  M [AR]
AC  AC + M [AR],
2. ADD D1
E  Cout
3. LDA D2 AC  M [AR]
4. STA D3 M [AR]  AC
5. BUN D4 PC  AR
M [AR]  PC,
6. BSA D5
PC  AR + 1
M [AR]  M [AR] +1,
7. ISZ D6 if M [AR] + 1 = 0,
PC  PC +1
• The effective address of the instruction is in the
address register [AR].
• Which is placed during timing signal T2 when I = 0
or during T3 when I = 1.
• The execution of the memory reference instruction
starts with timing signal T4.
1) AND to AC
• This is an instruction that performs the AND logic
operation on pairs of bits in AC and MEMORY
WORD specified by the effective address.
• The result of the operation is transferred to AC.
• The micro-operation that execute this instruction:
D0 T4 : DR M[AR}

D0 T5 : AC 
AC DR, SC 0

2. ADD to AC
• This instruction adds the content of the memory word
specified by the effective address to the value of AC.
• The sum is transferred in to AC and o/p carry C out is
transferred to E (extended accumulator) flip - flop.
• Micro - operations:
D1 T4 : DR M [AR]
D1 T5 :AC AC + DR
E C out
SC 0.

3) Load to AC
• This instruction transfers the memory word specified by
the effective address to AC.
D2 T4 : DR M [AR]
D2 T5 :AC DR, SC 0.
4) STA : Store AC
• This instruction stores the content of AC into memory
word specified by the effective address.
D3 T4 : m [AR] AC,

SC 0.
5) BUN : Branch Unconditionally
• This instruction transfers the program the instruction
specified by the effective address.
• Since PC holds the address of the instruction to be read
fro the memory in the next instruction cycle.
• The BUN instruction allows to specify an instruction out
of the sequence.
so that the program branches unconditionally
D4 T4 : PC AR,
SC 0
6) ISZ : Increment & Skip if Zero
D6 T4 : DR M [AR]
D6 T5 : DR DR + 1
D6 T6 : M [AR] DR,
if (DR = 0) then
(PC PC + I),
SC = 0
14) Central processing unit

• The organization of the computer is defined by its

internal registers, timing and control structures and the
set of instructions that it uses.
• The general purpose digital computer is capable of
executing various micro-operations.
• A program:
• It is a set of instructions that specify the operations,
operands and sequence by which processing has to
occur.
• How data processing can be altered?
• By specifying a new program with different instruction or
specifying the same instruction with different data.
• What is a computer instruction?
• It is binary code that specified a sequence of micro -
operations for the computer together with data stored in
the memory.
• How does this works:
 The computer reads cash instruction from memory and
places it in control register.
 The control then interprets the binary code of the
instruction and proceeds to execute it by issuing a
sequence of micro - operations.
The ability to store & execute instructions, is the
important property of a general purpose computer.
Features of CPU:
15) STACK ORGANIZATION
• A useful feature that is included in the CPU of most
computers is a stack or last in, first out (LiFo) list.
• A stack is a storage device that stores information in
such a manner that the item stored last is the first item
retrieved.
• The operation of a stack can be compared to a stack of
trays.
• The physical registers of a stack are always available for
reading or writing.
• The two operations of a stack are the insertion and
deletion of items.
• The operation of insertion is called PUSH (or push-
down) as it can be thought of as a result of pushing a
new item on top.
• The operation of deletion is called PoP (or pop-up) as it
can be thought of as a result of removing one item so
that the stack pops up.
 Register stack
Address

63 63
FULL EMPTY

It is a 64 word
Register stock
e b it r e g isters
On
4 4
3 C 3
SP
2 B 2

1 A 1

0 0 is ters
i tr eg
ne b
O
DR
• A stack can be placed in a portion of a large memory or it
can be organized as a collection of finite no. of memory
words or registers.
• In the above figure, there is an organization of 64 word
register stack.
• The stack points 'SP' contains a binary no. whose value
is equal to the address of the word currently on top of the
stack.
• There are three items in the stack A, B and C.
• Item C is on the top so, the content of SP is 3.
• To remove item, the stack is popped by reading the
memory word at address 3 and decrementing he content
of SP.
• Item 'B' is on the top of the stack since SP holds
address 2.
• To insert a new item, the stack is pushed by
incrementing SP and writing a word in the next higher
location.
• 'DR' is the 'data register' that holds the binary data to be
written or read out of the stack.
• In a 64 word stack, the stack pointer contain 6-bits as
• 2*2*2*2*2*2 = 64.
• Since, SP has only 6 bits so, it cannot exceed a no.
greater then 63 (111111 in binary). When 111111 + 1
(incremented by 1),
the result is O since III II .I
+ I
1000 000 Binary
• A stack organization is very effective for evaluating
arithmatic expressions.
• The common arithmatic expressions are written in infix
notation.
• A*B + C*D
• The star is in b/w two operands A and B or C and D.
• The plus is in b/w two products.
• A + B infix notation
+ A B prefix or polish notation
AB + post fix or reverse polish notation
 16) Various types of address instructions:
Based on the number of address used in instruction:
a) Three – address instruction:
• The program in assembly language that evaluate:
X = (A+B) * (C+D)
ADD R1, A, B R1  M [A] + M [B]
ADD R2, C, D R2  M [C] + M [D]
MUL X, R1, R2 M [X]  R1 * R2
• It is assumed that the computer has two processor
registers R1 and R2.
• M [A]  operand at memory address symbolized by
A.
 Advantage:
• It results in short programs when evaluating arithmatic
operations.
 Disadvantage:
• Binary coded instructions require too many bits to
specify thee address.
b) Two-Address instructions:
• Two - Address instructions are the most common in
commercial computers.
• Here, again each address field can specify either a
processor register or a memory word.
 Evaluate = (A+B) * (C+D)

MOV R1, A R1  M [A]

ADD R1, B R1  R1 + M[B}

MOV R2, C R2  M [C]

ADD R2, D R2  R2 + M [D]

MUL R1, R2 R1  R1 * R2

MOV X, R1 M [X]  R1
• MOV instruction moves or transfers the operands to and
from memory and processor registers.
c) One - address instructions:
• One - address instructions use an Accumulator Register
(AC) for all data manipulations.
• For multiplication and division there is a need for a
second register.
• Here, we neglect the second register and assume that
AC contains results of all operators:
• program to evaluate:
 X = (A+B) * (C+D)
• LOAD A AC  M [A]
• ADD B AC  AC + M [B]
• STORE T M [T]  AC
• LOAD C AC  M [C]
• ADD D AC  AC + M [D]
• MUL T AC  AC * M [T]
• STORE X M [X]  AC
* T is the address of temporary memory location
required for storing the immediate result.
d)Zero - address instructions:
• A stack organized computer does not use an address
field
• PUSH and POP are used.
X = (A+B) * (C+D)
(TOS stands for top of stack)
PUSH A TOS  A
PUSH B TOS  B
ADD TOS  (A+B)
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C+D)
MUL TOS  (C+D) * (A+B)
POP X M [X]  TOS
• The name "zero - address" is given to this type of
computer because of the absence of an address field in
the computational instructions.
17) Addressing modes: (AM)
These are used by the Computers for:
a) For providing versatility to the user such as printers to
memory, wireless for loop control, program relocation,
indexing of data.
b) To reduce the no. of bits in the addressing field of the
instruction.
The Basic operation cycle is divided in 3 phases:
c) Fetch the instruction from memory
d) Decode the instruction
c) Execute the instruction.
• Program Counter: (PC)
 This is a register in the Computer that keeps track of the
instruction in a program stored in memory.
 PC holds the address of the instruction to be executed
next and is incremented each time an instruction is
fetched from memory.
• Mode field:
 These are used to locate the operands needed for the
operation.
ADDRESSING MODES:

1) Immediate mode
2) Direct mode
3) Indirect mode
18) Reduced Instruction set computer (RISC):
In 1980's a no. of computer designers recommended that a
computer uses fewer instructions with simple constructs so
they can be executed much faster within CPU without having
to use memory so often.
This type of computer is RISC .
• Characteristics of RISC:

a) Relatively few instructions.

b) Relatively few addressing modes.
c) Memory address method limited to load an instruction.
d) All operations done within the register of the CPU7.
e) Fixed length, easily decoded instruction for mat.
f) Single cycle instruction execution.
g) Hardware control rather than micro-programmer control.
Complex Instruction Set Computer (CISC):
a) Large no. of instructions.
b) Some instructions that perform specialized task and one
used for quantity.
c) Large no. of addressing modes.
d) Variable length instruction formats.
e) Instructions that manipulate operational in memory.