8085 - Interrupts

 What is an Interrupt?
• It means interrupting the normal execution of the microprocessor.
Interrupt is a process where an external device can get the attention of the
microprocessor.
• The process starts from the I/O device
• The process is asynchronous.
An interrupt is considered to be an emergency signal that may be serviced.
• The Microprocessor may respond to it as soon as possible.
What happens when MP is interrupted ?
• When the Microprocessor receives an interrupt signal, it suspends the
currently executing program and jumps to an Interrupt Service Routine (ISR)
to respond to the incoming interrupt.
• Each interrupt will most probably have its own ISR.
Steps whenever there is an interrupt?

PC PC contents are
stored in stack
103

100
101
current
STACK
102
103
103 SP
104
 Interrupts in 8085 INTA

Interrupt

Save Send out

program Disable interupt
counter interrupts acknowledg
e

Main routine
Go to
service
Go back
routine

Get EI
original RET
program
counter Service routine

4
 Interrupts in 8085
 When the interrupt signal arrives:
• The processor will break its routine
• Go to a different routine (interrupt service routine)
• Complete the interrupt service routine(ISR)
• Go back to the “regular” routine
 In order to execute an interrupt routine, the processor:
• Should be able to accept interrupts (interrupt enable)
• Save the last content of the program counter
• Know where to go in program memory to execute the ISR
• Tell the outside world that it is executing an interrupt.
• Go back to the saved PC location when finished.
 Interrupts increase processor system efficiency by letting I/O device request CPU time only
when that device needs immediate attention.
 An interrupt is a subroutine call initialized by external hardware.
 The request is asynchronous  it may occur at any point in a program’s execution.
 Types of Interrupts

Interrupts

Based on source of Based on ISR Based on Recognition

Interrupts execution of Interrupts

Non - Non -
Hardware Software Vectored Maskable
Vectored Maskable
• Based on triggering the Interrupts can be classified as Edge Triggered and Level
Triggered
• The Interrupt structure can also be priority based interrupts.
 CLASSIFICATION OF INTERRUPTS
 Based on masking and unmasking of interrupts :
Maskable Interrupts:
Can be delayed or Rejected
The MPU is interrupted ONLY if that particular input is enabled.
It is enabled or disabled under program control.
If disabled, an interrupt signal is ignored by the MPU
Non-Maskable Interrupts
Can not be delayed or Rejected
The MPU is interrupted when a logic signal is applied to this type of input.
 Response to Interrupt
• Responding to an interrupt may be immediate or delayed depending on whether the interrupt is
Maskable or Non-Maskable and whether interrupts are being masked or not.
• MP completes its current machine cycle.
• There are two ways of redirecting the execution to the ISR depending on whether the interrupt is
vectored or non-vectored.
• Steps in response to Interrupt:
1. The interrupt process should be enabled using the EI instruction.
2. The processing of the current instruction is completed. The 8085 checks for an
interrupt during the execution of every instruction.
3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the
microprocessor will complete the executing instruction, and reset the interrupt flip flop.
4. An interrupt machine cycle is executed during which the PC is saved and control is
transferred to an appropriate memory location.
5. The state of the MPU is saved.
6. If more than one I/O device is associated with the location transferred
to, the highest priority device requesting an interrupt is identified.
7. The microprocessor then executes a call instruction that sends the
execution to the appropriate location in the interrupt vector table.
8. A subroutine is executed which services the interrupt I/O device.
9. The service routine must include the instruction EI to re-enable the
interrupt process.
10. At the end of the service routine, the RET instruction returns the
execution to where the program was interrupted.
11. The saved state of the microprocessor is restored.
12. Control is returned to the instruction that follows the interrupted
instruction.
Response to Interrupt
There are two ways of redirecting the execution to the
ISR depending on whether the interrupt is vectored or
non-vectored.
Vectored: The address of the subroutine is already
known to the Microprocessor
Non Vectored: The device will have to supply the
address of the subroutine to the Microprocessor
Edge Triggered Interrupts Vs Level Triggered Interrupts

Rising High
edge level

Falling
edge Low
level
8085 Interrupts
TRAP
RST7.5
RST6.5
RST 5.5 8085
INTR
 Interrupts of 8085
• Hardware interrupts:
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• INTR
• Software Interrupts
• RST O
• RST 1
• RST 2
• RST 3
• RST 4
• RST 5
• RST 6
• RST 7
 Interrupts of 8085
• Priorities of the Interrupts:
• TRAP Highest Priority
• RST 7.5
• RST 6.5
• RST 5.5
Lowest Priority
• INTR
 Interrupts of 8085
• Maskable Interrupts:
• RST 7.5
• RST 6.5
• RST 5.5
• INTR
• RST O
• RST 1
• RST 2
• RST 3
• RST 4
• RST 5
• RST 6
• RST 7
• Non - Maskable Interrupts
• TRAP
 RST7.5 Memory
RST 7.5

M 7.5

RST 6.5

M 6.5

RST 5.5

M 5.5

INTR

Interrupt
Enable
Flip Flop

17
 Interrupts of 8085
• Vectored Interrupts:
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• RST O
• RST 1
• RST 2
• RST 3
• RST 4
• RST 5
• RST 6
• RST 7
• Non – Vectored Interrupts
• INTR
 Interrupts of 8085
• Vector address of interrupts
• Vector Address Interrupt number * 8
• Vector address of hardware interrupts

NAME VECTOR ADDRESSES

RST 7.5 003CH(7.5 X 0008H)

RST 6.5 0034H(6.5 X 0008H)

RST 5.5 002CH(5.5 X 0008H)

TRAP 0024H(4.5 X 0008H)

 Interrupts of 8085
• Vector address of Software interrupts
Interrupt Vector Address
RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H
Vectored / Masked Interrupts
The 8085 Interrupts

Interrupt name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes
 Interrupts of 8085
• INTA signal is used for acknowledging interrupt requests foe hardware interrupts
• TRAP and RST 7.5 are both edge triggered and level triggered
• RST 6.5 and RST 5.5 are level triggered
• Trap is a Non – Maskable interrupt and can be delayed only using HOLD signals
or by resetting the microprocessors.
• The interrupts are enabled using EI (enable interrupt) and disabled using DI
(disable interrupt) instructions.
• The interrupts can be masked using SIM (set interrupt Mask) instruction.
• The Interrupt Enable flip flop is manipulated using the EI/DI instructions.
• The individual masks for RST 5.5, RST 6.5 and RST 7.5 are manipulated using
the SIM instruction (Set Interrupt Mask).
• This instruction takes the bit pattern in the Accumulator and applies it to the
interrupt mask enabling and disabling the specific interrupts.
• Accumulator contents for a SIM instruction:

SOD SOE X R 7.5 MSE M 7.5 M 6.5 M 5.5

RST 5.5 MASK

Serial Output Data RST 6.5 MASK
RST 7.5 MASK

MASK SET ENABLE

SOD Enable

Reset RST 7.5

Undefined
• Accumulator contents for a RIM instruction:
The 8085 Interrupts
Interrupt Masking Triggering
Maskable Vectored
Name Method Method

Level
INTR Yes DI / EI No
Sensitive

RST 5.5 / DI / EI Level

Yes Yes
RST 6.5 SIM Sensitive

DI / EI Edge
RST 7.5 Yes Yes
SIM Sensitive
Level &
TRAP No None Yes Edge
Sensitive

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