COE 372 Sem2, 2023/24

L10:
Digital System Design at
the Register Transfer Level
 Reading
• Hwang, Digital Logic & Microprocessor Design
With VHDL
– Chapter 9
• Sections 9.1, 9.2, 9.3, 9.4, 9.5, 9.6
– Chapter 10
• Sections 10.1, 10.2, 10.3

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 Lecture Overview
• Digital system design approach
• Complex data
• Datapath
• Designing datapath
• Control unit
• FSM-based control unit
• Moore and Mealy Machines
• Designing FSM-based control unit

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 Digital System Design Approach

First, partition into Datapath and Control Unit

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 Digital System Design
• First, partition into two main subsystems

1. Datapath/Data Subsystem
2. Control Unit /Control Subsystem/Controller
Structure of a Digital System
 Circuits for Complex Data
Operations
• Complex data operations involve multiple
steps
• For example, circuit for adding four
numbers
– (n-1) adders
 Circuits for Complex Data
Operations—Datapath
• What about a circuit for adding a million
numbers? Use 999999 adders?
• No, instead, we design a circuit one adder
and use it a million times
• A datapath circuit allows us to
do such—for performing
operations involving
multiple steps
 Circuits for Complex Data
Operations—Register
• A register is needed to store the temporary
result after each addition
• The temporary result is fed back to the
input of the adder so that the next
number can be added to the
current sum (accummulation)
 Datapath
• Responsible for the manipulation of data
• Comprises functional units such as
– adders, shifters, multipliers, ALUs, and
comparators
• registers and other memory elements for
temporary storage of data
• buses, multiplexers, and tri-state buffers
—movement of data among different
components in datapath, and the external
world
 Datapath—Data I/O
• external data enters the datapath through the
data input lines
• Results from the datapath operations are
provided through the data output lines
• These are attached to the primary
input/output data ports
 Datapath—Control Signals
• For correct function
– Appropriate control signals must be asserted
timely
• Control signals are needed for the select and
control lines for the datapath components
– Select lines are for multiplexers, ALUs, and
other units with multiple function
– Read/Write enable signals for registers and
register files
 Datapath—Control Signals Source

– Address lines for register files

– Enable signals for tristate buffers
• At any time the operation of the datapath is
determined by which control signals are
asserted or de-asserted
• Control signals are generated by the control
unit
 Datapath—Status Signals
• Some control signals are dependent on the
data that is being manipulated within the
datapath
• For the control unit to generate these
control signals correctly, the datapath needs
to supply status signals to the control unit
• these signals are usually the output of
comparators
 Datapath—Optimized Storage
• the datapath must be able to perform all of the
operations that are required to solve the given
problem
• If the problem requires the storage of three
temporary variables, the datapath must have
registers for their storage
• Registers can be separate register units or
combined in a register file
• two temporary variables can share the same
register if they are not needed at the same time
 Datapath—RTL Design
• Datapath design is also referred to as register-
transfer level (RTL) design
• RTL design takes into consideration how data is
transferred from one register to another, or back to
the same register
• A register-transfer operation is the sequence of
RTL operations
– read data from a register
– modify data by functional units
– write result to a register
 Datapath—Functional Unit Utilization

• Every register-transfer operation must complete

within one clock cycle
• In a single register-transfer operation, a functional
unit cannot be used more than once
• A functional unit can be used only once in the
same clock cycle, but can be used again in a
different clock cycle
DATAPATH
 Designing Dedicated Datapaths
• Building a circuit for solving a single specific problem
• Problem may be specified in the form of an algorithm
• Decisions:
– Kind of registers to use, and how many are needed
– Kind of functional units to use, and how many are needed?
– Can two or more operations share a certain functional unit
– How to connect the registers and functional units together
• Datapath must be able to perform all of the data
manipulation statements and conditional tests specified by
the algorithm
 Designing Dedicated Datapaths:
Selecting Registers
• In most situations, one register per variable used by the
algorithm, however
• if two variables are not used at the same time, then they
can share the same register
• if two or more variables share the same register, then the
data transfer connections are usually more complex
• Can connect all destinations to the same source
• However, multiple sources will require a multiplexer to
select one of the sources to transfer to the destination at a
time
 Designing Dedicated Datapaths
Selecting Functional Units (1)
• Fairly straightforward to decide what kind of functional
units are required
• e.g., algorithm requires the addition of two numbers
include an adder
– dedicated adder, an adder–subtractor combination, or an ALU?
• can be answered by knowing what other data operations are needed
by the algorithm
– only an addition and a subtraction use adder–subtract or
combination unit
– if the algorithm requires several addition operations
• use one adder or several adders?
 Designing Dedicated Datapaths
Selecting Functional Units (2)
• Using one adder:
• datapath size in terms of number of
functional units may decrease
• but, datapath size may also increase because
more complex data transfer paths are
needed
 Designing Dedicated Datapaths
Selecting Functional Units (3)
• e.g., an algorithm containing the following two
addition operations:
• a=b+c
• d=e+f
• Using two separate
adders will result in the
datapath shown 
 Designing Dedicated Datapaths
Selecting Functional Units (4)
• using one adder will require the use of two extra 2-to-1 multiplexers to
select which register will supply the input to the adder
operands
 Designing Dedicated Datapaths
Selecting Functional Units (5)
• The second datapath requires two extra control
signals for the two multiplexers
• In terms of execution speed, the first datapath can
execute both addition statements simultaneously
within the same clock cycle
• but, the second one will have to execute these two
additions sequentially in two different clock cycles
• Final decision as to which datapath to use is up to
the designer
 Designing Dedicated Datapaths
Data Transfer Methods
• Multiple Sources
– multiplexer for selecting which of the sources to use
– sources can be registers, constant values, or functional
unit outputs
• Multiple Destinations
– A source having multiple destinations does not require
any extra circuitry
– A destination does not need data at a particular time—
ignore data
• Tri-state Bus
– multiple sources are connected to the same bus, only
one source is enabled to output at any one time
 Designing Dedicated Datapaths
Generating Status Signals (1)
• Status signals are the results of the
conditional tests t
• Every conditional test requires a
corresponding status signal
• These signals usually are generated by
comparators
 Designing Dedicated Datapaths
Generating Status Signals (2)
• Consider the following IF statement
IF (A = 0) THEN …
 Designing Dedicated Datapaths
Generating Status Signals (3)
• Implementing comparator with an 8-input
NOR gate
 Designing Dedicated Datapaths
Generating Status Signals (4)
• Sometimes an actual comparator is not
needed for generating a status signal
• e.g., IF (A is an odd number) THEN …
• We can simply use
the A0 bit of the 8-bit
number from register
A as the status signal
 Using Dedicated Datapaths (1)
• Datapath has a number of control signals
• Different register-transfer operations are
performed by asserting some control signals
and de-asserting others at different times
• Control signals are thought of as a unit
rather than as individual signals
• All of the control signals for a datapath,
when grouped together, are referred to as a
control word
 Using Dedicated Datapaths (2)
• Datapath operation can be determined by
specifying the bit string for the control word
• Each control word operation will take one
clock cycle to perform
• By combining multiple control words
together in a certain sequence, the datapath
will perform the specified operations in the
require (given) order
 Examples of Dedicated
Datapaths

A=A+ 3 A= B+ C
Datapath for both operations

A= B+ C
A=A+ 3
Both operations with a common adder—
Table of Control Words
Summation of n to 1
Datapath of the Summer
 General Datapaths
• Can be used to solve various problems instead of
just one specific problem, BUT must have
– all of the required functional units
– enough registers for storing all of the temporary data
• Can use a “ready-made” datapath circuit to solve a
given problem without having to modify it
• The tradeoff is a time versus space and for that
matter power consumption
 General Datapath Operation
• Using a general datapath is exactly the same
as using a dedicated datapath
• assert (or deassert) the appropriate control
signals at the right time so that the data
transfer between registers is correct for the
realization of a data manipulation statement
 A Simple General Datapath
• One 2-to-1 MUX
• One ALU
• One register
• One output tri-state
buffer
• Seven control lines
(numbered 0 to 6)
• Thus width of control
word is 7
 A Simple General Datapath:
ALU Operations
• Control signals ALU2,
ALU1, and ALU0 are
used for the selection
of ALU operation
An example of General Datapath
General datapaths—sample
algorithm
The General Datapath with a
Status Signal
Simulation Trace
 A More Complex Algorithm
• How many registers
required?
– More than one
• Cannot use the simple
general datapath
• select a more complex
datapath
.
A more general datapath—register file
and shifter
Summing numbers from n to 1
Control words
Simulation trace
 Revision to do
• Sequential circuit with emphasis on state
diagrams and FSMs
 Controller (Control Unit)
 Controls data movement in the datapath by
switching multiplexers and enabling or disabling
resources
Example: enable signals for registers
Example: select signals for muxes
 Provides signals to activate various processing
tasks in the datapath, i.e. +, -, or *, ...
 Determines the sequence of operations
performed by the datapath.
 Follows some ‘program’ or schedule.
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Programmable vs. Non-Programmable Controller

 Controller can be programmable or non-

programmable
 Programmable
 Has a program counter which points to next instruction
 Instructions are stored in a RAM or ROM
 Microprogrammed CU is an example of programmable
controller
 Non-Programmable
 Once designed, implements the same functionality
 Another term is a “hardwired state machine,” or “hardwired
FSM,” or “hardwired instructions”
 In this course we will be focusing on nonprogrammable
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Control Units based on FSM
 Finite State Machines (FSMs)
 An FSM is used to model a system that transits among
a finite number of internal states. The transitions
depend on the current state and external input.
 The main application of an FSM is to act as the
controller to a large digital system
 Design of FSMs involves
 Define states
 Define state transitions
 Define operations performed in each state
 Optimize / minimize FSM
 Manual optimization/minimization is practical for
small FSMs only.
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 Moore FSM
 Output is a function of the present state only.

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 Mealy FSM
 Output is a function of the present state and the inputs.

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STATE DIAGRAMS

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 Moore Machine
 State operations: datapath operations including
output assignments.
 Transition conditions: Boolean expressions

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 Mealy Machine

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 Moore FSM – Example 1
 Moore FSM that recognizes sequence “10”

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 Mealy FSM – Example 1
 Mealy FSM that recognizes sequence “10”

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 Moore vs. Mealy FSM (1)

 Moore and Mealy FSMs are functionally

equivalent.
 Equivalent Mealy FSM can be derived from
Moore FSM and vice versa.
 Mealy FSM usually requires less number of
states
 Smaller circuit area.

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 Moore vs. Mealy FSM (2)
 ➺Mealy FSM computes outputs as soon as
inputs change.
 Mealy FSM responds to inputs one clock cycle
sooner than equivalent Moore FSM.
 There are direct paths from inputs to outputs –
can cause output glitches.
 Moore FSM has no combinational path
between inputs and outputs.
 Less likely to affect the critical path of the
entire circuit.

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 Which Way to Go?

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 Designing a Control Unit
• Control unit is a sequential circuit in which
its outputs are dependent on both its current and past
inputs.
• history of past inputs is stored in the state memory
• The datapath is responsible only for the manipulation
of the data; it only performs the register-transfer
operations.
• It is the control unit that determines when each
register-transfer operation is to be executed and in
what order.
Example: Counting 1 to 10
Datapath and a Table of Control
Words
State Tables and State Diagram
Generating Control Words
Implementing the Control Unit
Simple If-Then-Else
Table of Control Words
Incorrect state diagram
Correct state diagram
Correct State Table & Diagram
Generating the Control Words
Implementation
Generating status signals
Tapping Status Signals
 Summary
 Overview of a digital system
 Complex data
 Datapath
 Designing datapath
– Selecting registers
– Selecting functional units
– Data transfer methods
– Generating status signals
 Dedicated datapath
 General datapath
 Control unit
– FSM-based control unit
– Moore and Mealy Machines
– Designing FSM-based control unit
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