+ Chapter 7

Input/Output

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+
External Devices

 Provide a means of
Three
exchanging data between
the external environment
categories:
and the computer  Human readable
 Suitable for communicating with
 Attach to the computer by a the computer user
link to an I/O module  Video display terminals (VDTs),
 The link is used to exchange printers
control, status, and data
between the I/O module and
 Machine readable
the external device  Suitable for communicating with
equipment
 Peripheral device
 Magnetic disk and tape systems,
sensors and actuators
 An external device
connected to an I/O module  Communication
 Suitable for communicating with
remote devices such as a
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. terminal, a machine readable
device, or another computer
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+ Keyboard/Monitor Most common means of
computer/user interaction
User provides input through
the keyboard
International Reference
Alphabet (IRA) The monitor displays data
provided by the computer
 Basic unit of exchange is the
character
Keyboard Codes
 Associated with each character is a
code
 When the user depresses a key it
 Each character in this code is
represented by a unique 7-bit binary generates an electronic signal that is
code interpreted by the transducer in the
keyboard and translated into the bit
 128 different characters can be
pattern of the corresponding IRA code
represented
 This bit pattern is transmitted to the
 Characters are of two types: I/O module in the computer
 Printable
 Alphabetic, numeric, and special  On output, IRA code characters are
characters that can be printed on transmitted to an external device
paper or displayed on a screen from the I/O module
 Control
 Have to do with controlling the
 The transducer interprets the code
and sends the required electronic
printing or displaying of characters
signals to the output device either to
 Example is carriage return
display the indicated character or
 Other control characters are perform the requested control
concerned with communications
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procedures
 The major functions for an I/O
module fall into the following
categories:
Control and timing
• Coordinates the flow of traffic between internal resources and external
devices
Processor communication
• Involves command decoding, data, status reporting, address recognition

Device communication
• Involves commands, status information, and data

Data buffering
• Performs the needed buffering operation to balance device and memory
speeds
Error detection
• Detects and reports transmission errors

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ Programmed I/O
Three techniques are possible for I/O
operations:
 Programmed I/O
 Data are exchanged between the processor and the I/O module
 Processor executes a program that gives it direct control of the
I/O operation
 When the processor issues a command it must wait until the I/O
operation is complete
 If the processor is faster than the I/O module this is wasteful of
processor time
 Interrupt-driven I/O
 Processor issues an I/O command, continues to execute other
instructions, and is interrupted by the I/O module when the latter
has completed its work
 Direct memory access (DMA)
 The I/O module and main memory exchange data directly
without
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Hoboken, NJ. All rights reserved.
 Table 7.1
I/O Techniques

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+
I/O Commands
 There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:

1) Control
- used to activate a peripheral and tell it what to do

2) Test
- used to test various status conditions associated with an I/O
module and its peripherals

3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer

4) Write
- causes the I/O module to take an item of data from the data
bus and subsequently transmit that data item to the
peripheral
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 I/O Instructions
With programmed I/O there is a close correspondence between the I/O-
related instructions that the processor fetches from memory and the I/O
commands that the processor issues to an I/O module to execute the
instructions

Each I/O device connected through I/O modules is given

a unique identifier or address

The form of the

instruction
When the processor
issues an I/O Memory-mapped I/O
depends on the command, the
way in which command contains
external devices the address of the
are addressed desired device

Thus each I/O

module must There is a single address space for A single read line and a single write
interpret the memory locations and I/O devices line are needed on the bus
address lines to
determine if the
command is for
itself

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+
I/O Mapping Summary

 Memory mapped I/O

 Devices and memory share an address space
 I/O looks just like memory read/write
 No special commands for I/O
 Large selection of memory access commands available

 Isolated I/O
 Separate address spaces
 Need I/O or memory select lines
 Special commands for I/O
 Limited set

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 Interrupt-Driven I/O
The problem with programmed I/O is that the
processor has to wait a long time for the I/O
module to be ready for either reception or
transmission of data

An alternative is for the processor to issue an

I/O command to a module and then go on to do
some other useful work

The I/O module will then interrupt the processor

to request service when it is ready to exchange
data with the processor

The processor executes the data transfer and

resumes its former processing

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 Design Issues
• Because there
will be multiple
I/O modules how
does the
Two design processor
determine which
issues arise device issued
in the interrupt?
implementin • If multiple
g interrupt interrupts have
I/O: occurred how
does the
processor decide
which one to
process?
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+ Device Identification
Four general categories of techniques are in
common use:
 Multiple interrupt lines
 Between the processor and the I/O modules
 Most straightforward approach to the problem
 Consequently even if multiple lines are used, it is likely that each line will have
multiple I/O modules attached to it
 Software poll
 When processor detects an interrupt it branches to an interrupt-service routine whose
job is to poll each I/O module to determine which module caused the interrupt
 Time consuming

 Daisy chain (hardware poll, vectored)

 The interrupt acknowledge line is daisy chained through the modules
 Vector – address of the I/O module or some other unique identifier
 Vectored interrupt – processor uses the vector as a pointer to the appropriate
device-service routine, avoiding the need to execute a general interrupt-service
routine first
 Bus arbitration (vectored)
 An I/O module must first gain control of the bus before it can raise the interrupt
request line
 When the processor detects the interrupt it responds on the interrupt acknowledge
line
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 ThenEducation, Inc., Hoboken, NJ. All rights reserved.
the requesting module places its vector on the data lines
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 Drawbacks of Programmed and
Interrupt-Driven I/O

 Both forms of I/O suffer from two inherent

drawbacks:

1) The I/O transfer rate is limited by the

speed with which the processor can test
and service a device

2) The processor is tied up in managing an

I/O transfer; a number of instructions
must be executed for each I/O transfer

+
 When large volumes of data are to be moved a
more efficient technique is direct memory access
(DMA)

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Fly-By DMA Controller

Data does not pass 8237 contains four

through and is not DMA channels
stored in DMA chip • Programmed
• DMA only independently
between I/O port Can do memory to • Any one active
and memory memory via
• Numbered 0, 1, 2,
• Not between two register
and 3
I/O ports or two
memory locations

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+
Direct Cache Access (DCA)
 DMA is not able to scale to meet the increased
demand due to dramatic increases in data rates for
network I/O
 Demand is coming primarily from the widespread
deployment of 10-Gbps and 100-Gbps Ethernet
switches to handle massive amounts of data transfer
to and from database servers and other high-
performance systems
 Another source of traffic comes from Wi-Fi in the
gigabit range
 Network Wi-Fi devices that handle 3.2 Gbps and 6.76
Gbps are becoming widely available and producing
demand on enterprise systems
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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Cache-Related Performance
Issues
Network traffic is transmitted in the form of a sequence of protocol blocks called packets or
protocol data units

The lowest, or link, level protocol is typically Ethernet, so that each arriving and departing
block of data consists of an Ethernet packet containing as payload the higher-level protocol
packet

The higher-level protocols are usually the Internet Protocol (IP), operating on top of
Ethernet and the Transmission Control Protocol (TCP), operating on top of IP

The Ethernet payload consists of a block of data with a TCP header and an IP header

For outgoing data, Ethernet packets are formed in a peripheral component, such as in I/O
controller or network interface controller (NIC)

For incoming traffic, the I/O controller strips off the Ethernet information and delivers the TCP/IP
packet to the host CPU

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+
Cache-Related Performance
Issues

In a DMA scheme, when an

application wishes to
transmit data, it places that
data in an application-
assigned buffer in main
memory
For both • The core transfers this to a system
buffer in main memory and creates
outgoing and the necessary TCP and IP headers,
which are also buffered in system
incoming traffic memory
• The packet is then picked up via
the core, main DMA for transfer via the NIC
• This activity engages not only main
memory, and memory but also the cache
• Similar transfers between system
cache are all and application buffers are
required for incoming traffic
involved
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+
Packet Traffic Steps:
Incoming
Outgoing
 Packet arrives
 Packet transfer requested
 DMA
 Packet created
 NIC interrupts host
 Output operation invoked
 Retrieve descriptors and
headers  DMA transfer

 Cache miss occurs  NIC signals completion

 Header is processed  Driver frees buffer

 Payload transferred

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+
Direct Cache Access Strategies

Simplest strategy was implemented as a prototype

on a number of Intel Xeon processors between 2006
This form of DCA applies only to
and
The DCA 2010
function in the memory
controller sends a prefetch hint to
This enables the core to prefetch
the data packet from the system
incoming network traffic the core as soon as the data is
buffer
available in system memory

Much more substantial gains can be realized by

avoiding the system buffer in main memory
altogether
For incoming
The packet and
packets, the core Implemented in
packet descriptor It has no need to
reads the data from Intel’s Xeon
information are access that data in
the buffer and Cache injection processor line,
accessed only once the system buffer
transfers the packet referred to as Direct
in the system buffer again
payload to an Data I/O
by the core
application buffer

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+
Evolution of the I/O Function

1. The CPU directly controls

4. The I/O module is given direct
a peripheral device.
access to memory via DMA. It can
now move a block of data to or
2. A controller or I/O module from memory without involving the
is added. The CPU uses CPU, except at the beginning and
programmed I/O without end of the transfer.
interrupts.
5. The I/O module is enhanced to
3. Same configuration as in become a processor in its own
step 2 is used, but now right, with a specialized instruction
interrupts are employed. set tailored for I/O
The CPU need not spend
6. The I/O module has a local memory
time waiting for an I/O
of its own and is, in fact, a
operation to be
computer in its own right. With
performed, thus
this architecture a large set of I/O
increasing efficiency.
devices can be controlled with
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+ Universal Serial Bus (USB)
 Widely used for peripheral connections
 Is the default interface for slower speed devices
 Commonly used high-speed I/O
 Has gone through multiple generations
 USB 1.0
 Defined a Low Speed data rate of 1.5 Mbps and a Full Speed rate of 12
Mbps
 USB 2.0
 Provides a data rate of 480 Mbps
 USB 3.0
 Higher speed bus called SuperSpeed in parallel with the USB 2.0 bus
 Signaling speed of SuperSpeed is 5 Gbps, but due to signaling overhead
the usable data rate is up to 4 Gbps
 USB 3.1
 Includes a faster transfer mode called SuperSpeed+
 This transfer mode achieves a signaling rate of 10 Gbps and a theoretical
usable data rate of 9.7 Gbps

 Is controlled by a root host controller which attaches to devices to

create a local network with a hierarchical tree topology
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+ FireWire Serial Bus
 Was developed as an alternative to small computer system interface
(SCSI) to be used on smaller systems, such as personal computers,
workstations, and servers
 Objective was to meet the increasing demands for high I/O rates
while avoiding the bulky and expensive I/O channel technologies
developed for mainframe and supercomputer systems
 IEEE standard 1394, for a High Performance Serial Bus
 Uses a daisy chain configuration, with up to 63 devices connected
off a single port
 1022 FireWire buses can be interconnected using bridges
 Provides for hot plugging which makes it possible to connect and
disconnect peripherals without having to power the computer
system down or reconfigure the system
 Provides for automatic configuration
 No terminations and the system automatically performs a
configuration function to assign addresses
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+
SCSI
 Small Computer System Interface
 A once common standard for connecting peripheral devices to
small and medium-sized computers
 Has lost popularity to USB and FireWire in smaller systems
 High-speed versions remain popular for mass memory support
on enterprise systems
 Physical organization is a shared bus, which can support up
to 16 or 32 devices, depending on the generation of the
standard
 The bus provides for parallel transmission rather than serial,
with a bus width of 16 bits on earlier generations and 32 bits
on later generations
 Speeds range from 5 Mbps on the original SCSI-1
specification to 160 Mbps on SCSI-3 U3

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+
Thunderbolt

 Most recent and fastest

peripheral connection
technology to become
available for general-
purpose use

 Developed by Intel with

collaboration from Apple
 Provides up to 10 Gbps
throughput in each
 The technology combines direction and up to 10
data, video, audio, and Watts of power to
power into a single high- connected peripherals
speed connection for
peripherals such as hard
drives, RAID arrays, video-
capture boxes, and network
interfaces
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+
InfiniBand
 I/O specification aimed at the high-end server market
 First version was released in early 2001
 Heavily relied on by IBM zEnterprise series of mainframes
 Standard describes an architecture and specifications for
data flow among processors and intelligent I/O devices
 Has become a popular interface for storage area
networking and other large storage configurations
 Enables servers, remote storage, and other network
devices to be attached in a central fabric of switches and
links
 The switch-based architecture can connect up to 64,000
servers, storage systems, and networking devices
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+
SATA
PCI Express

 Serial Advanced
 High-speed bus system for
Technology Attachment
connecting peripherals of a
wide variety of types and  An interface for disk
speeds storage systems

 Provides data rates of up

to 6 Gbps, with a
maximum per device of
300 Mbps

 Widely used in desktop

computers and in
industrial and embedded
applications

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+
Ethernet
 Predominant wired
networking technology
 Has moved from bus-based
 Has evolved to support data
to switch-based
rates up to 100 Gbps and
distances from a few meters  Data rate has periodically
to tens of km increased by an order of
magnitude
 Has become essential for  There is a central switch
supporting personal with all of the devices
computers, workstations, connected directly to the
servers, and massive data switch
storage devices in
organizations large and  Ethernet systems are
small currently available at
speeds up to 100 Gbps
 Began as an experimental
bus-based 3-Mbps system

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+ Wi-Fi  As the technology of
antennas, wireless
transmission techniques,
 Is the predominant wireless
and wireless protocol
Internet access technology
design has evolved, the
 Now connects computers, IEEE 802.11 committee
tablets, smart phones, and has been able to
other electronic devices such introduce standards for
as video cameras TVs and new versions of Wi-Fi at
thermostats higher speeds
 In the enterprise has become  Current version is
an essential means of 802.11ac (2014) with a
enhancing worker maximum data rate of 3.2
productivity and network Gbps
effectiveness

 Public hotspots have

expanded dramatically to
provide free Internet access in
most public places

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 Figure 7.20
IBM zEC12 I/O Frames-Front View

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+ Summary
Input/Output
Chapter 7
Interrupt-driven I/O
 External devices  Interrupt processing
 Keyboard/monitor  Design issues
 Disk drive  Intel 82C59A interrupt controller
 I/O modules  Intel 82C55A programmable
 Module function peripheral interface
 Direct Cache Access
 I/O module structure
 DMA using shared last-level
 Programmed I/O cache
 Overview of programmed I/O  Cache-related performance
 I/O commands/instructions issues
 Direct cache access strategies
 Direct memory access
 Direct data I/O
 Drawbacks of programmed
 I/O channels and processors
and interrupt-driven I/O
 The evolution of the I/O function
 DMA function
 Characteristics of I/O channels
 Intel 8237A DMA controller
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