MODULE V

MICROCONTROLLERS
Module-1(Evolution of microprocessors): 8085 microprocessor (-Basic Architecture only). 8086
microprocessor – Architecture and signals, Physical Memory organization, Minimum and maximum mode
of 8086 system and timings. Comparison of 8086 and 8088.Machine language Instruction format.

Module-2 (Addressing modes and instructions): Addressing Modes of 8086. Instruction set – data copy
/transfer instructions, arithmetic instructions, logical instructions, string manipulation instructions, branch
instructions, unconditional and conditional branch instruction, flag manipulation and processor control
instructions. Assembler Directives and operators. Assembly Language Programming with 8086.

Module- 3 (Stack and interrupts):

Stack structure of 8086, programming using stack- Interrupts - Types of Interrupts and Interrupt Service
Routine- Handling Interrupts in 8086- Interrupt programming. -
Programmable Interrupt Controller - 8259, Architecture (Just mention the control word, no need to
memorize the control word)- Interfacing Memory with 8086.

Module- 4 (Interfacing chips): Programmable Peripheral Input/output port 8255 - Architecture and modes
of operation- Programmable interval timer 8254-Architecture and modes of operation- DMA controller 8257
Architecture (Just mention the control word, no need to memorize the control word of 8254 and 8257)

Module- 5 (Microcontrollers): 8051 Architecture- Register Organization- Memory and I/O addressing-
Interrupts and Stack- 8051 Addressing Modes- Instruction Set- data transfer instructions, arithmetic
instructions, logical instructions, Boolean instructions, control transfer instructions- Simple programs.
MICROCONTROLLERS

Module- 5 (Microcontrollers): 8051 Architecture- Register

Organization- Memory and I/O addressing- Interrupts and Stack-
8051 Addressing Modes- Instruction Set- data transfer instructions,
arithmetic instructions, logical instructions, Boolean instructions,
control transfer instructions- Simple programs.
8051 Microcontroller
◦ A microcontroller is an integrated circuit (IC) that can be
programmed to perform a set of functions to control a
collection of electronic devices.
◦ Microprocessor is a single chip CPU, microcontroller
contains, a CPU and much of the remaining circuitry of a
complete microcomputer system in a single chip.
◦ Microcontroller includes RAM, ROM, serial and parallel
interface, timer, interrupt schedule circuitry (in addition
to CPU) in a single chip.
Micro controller Vs
Microprocessor
Computer System Vs Embedded System:
1)
◦ Microprocessor widely used in the computer
system. And microcontroller is used in embedded
system.
◦ If the microprocessor is the heart of computer
system then microcontroller is the heart of the
embedded system.
 MICROCONTROLLERS
2) Architecture:
◦ The microprocessor uses Von Neumann architecture where
data and program present in the same memory module .
◦ The microcontroller uses Harvard architecture. In this
module, data and program get stored in separate memory.
◦ The microcontroller can access data and program at the
same time as it is in a separate memory. This is one of the
reasons microcontrollers is faster than the microprocessor.
MICROCONTROLLERS

3) Memory and I/O Components:

◦ The microprocessor can not operate without peripheral
components. It has only processing unit and have to
attach all the required components externally to operate.
◦ Whereas micro control has small processing unit along
with internal memory to store and I/O components to
give input. So it can work independently.
How are Microcontrollers Classified ?
(Types of Microcontrollers)
MICROCONTROLLERS

The types of microcontroller is shown in figure, they are

characterized by their
◦ bits,
◦ memory architecture
◦ memory/devices
◦ and instruction set. .
Applications of Microcontrollers
Laptop components: mouse, keyboard, modem, fax card, sound card, battery
charger
Home appliances: door lock, alarm clock, thermostat, air conditioner, TV
remote, VCR, small refrigerator, exercise equipment, washer/dryer, microwave
oven
Industrial equipment: Temperature/pressure controllers, Counters, timers,
RPM
Controllers Toys: video games, cars, dolls, etc.
ARCHITECTURE
OF 8051
 8051 Features
The 8 bit CPU with Registers A and B
 Internal ROM
16-bit program counter(PC) and data pointer(DPTR)
 Internal RAM of 128 bytes
8-bit Program Status word(PSW)
Two 16 bit Counter / timers
 4 eight-bit ports
3 internal interrupts and 2 external interrupts.
Control register
 Oscillator and clock circuits.
A and B CPU Register
The 8051 contains 34 general purpose or working registers.
Two of these Register A and B.
The immediate result is stored in the accumulator register (Acc) for next
operation.
The B register is a register just for multiplication and division operation which
requires more register spaces for the product of multiplication and the quotient
and the remainder for the division.
Program status word(PSW)
The program status word shown in figure.
The PSW contain the math flags, User program flag F0,and the register select
bits that identify which of the four General-purpose register banks is currently in
use by the program.
The math flags include carry(c),auxiliary carry(AC), overflow(OV) and parity(p)
Program status word(PSW)
The 8051 oscillator and
clock
The 8051 requires an external oscillator circuit. The oscillator circuit usually
runs around 12MHz. The crystal generates 12M pulses in one second.
A machine cycle is minimum amount time must take by simplest machine
instruction
 An 8051 machine cycle consists of 12 crystal pulses (clock cycle).
The first 6 crystal pulses (clock cycle) is used to fetch the Opcode and the
second 6 pulses are used to perform the operation on the operands in the ALU.
This gives an effective machine cycle rate at 1MIPS (Million Instructions Per
Second).
Program counter (PC)

 The program counter points to the address of the next instruction to be

Executed
 As the CPU fetches the opcode from the program ROM, the program counter is
increasing to point to the next instruction.
 The program counter is 16 bits wide
 This means that it can access program addresses 0000 to FFFFH, a total of 64K
bytes of code
 Data pointer (DPTR)

The data pointer is 16 bit register.

It is used to hold the address of the data in the memory.
The DPTR register can be accessed separately as lower eight bit(DPL) and
higher eight bit (DPH).
It can be used as a 16 bit data register or two independent data register.
The stack and The stack
pointer (SP)

The stack is a section of RAM used by the CPU to store information temporarily
This information could be data or an address
 The register used to access the stack is called the SP (stack pointer) register
The stack pointer in the 8051 is only 8 bit wide.
Operation of stack
 Internal memory

128 bytes of RAM.

Directly addressable range:
00 to 7F hexadecimal.
Indirectly addressable range:
00 to FF hexadecimal.
Bit addressable space:
20 to 2F hexadecimal .
Four register banks:
00 to 1F hexadecimal.
Internal
Memory
 Internal
RAM
The 128 byte internal RAM shown in figure It is organized into three areas.

1.Working register:
Thirty-two bytes from address 00h to 1Fh that make up 32 working register organized as Four bank of
eight bit each.
Bits RS0 and RS1 in the PSW determine which bank of register is currently Is use.
Bank 0 is selected upon reset

2.Bit addressable:
A bit addressable area of 16 bytes occupies RAM bytes addresses 20h to 2Fh,forming A total of 128
addressable bits.
An addressable bit may be specified by its bit address of 00h to 7Fh.

3.General purpose:
A general-purpose RAM area above the bit area,form 30h to 7Fh,addresable as bytes.
Internal RAM
Organization

Sachin Bhalavat
(9409049436)
 External
memory

External memory is used in cases when the internal ROM

and RAM memory Available On chip is not sufficient. Two
separate are made available by the 16-bit PC and the DPTR
and by different control pins for enabling external ROM and
RAM chips.

If the 128 bytes of internal RAM is insufficient, the

external RAM is accessed by the DPTR. In the 8051
family, external RAM of upto 64 KB can be added to any
chip.
Special Function Register
(SFR)

The SFR (Special Function Register) can be accessed

by their names or by their addresses.
‰The SFR registers have addresses between 80H
and FFH.
Not all the address space of 80 to FF is used by SFR.

The unused locations 80H to FFH are reserved and

must not be used by the 8051 programmer.
There are 21 SFRs.
 Special Function
Register Map
Bit Addressable

F8 F0 E8 E0 D8
D0 C8 C0 B8 B0 B
A8 A0 98
90 ACC
88
80 PSW

IP
P3
IE
P2
SCON SBUF
P1
TCON TMOD TL0 TL1 TH0 TH1
P0 SP DPL DPH PCON
Special Function Register
(SFR)cont..
Special Function Register
(SFR)cont..

 128 byte address space, directly

addressable as 80 to FF hex.
 16 addresses are bit addressable:
(those ending in 0 or 8).

 This space contains:

Special purpose CPU registers. I/O

ports.
Interrupt control Timers
serial I/O
Special Function Register
(SFR)cont..
 CPU registers:
- ACC :
Accumulator.
- B : B register.
- PSW :
Program Status Word.
- SP : Stack
 Interrupt control: Pointer.
-IE - DPTR : :Data
Interrupt Enable.
Pointer (DPH, DPL).
-IP : Interrupt Priority.
 I/O Ports:
- P0 : Port 0.
- P1 : Port 1.
- P2 : Port 2.
- P3 : Port 3.
Special Function Register
(SFR)cont..
 Timers:
- TMOD: Timer mode.
- TCON : Timer control.
- TH0 : Timer 0 high byte.
- TL0 : Timer 0 low byte.
- TH1 : Timer 1 high byte.
- TL1 : Timer 1 low byte.
 Serial I/O:
- SCON: Serial port control.
- SBUF : Serial data registers.
 Other:
- PCON: Power control
 I/O
Ports

-Four 8-bit I/O ports.

Port 0
Port 1
Port 2
Port 3

-Most have alternate functions.

-Quasi-bidirectional:
 Port
0

- Port 0 is a dual purpose port, it is located from pin 32 to pin 39

(8 pins).

- To use this port as both input/output ports each pin must be

connected externally to pull-up resistor.
- As an I/O port.
- Alternate functions:
As a multiplexed data bus.
8-bit instruction bus, strobed by PSEN. Low byte of address bus,
strobed by ALE. 8-bit data bus, strobed by WR and RD.
 Port
1

- Port 1 is a dedicated I/O port from pin 1 to pin 8.

- Upon reset it is configured as outport.
- It is generally used for interfacing to external device
- thus if you need to connect to switches or LEDs, you could make use
of these 8 pins,
- but it doesn’t need any pull- up resistors as it is having internally
- As an I/O port: Standard quasi-bidirectional.
 Port
2

- Like port 0, port 2 is a dual-purpose port.(Pins 21 through 28)

- It can be used for general I/O or as the high byte of the address bus
for designs with external code memory.
- Like P1 ,Port2 also doesn’t require any pull-up resistors
- As an I/O port:
Standard quasi-bidirectional.
- Alternate functions:
High byte of address bus for externalprogram and data memory
accesses.
 Port
3
- Port 3 is also dual purpose but designers generally avoid using this
port unnecessarily for I/O because the pins have alternate
functions which are related to special features of the 8051.
- Indiscriminate use of these pins may interfere with the normal
operation of the 8051.
- As an I/O port:
Standard quasi-bidirectional.
- Alternate functions:
Serial I/O - TXD, RXD Timer clocks - T0, T1 Interrupts -
INT0, INT1 Data memory- RD, WR
 I/O Port
structure

 The internal circuitry for the I/O port is shown in

the figure
 If you want to read in from a pin, you must first
give a logic ‘1’ to the port latch to turn off the FET
otherwise the data read in will always be logic ‘0’.
 When you write to the port you are actually writing
to the latch e.g. a logic 0 given to the latch will be
inverted and turn on the FET which cause the port
pin to be connected to Gnd (logic 0).
I/O Port structure
Diagram

Sachin Bhalavat
(9409049436)
 Timer/
Counters

 Two 16-bit up counters, named T0 and T1, are provided for the general use
of the programmer.
 Each counter may be programmed to count internal clock pulses, acting as
a timer, or programmed to count external pulses as a counter.
 The counters are divided into two 8-bit registers called the timer low
(TL0,TL1) and high (TH0, TH1) bytes.
 All counter action is controlled by bit states in the timer mode control register
(TMOD), the timer/counter control register (TCON) and certain program
instructions.
 TMOD is dedicated to the two timers and can be consider two duplicate 4-bit
registers, each of which controls the action of the timers.
 TCON has control bits and flags for the timers in the upper control bits and
flags for the external interrupts in the lower nibble.
 Timer/
Counters(cont..)
 These timers exist in the SFR area as pairs of 8- bit registers.
– TL0 (8AH) and TH0 (8CH) for Timer0.
– TL1 (8BH) and TH1 (8DH) for Timer1. (LSB is bit 0 ; MSB is bit 7)

 When used as timers, the registers are incremented once per

machine cycle. – Each machine cycle is 12 clock cycles.

Count frequency = (system clock frequency) / 12

 When used as counters, the registers will be incremented once on

every 1-0 (negative edge) on the appropriate input pin.
• T0 – P3.4
• T1 – P3.5

 The pins must be held high for one complete machine cycle and then
low for one complete machine cycle.
Block
Schematic
 Timer/Counters:
Application

The timers can be used for:

1.Interval timing
The timer is programmed to overflow at a regular interval and set
the timer overflow flag. Overflow means reaching maximum
count of FFFFH.

2.Event counting
Determine the number of occurrences of an event. An event is
any external stimulus that provides a 1-to-0 transition on a pin of
the µC.
TCON (Counter/Timer Control
Register)

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

- TF1, TF0 : Overflow flags for Timer 1 and Timer 0.

- TR1, TR0 : Run control bits for Timer 1 and Timer 0.

Set to run, reset to hold.

- IE1, IE0 : Edge flag for external interrupts 1 and 0. *

Set by interrupt edge, cleared when interrupt is processed.

- IT1, IT0 : Type bit for external interrupts. *

Set for falling edge interrupts, reset for 0 level interrupts.

* = not related to counter/timer operation.

 TMO
D
GATE C/T M1 M0 GATE C/T M1 M0

Timer 1 Timer 0

-GATE : Permits INTx pin to enable/disable

counter.
-C/T : Set for counter operation, reset for timer
operation.
M1, M0 : Operating Mode select Bit 1/0.
Set/Cleared
M1 by
M0 Mode
program
0 to select
0 Mode
0
0 1 1
1 0 2
1 1 3
 Interrupt
System
 5 Interrupt Sources (in order of priority):
1 External Interrupt 0 (IE0)
2 Timer 0 (TF0)
3 External Interrupt 1 (IE1)
4 Timer 1 (TF1)
5 Serial Port (RI/TI)
 Each interrupt type has a separate
vector address.
 Each interrupt type can be programmed
to one of two priority levels.
 External interrupts can be programmed
for edge or level sensitivity.
Interrupt vector
Addresses
Source Address
IE0 03H
TF0 0BH
IE1 13H
TF1 1BH
RI&TI 23H

The 8051 starts execution at 0000H after

Reset.
IE : Interrupt Enable
Register

EA ---- ---- ES ET1 EX1 ET0 EX0

- EA : Global interrupt enable.

- ES : Enable serial port
interrupt
- ET1 : Timer 1.
- EX1 : External interrupt 1.
- ET0 : Timer 0.
- EX0 : External interrupt 0.

- 0 = Disabled.
- 1 = Enabled.
IP: Interrupt Priority
Register
----- ----- ----- PS PT1 PX1 PT0 PX0

- PS : Serial interface.
- PT1 : Timer 1.
- PX1 : External interrupt
1.
- PT0 : Timer 0.
- PX0 : External interrupt
0.

- 0 = Low priority.
- 1 = High priority.
Basics of serial
communication
Types of Serial
communications
 RxD and TxD pins in
the 8051
 The 8051 has two pins for transferring and
receiving data by serial communication. These
two pins are part of the Port3(P3.0 &P3.1)
 These pins are TTL compatible and hence they
require a line driver to make them RS232
compatible
 Serial communication is controlled by an 8-bit
register called SCON register, it is a bit
addressable register.
SCON : Serial Control
Register
SMO SM1 SM2 REN TB8 RB8 TI RI

- SM0, SM1 = Serial Mode:

00 = Mode 0 : Shift register I/O expansion.
01 = Mode 1 : 8-bit UART with variable baud rate.
10 = Mode 2 : 9-bit UART with fixed baud rate.
11 = Mode 3 : 9-bit UART with variable baud rate.
- SM2 : It enables the multiprocessor communication feature in
Mode 2 & Mode 3
-REN = Enables receiver.
-TB8 = Ninth bit transmitted (in modes 2 and 3).
-RB8 = Ninth bit received:
Mode 0 : Not used.
Mode 1 : Stop bit.
Mode 2,3 : Ninth data bit.
- TI = Transmit interrupt flag.
- RI = Receive interrupt flag.
 SM0 ,
SM1
 These two bits of SCON register determine the framing of data by specifying the numbe
bits per character and start bit and stop bits. There are 4 serial modes.

SM0 SM1
0 0 Serial Mode 0
0 1 Serial Mode 1, 8 bit data,
1 stop bit, 1 start bit
1 0 Serial Mode 2
1 1 Serial Mode 3
 REN
• REN (Receive Enable) also referred as SCON.4.
When it is high,it allows the 8051 to receive
data on the RxD pin. So to receive and transfer
data REN must be set to 1.When REN=0,the
receiver is disabled. This is achieved as below
SETB SCON.4 & CLR SCON.4
 TI ,
RI
• TI (Transmit interrupt) is the D1 bit of SCON register.
When 8051 finishes the transfer of 8-bit character, it
raises the TI flag to indicate that it is ready to
transfer another byte. The TI bit is raised at the
beginning of the stop bit.
• RI (Receive interrupt) is the D0 bit of the SCON
register. When the 8051 receives data serially ,via
RxD, it gets rid of the start and stop bits and places
the byte in the SBUF register. Then it raises the RI
flag bit to indicate that a byte has been received and
should be picked up before it is lost. RI is raised
halfway through the stop bit.
 Serial
Interface

 Full duplex UART.

 Four modes of operation:
1.Synchronous serial I/O expansion.
2.Asynchronous serial I/O with variable
baud rate.
3. Nine bit mode with variable baud rate.
4. Nine bit mode with fixed baud rate.
 10 or 11 bit frames.
 Registers:
SCON - Serial port control register. SBUF - Read
received data.
- Write data to be transmitted.
PCON - SMOD bit.
 Modes of
Operation
TXD and RXD are the serial output and input pins (Port 3,
bits 1 and 0).

Mode 0:
Shift Register Mode. Serial data is transmitted/received on
RXD. TXD outputs shift clock. Baud Rate is 1/12 of clock
frequency.

Mode 1:
10-bits transmitted or received. Start (0), 8 data bits (LSB
first), and a stop bit (1). Baud Rate Clock is variable using
Timer 1 overflow or external count input. Can go up to
104.2KHz (20MHz osc.).
 Addressing modes of 8051

In 8051 There are six types of addressing modes.

•Immediate Addressing Mode

•Register Addressing Mode
•Direct Addressing Mode
•Indirect Addressing Mode
•Indexed Addressing Mode
•Implied Addressing Mode
 Immediate addressing mode
•Data is provided in the instruction itself
•Data is provided immediately after the opcode

MOV A, #0AFH
MOV R3, #45H
MOV DPTR, #FE00H

• # symbol is used for immediate data

 Register addressing mode
•One of the operands must be accumulator and other
operand is any register R0 – R7

MOV A, R0
MOV R1, A

MOV R0, R4 ; Invalid instruction

 Direct Addressing Mode
•Source or destination address is specified by using
8-bit data in the instruction
•Only the internal data memory can be used in this mode
MOV A, 20H
MOV R2, 45H
MOV 20H, R1
MOV 21H, 05H
 Indirect addressing Mode
•Source or destination address is given in the register
•Internal or external addresses can be accessed
•R0 and R1 are used for 8-bit addresses, and DPTR is used
for 16-bit addresses, no other registers can be used for
addressing purpose

` MOV E5H, @R0

MOV @R1, 80H
•@ symbol is used for register indirect addressing
 Indexed addressing mode
•Source memory can only be accessed from program
memory only
•Destination operand is always the register A

MOVC A, @A+PC
MOVC A, @A+DPTR

• C in MOVC instruction refers to code byte

 Implied Addressing Mode
•There will be a single operand
•These types of instruction can work on specific registers
only
•These types of instructions are also known as register
specific instruction
RLA
SWAP A
•These are 1- byte instruction. The first one is used to
rotate the A register content to the Left. The second one is
used to swap the nibbles in A.
 8051 Microcontroller Instruction Set

• Types of Instructions in 8051 Microcontroller Instruction Set

• Before seeing the types of instructions, let us see the structure
of the 8051 Microcontroller Instruction. An 8051 Instruction
consists of an Opcode (short of Operation – Code) followed by
Operand(s) of size Zero Byte, One Byte or Two Bytes.
• The Op-Code part of the instruction contains the Mnemonic,
which specifies the type of operation to be performed. All
Mnemonics or the Opcode part of the instruction are of One
Byte size.
 8051 Microcontroller Instruction Set
• Coming to the Operand part of the instruction, it defines the data
being processed by the instructions. The operand can be any of the
following:
• No Operand
• Data value
• I/O Port
• Memory Location
• CPU register
• There can multiple operands and the format of instruction is as
follows:
•
 8051 Microcontroller Instruction Set
• MNEMONIC DESTINATION OPERAND, SOURCE OPERAND A simple
instruction
consists of just the opcode. Other instructions may include one
or more operands. Instruction can be one-byte instruction,
which contains only opcode, or two-byte instructions, where
the second byte is the operand or three byte instructions,
where the operand makes up the second and third byte.
• Based on the operation they perform, all the instructions in the
8051 Microcontroller Instruction Set are divided into five
groups. They are:
 8051 Microcontroller Instruction Set

• Data Transfer Instructions

• Arithmetic Instructions
• Logical Instructions
• Boolean or Bit Manipulation Instructions
• Program Branching Instructions
 8051 Microcontroller Instruction Set
• Data Transfer Instructions
• The Data Transfer Instructions are associated with transfer of
data between registers or external program memory or
external data memory. The Mnemonics associated with Data
Transfer are given below.
• MOV
• MOVC
• MOVX
• PUSH
• POP
• XCH
• XCHD
 8051 Microcontroller Instruction Set

Mnemonic Description

MOV Move Data

MOVC Move Code

MOCX Move External Data

PUSH Move Data to Stack

POP Copy Data from Stack

XCHD Exchange Data between two Registers

 8051 Microcontroller Instruction Set
• Arithmetic Instructions
• Using Arithmetic Instructions, you can perform addition, subtraction,
multiplication and division. The arithmetic instructions also include
increment by one, decrement by one and a special instruction called
Decimal Adjust Accumulator.
• The Mnemonics associated with the Arithmetic Instructions of the 8051
Microcontroller Instruction Set are:
• ADD
• ADDC
• SUBB
• INC
• DEC
• MUL
• DIV
• DA A
 Arithmatic Instructions
Mnemonic Description

ADD Addition without Carry

ADDC Addition with Carry

SUBB Subtract with Carry

INC Increment by 1

DEC Decrement by 1

MUL Multiply

DIV Divide

DA A Decimal Adjust the Accumulator (A Register)

 8051 Microcontroller Instruction Set
• Logical Instructions
• The next group of instructions are the Logical Instructions, which perform logical operations like
AND, OR, XOR, NOT, Rotate, Clear and Swap. Logical Instruction are performed on Bytes of data on
a bit-by-bit basis.
• Mnemonics associated with Logical Instructions are as follows:
• ANL
• ORL
• XRL
• CLR
• CPL
• RL
• RLC
• RR
• RRC
• SWAP
 Logical Instructions
Mnemonic Description

ANL Logical AND

ORL Logical OR

XRL Ex-OR

CLR Clear Register

CPL Complement the Register

RL Rotate a Byte to Left

RLC Rotate a Byte and Carry Bit to Left

RR Rotate a Byte to Right

RRC Rotate a Byte and Carry Bit to Right

 8051 Microcontroller Instruction Set
• Boolean or Bit Manipulation Instructions
• As the name suggests, Boolean or Bit Manipulation Instructions deal with bit variables. We know that there is
a special bit-addressable area in the RAM and some of the Special Function Registers (SFRs) are also bit
addressable.
• The Mnemonics corresponding to the Boolean or Bit Manipulation instructions are:
• CLR
• SETB
• MOV
• JC
• JNC
• JB
• JNB
• JBC
• ANL
• ORL
• CPL
 8051 Microcontroller Instruction Set
Mnemonic Description
CLR Clear a Bit (Reset to 0)
SETB Set a Bit (Set to 1)
MOV Move a Bit
JC Jump if Carry Flag is Set
JNC Jump if Carry Flag is Not Set
JB Jump if specified Bit is Set
JNB Jump if specified Bit is Not Set
JBC Jump if specified Bit is Set and also clear the Bit
ANL Bitwise AND
ORL Bitwise OR
CPL Complement the Bit
 8051 Microcontroller Instruction Set
• Program Branching Instructions
• The last group of instructions in the 8051 Microcontroller Instruction Set are the Program
Branching Instructions. These instructions control the flow of program logic. The mnemonics of the
Program Branching Instructions are as follows.
• LJMP
• AJMP
• SJMP
• JZ
• JNZ
• CJNE
• DJNZ
• NOP
• LCALL
• ACALL
• RET
• RETI,JMP
 8051 Microcontroller Instruction Set
Mnemonic Description
LJMP Long Jump (Unconditional)
AJMP Absolute Jump (Unconditional)
SJMP Short Jump (Unconditional)
JZ Jump if A is equal to 0
JNZ Jump if A is not equal to 0
CJNE Compare and Jump if Not Equal
DJNZ Decrement and Jump if Not Zero
NOP No Operation
LCALL Long Call to Subroutine
ACALL Absolute Call to Subroutine (Unconditional)
RET Return from Subroutine
RETI Return from Interrupt
 Addr16: 16-bit destination address for long call or long jump.
Rel: 2's complement 8-bit offset (one - byte) used for short jump (SJMP) and all
conditional jumps.
bit: Directly addressed bit in internal RAM or SFR
Arithmetic Instructions
Mnemonics Description Bytes Instruction Cycles

ADD A, Rn A A + Rn 1 1
ADD A, direct A A + (direct) 2 1
ADD A, @Ri A A + @Ri 1 1
ADD A, #data A A + data 2 1
ADDC A, Rn A A + Rn + C 1 1
ADDC A, A A + (direct) + C 2 1
direct
ADDC A, @Ri A A + @Ri + C 1 1

ADDC A, A A + data + C 2 1
#data
DA A Decimal adjust accumulator 1 1

DIV AB Divide A by B A quotient

B remainder 1 4

DEC A A A -1 1 1
 DEC Rn Rn Rn - 1 1 1
DEC direct (direct) (direct) - 1 2 1
DEC @Ri @Ri @Ri - 1 1 1
INC A A A+1 1 1
INC Rn Rn Rn + 1 1 1
INC direct (direct) (direct) + 1 2 1
INC @Ri @Ri @Ri +1 1 1
INC DPTR DPTR DPTR +1 1 2
MUL AB Multiply A by B A low byte (A*B)
B high byte (A* B) 1 4

SUBB A, Rn A A - Rn - C 1 1
SUBB A, A A - (direct) - C 2 1
direct
SUBB A, @Ri A A - @Ri - C 1 1
SUBB A, A A - data - C 2 1
#data Logical Instructions
Mnemonics Description Byte s Instruction Cycles

ANL A, Rn A A AND Rn 1 1
ANL A, direct A A AND (direct) 2 1
ANL A, @Ri A A AND @Ri 1 1
ANL A, #data A A AND data 2 1
ANL direct, A (direct) (direct) AND A 2 1

ANL direct, #data (direct) (direct) AND data 3 2

CLR A A 00H 1 1
CPL A A A 1 1
ORL A, Rn A A OR Rn 1 1
ORL A, direct A A OR (direct) 1 1
ORL A, @Ri A A OR @Ri 2 1
ORL A, #data A A OR data 1 1
ORL direct, A (direct) (direct) OR A 2 1

ORL direct, #data (direct) (direct) OR data 3 2

RL A Rotate accumulator left 1 1

RLC A Rotate accumulator left through carry 1 1

RR A Rotate accumulator right 1 1

RRC A Rotate accumulator right through carry 1 1

 SWAP A Swap nibbles within Acumulator 1 1

XRL A, Rn A A EXOR Rn 1 1
XRL A, direct A A EXOR (direct) 1 1
XRL A, @Ri A A EXOR @Ri 2 1
XRL A, #data A A EXOR data 1 1
XRL direct, A (direct) (direct) EXOR A 2 1

XRL direct, #data (direct) (direct) EXOR data 3 2

Data Transfer Instructions

Mnemonic s Description Byt es Instructi on Cycles

MOV A, Rn A Rn 1 1
MOV A, A (direct) 2 1
direct
MOV A, A @Ri 1 1
@Ri
MOV A, A data 2 1
#data
MOV Rn, A Rn A 1 1
MOV Rn, Rn (direct) 2 2
direct
MOV Rn, Rn data 2 1
#data
MOV direct, A (direct) A 2 1
MOV direct, Rn (direct) Rn 2 2
MOV (direct1) (direct2) 3 2
direct1, direct2
MOV direct, @Ri (direct) @Ri 2 2
MOV direct, #data (direct) #data 3 2
MOV @Ri, A @Ri A 1 1
MOV @Ri, @Ri (direct) 2 2
direct
MOV @Ri, @Ri data 2 1
#data
MOV DPTR, DPTR data16 3 2
#data16
MOVC A, @A+DPTR A Code byte pointed by A 1 2
+ DPTR
MOVC A, @A+PC A Code byte pointed by A 1 2
+ PC
MOVC A, A Code byte pointed by Ri 8-bit address) 1 2
@Ri
MOVX A, @DPTR A External data pointed by DPTR 1 2

MOVX @Ri, A @Ri A (External data - 8bit address) 1 2

MOVX @DPTR, A @DPTR A(External data - 16bit address) 1 2

PUSH (SP) (direct) 2 2

direct
POP direct (direct) (SP) 2 2
XCH Rn Exchange A with Rn 1 1
XCH direct Exchange A with direct byte 2 1

XCH @Ri Exchange A with indirect RAM 1 1

XCHD A, Exchange least significant nibble of A with that of 1 1

@Ri indirect RAM
Boolean Variable Instructions
Mnemonics Description Byte s Instruction Cycles

CLR C C-bit 0 1 1
CLR bit bit 0 2 1
SET C C 1 1 1
SET bit bit 1 2 1
CPL C C 1 1
CPL bit bit 2 1
ANL C, /bit C C. 2 1
ANL C, bit C C. bit 2 1
ORL C, /bit C C+ 2 1
ORL C, bit C C + bit 2 1
MOV C, bit C bit 2 1
MOV bit, C bit C 2 2

Program Branching Instructions

Mnemonics Description Byt es Instructi on Cycles

ACALL addr11 PC + 2(SP) ; addr 11 2 2

PC
AJMP addr11 Addr11 PC 2 2
CJNE A, direct, rel Compare with A, jump (PC + rel) if not 3 2
equal
CJNE A, #data, rel Compare with A, jump (PC + rel) if not 3 2
equal
CJNE Rn, Compare with Rn, jump (PC + rel) if not 3 2
#data, rel equal
CJNE @Ri, Compare with @Ri A, jump (PC + rel) if 3 2
#data, rel not
 equal

DJNZ Rn, rel Decrement Rn, jump if not zero 2 2

DJNZ direct, rel Decrement (direct), jump if not zero 3 2

JC rel Jump (PC + rel) if C bit 2 2

= 1
JNC rel Jump (PC + rel) if C bit 2 2
= 0
JB bit, rel Jump (PC + rel) if bit = 1 3 2

JNB bit, rel Jump (PC + rel) if bit = 0 3 2

JBC bit, rel Jump (PC + rel) if bit = 1 3 2

JMP @A+DPTR A+DPTR PC 1 2

JZ rel If A=0, jump to PC + rel 2 2

JNZ rel If A ≠ 0 , jump to PC + rel 2 2

LCALL addr16 PC + 3 (SP), addr16 3 2

PC
LJMP addr 16 Addr16 PC 3 2
NOP No operation 1 1
RET (SP) PC 1 2
RETI (SP) PC, Enable Interrupt 1 2
SJMP rel PC + 2 + rel PC 2 2

JMP @A+DPTR A+DPTR PC 1 2

JZ rel If A = 0. jump PC+ rel 2 2
JNZ rel If A ≠ 0, jump PC + rel 2 2
NOP No operation 1 1