PROJECT
FPGA DESIGN AND VERIFICATION
TITLE 25
BATCH:INTVL 13 V
Guide
Presented By
Vyasaraj
Ananya chowdappa gowda
CONTENTS 25
• Abstract
• Introduction to Synchronous DPRAM
• Block Diagram of Synchronous DPRAM
• Methodology
• Advantages
• Applications
• Conclusion
ABSTRACT 25
• This project focuses on the design and implementation of an 8-bit
wide, 16-location synchronous Dual Port RAM using Verilog HDL,
suitable for simulation and synthesis in Xilinx Vivado. Each port
supports independent read/write access, clock signals, and control
lines, allowing concurrent data transactions. A comprehensive
Verilog testbench is developed to verify the functionality and
correctness of the design through waveform analysis.
25
• In modern digital systems, efficient memory access and data handling
are critical for performance.
• Traditional single-port RAM allows either a read or write operation at
a given time.
• Dual Port RAM (DPRAM) is a type of memory that allows two
simultaneous memory accesses via two independent ports.
• Each port has its own address lines, data lines, control signals
(read/write), and clock, allowing parallel operations.
• It supports:Two independent read operations
Two independent write operations
One read and one write operation at the same time
25
Figure 1:Dual port RAM
Dual-port RAM is beneficial because it increases bandwidth, reduces design
complexity, and shortens time-to-market compared to alternative solutions.
BLOCK DIAGRAM 25
Figure2:Synchronous Dual Port RAM
METHODOLOGY 25
1. Clock Synchronization:
Both ports share a common clock signal, ensuring that all memory accesses are
synchronized.
2. Independent Ports:
Each port has its own address, data in, data out, read enable, and write enable
signals, allowing for independent control of each access.
3. Concurrent Access:
DPRAM allows simultaneous read or write operations on different memory
locations by the two ports.
4. Addressing and Data Transfer:
Each port can independently address and transfer data, with the clock signal
coordinating these operations.
5. Data Integrity:
DPRAM ensures data integrity by preventing access collisions, even when both
ports are accessing the same memory location.
WAVEFORMS 25
Figure 3:Waveforms of Synchronous
Dual Port RAM
SPECIFICATIONS
Specifications for Synchronous dual port RAM
Simulation Tools: Xilinx Vivado
Functional Specifications:
● Data Width: 8-bit (Input Data A & B)
● Address Width: 4-bit (16 memory locations)
● Operation: Independent Read/Write for each port
● Ports: Dual Port (Port A and Port B)
● Control Signals:
wr_ena, rd_ena (Port A)
wr_enb, rd_enb (Port B)
● Clock Input: Single Clock
● Output: 8-bit data from each port (douta, doutb)
● Supported Operations:
○ Port A: Read / Write
○ Port B: Read / Write (simultaneous and independent)
● Read Latency: 1 Clock Cycle
Verification and Testing:
Simulation: Verify functionality using Xilinx Vivado
ADVANTAGES 25
● Increased Bandwidth: Supports simultaneous read/write, doubling
data throughput.
● Simplified Design:Clock-based control reduces system complexity.
● Higher Speed:Synchronous access enables faster performance.
● Data Integrity:Ensures consistent data with dual access.
● Efficient Transfer:Enables smooth CPU-to-peripheral data flow.
APPLICATIONS 25
● Cellular Base Stations: Handle multiple calls and data streams at
once.
● Routers: Allow fast data processing by reading and writing at the
same time.
● Ethernet/ATM Networks: Ensure smooth data transfer between
components.
● Video Conferencing: Supports real-time video streaming without
lag.
● Image Processing: Helps in storing and editing images in areas like
surveillance and medical systems.
● Industrial Automation: Manages communication between sensors
and machines for smooth operations.
● Digital Signal Processing (DSP): Handles high-speed signal
operations.
● FPGA Systems: Used in programmable devices to manage memory
between modules efficiently.
CONCLUSION 25
This project successfully designed and implemented a Dual Port RAM
using Verilog for efficient simultaneous read and write operations. The
memory module is optimized for high-speed and reliable data access,
making it suitable for applications in embedded systems, networking, and
digital signal processing. Future enhancements could include expanding
memory size, adding error-checking features, or supporting more
advanced synchronization techniques.
THANK YOU FOR
CONSIDERATION !
