INTEL 80386 MICROPROCESSOR

INTEL 80386
MICROPROCESSOR
Presented By:
06 Annies Minu SathiyaSeelan
07 Arun Thomas
08 Uttara M Babrekar
09 Kaustubh Bari
10 Kunal Chaubal

INDEX
• Introduction.
• Features.
• Architecture.
• Applications.

• Two versions of 80386 are commonly available: 1)
80386DX 2)80386SX .
• 80386SX was developed after the DX for application
that didn’t require the full 32-bit bus version . It is
found in many PCs that same basic mother board
design is used as the 80286.Most application less
than the 16MB of memory ,so the SX is popular and
less costly version of the 80386 microprocessor.
INTRODUCTION

• Manufactured using Intel’s complementary High-
performance Metal-oxide-semiconductor 3 process.
• 8 general purpose registers of 32-bit .
• 32-bit Address and Data Bus.
• Supports 8 bit,16 bit,32 bit data.
• Prefetch queue of 16B.
• Very Large address space i.e VM of 64 TB and PM of
4GB.
• Supports Segmentation and Paging.
FEATURES

Continued….
• 4 levels of protection.
• Uses 3-stage pipelines.
• Supports multitasking with protection.
• On chip cache memory for TLB.
• Pipelined instruction Execution.
• Memory Management unit.
• High speed numeric support via 80287 and 80387
coprocessor.
• It can operate in real , protected and virtual mode.

ARCHITECTURE OF 80386
• The Internal Architecture of 80386 is divided into 3
sections.
1. Central processing unit(CPU)
2. Memory management unit(MMU)
3. Bus interface unit(BIU)

• Central processing Unit(CU):
1. Execution unit(EU)
2.Instruction unit(IU)
• Memory Management Unit(MMU):
1.Segmentation Unit
2.Paging Unit
• Bus Interface Unit(BIU):
Architect(Continue)….

• Execution unit has 8 General purpose and 8 Special
purpose registers which are either used for handling data
or calculating offset addresses.
• The Instruction unit consist of a Prefetch and Decode unit.
• The Instruction Prefetch unit is used to fetch instructions
in advance to implement pipelinig.
• While the Execution unit(EU) is executing the current
instruction the Prefetch unit fetches the next 16B of the
program & stores it into the Prefetch Queue.

• The Prefetch unit requests the Bus unit to fetch for
instructions & if at the same time the EU also requests
then priority is given to EU.
• While the EU is busy , the Instruction Decode unit
decodes the opcode bytes received from the 16-byte
instruction code queue and arranges them in a 3-
instruction decoded instruction queue.
• After decoding them pass it to the control section for
deriving the necessary control signals. The 64-bit barrel
shifter increases the speed of all shift and rotate
operations.

• The multiply / divide logic implements the bit-shift-rotate
algorithms to complete the operations in minimum time.
• Even 32- bit multiplications can be executed within one
microsecond by the multiply / divide logic.
• Execution of any program needs Arithmetic and logic
operations & this is performed by a 32-bit ALU .
• Operands for ALU can be taken from Register File which
contains all general purpose register.
• Additionally it has a 32-bit flag register. These flags give
status of the current result.

• A Protection Test Unit provides/gives protection to the
programs or instruction based on their Privilege.
(There are 4 privilege levels, Usually kernel of the OS code has
highest privilege or protection followed by OS services [2nd &
3rd level] & the lowest for applications.
For eg : Like for critical OS code & data can be protected by
keeping them in more privilege segment than those that
contains application code. This prevents application code from
accessing the OS code & data . It is usually used to detect
problems & bugs. Lets not go into detail.. )

• The Memory management unit consists of a Segmentation
unit and a Paging unit. It is used to determine the Physical
address from the Logical(virtual) address.
• 80386 microprocessor implements 64TB of virtual
memory using Segmentation and Paging . Hence the
Memory unit is subdivided into Segmentation unit and
Paging unit.
• Segmentation unit allows the use of two address
components, viz. segment and offset for relocability and
sharing of code and data.

• Segmentation unit allows segments of size 4Gbytes at
max.
• Paging unit works under the control of the segmentation
unit, i.e. each segment is further divided into pages. The
virtual memory is also organizes in terms of segments and
pages by the memory management unit.
• The Segmentation unit provides a 4 level protection
mechanism for protecting and isolating the system code
and data from those of the application program.

• Segmentation is compulsory , while Paging is optional.
• The Paging unit organizes the physical memory in
terms of pages of 4kbytes size each.
• The Segmentation unit converts the 48-bit Logical
Address(actually 46b,2b for protection) into 32-bit Physical
address while the Paging unit converts the 32-bit linear
address into 32-bit physical address.
• If paging is not used, then Linear address itself is the
Physical address.

• The control and attribute PLA checks the privileges at the
page level. Each of the pages maintains the paging
information of the task. The limit and attribute PLA checks
segment limits and attributes at segment level to avoid
invalid accesses to code and data in the memory segments.
• The Bus control unit has a prioritizer to resolve the priority
of the various bus requests. This controls the access of the
bus. The address driver drives the bus enable and address
signal A0 – A31. The pipeline and dynamic bus sizing unit
handle the related control signals.
• The data buffers interface the internal data bus with the
system bus.

APPLICATIONS
• The 80386 microprocessor is currently in use on several
spaceflight projects.
• Some mobile phones also used the 80386 processor, such
as BlackBerry 950 and Nokia 9000 Communicator.
• The 80386 is currently used in Hubble Space Telescope
(HST) and Solar Anomalous Magnetospheric Particle
Explorer (SAMPEX)

INTEL 80386 MICROPROCESSOR

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