15CS44 MP & MC Module 4

15CS44 Microprocessors &Micro-controllers
Kishore Kumar R RLJIT Page 1
Module-4
Microprocessors versus Microcontrollers
Topics
ARM Embedded Systems
4.1 RISC Design Philosophy
4.2 The ARM Design Philosophy
4.2.1 Instruction Set for Embedded Systems
4.3 Embedded System Hardware
4.3.1 ARM Bus Technology
4.3.2 AMBA Bus Protocol
4.3.3 Memory
4.3.3.1 Width
4.3.3.2 Types
4.3.4 Peripherals
4.3.4.1 Memory Controllers
4.3.4.2 Interrupt Controllers
4.4 Embedded System Software
4.4.1 Initialization (BOOT) Code
4.4.2 Operating System
4.4.3 Applications
ARM Processor Fundamentals
4.5 Registers
4.6 Current program Status Register
4.7 Pipeline
4.8 Exceptions, Interrupts and vector Table
4.9 Core Extensions

4.1 RISC Design Philosophy:
RISC philosophy is implemented with four major design rules
1. Instructions
2. Pipelining
3. Registers
4. Load / Store Architecture
Instructions:
• RISC has reduced number of instruction classes.
• Each instruction is executed in one clock cycle
• Compiler Synthesizes complicated operations by combining several simple instructions.
• Each instruction is fixed length instruction
Pipelining:
• Overlapping the execution of multiple instructions.
Registers:
• RISC has large general purpose register set
• Register can contain either address or data
Load/store architecture:
• The RISC processor operates on data in registers.
• Separate LOAD and STORE instruction are used to transfer data between register bank
and external memory.
Differences between CISC and RISC:
CISC RISC
Any instruction can access memory location Only LOAD & STORE instructions can access
memory location
Variable length Instructions Fixed length instructions
LESS registers MORE registers
Multi-clock cycle instructions Single-clock cycle instructions
Program code size small Program code size large
4.2 ARM Design Philosophy:
There are number of features of ARM Processor Design.
Battery Power: ARM processor is designed to consume less power and extend battery operation
High Code Density: High code density is main requirement since embedded systems have
limited memory.

Cost: Embedded Systems are price sensitive and use slow and low-cost memory devices, hence
ARM processor should be inexpensive.
Size: size of the ARM processor should be small, if processor occupies less space, more space
will be available for the peripherals.
Debugging: ARM has hardware debug technology within processor so that errors can be
resolved easily.
4.2.1 Instruction set for Embedded Systems:
ARM instruction set is different from pure RISC architecture in several ways. ARM instruction
set is suitable for embedded applications.
ARM Instruction set features are
Variable Cycle Execution for certain instructions: In ARM, not every instruction executes in
a single cycle.
Inline Barrel Shifter: It is hardware component that preprocesses one of the input registers
before it is used by an instruction.
Thumb 16-bit Instruction set: THUMB state allows ARM processor to execute the 16-bit
instructions.
Conditional execution:
• An instruction is only executed when a specific condition has been satisfied.
• This feature improves performance and code density.
Enhanced Instructions:
• Advanced instructions are added to ARM instruction set to support complex operations
• These instructions improve the performance and speed
4.3 Embedded System Hardware:
Embedded System has four main Hardware components
1. ARM Processor
2. Controllers
3. Peripherals
4. Bus
ARM processor:
• ARM processor controls the embedded system.
• Different versions of ARM processors are available for different applications.
• ARM processor has a core which executes the instructions and manipulates data.
• The surrounding components of the ARM interface with a bus.

Controllers:
 Controllers coordinate important functional blocks of the system.
 Two types of controllers are 1. Memory Controller 2. Interrupt Controller
Peripherals:
 Peripherals are input/output devices which are external to processor.
Bus: It is used to communicate between different parts of the device.
4.3.1 ARM Bus Technology:
 ARM Processors use on-chip bus that is internal to the processor.
 ARM bus is used to connect different peripherals devices to the processor.
 Two types of devices are connected to bus 1. Bus Master 2. Bus Slave
 Bus Master: Device capable of starting a data transfer with another device.
 Bus Slave: Device capable only of responding to a bus master
Bus Architecture Levels:
Bus has two architecture levels 1. Physical Level 2. Protocol
Physical level: it covers electrical characteristics and bus width.
Protocol: Rules that control the communication between processor and peripheral
4.3.2 AMBA (Advanced Microcontroller Bus Architecture) Bus Protocol:
 AMBA bus was introduced in 1996.
 First AMBA buses introduced were ASB (ARM system Bus) and APB (ARM peripheral
Bus). Later ARM introduced another bus called AHB (ARM high performance Bus)
 AHB provides higher data throughput than ASB , AHB runs at higher clock speeds and
supports widths of 64 and 128-bits
 There are two types of AHB bus 1. Multi-Layer AHB 2. AHB-Lite.
 Multi-Layer AHB Bus allows multiple active Bus masters, Multi-layer AHB Bus is used
in multiple processor systems.
 AHB-Lite Bus allows only one bus master.
4.3.3 Memory Hierarchy:
 All computer systems, memory is arranged in some form of hierarchy.
1. Cache
2. Main Memory
3. Secondary storage
The figure below shows the hierarchy of the memory.

Cache Memory:
 Cache memory is placed between main memory and core.
 It is used to speed up data transfer between processor and main memory.
 Cache improves overall performance.
Main Memory:
 Main memory is larger than cache memory.
 The size of memory is around 256KB to 256 MB or even greater.
 It is stored in separate chips.
 Load and Store instructions are used to access main memory.
Secondary Storage:
 Secondary storage is largest and slowest memory.
 Hard disk drives and CD-ROM drives are examples of secondary storage.
 Secondary storage memory size may vary from 600MB to 60 GB.
4.3.3.1 Memory Width:
 Memory width is number of bits the memory returns on each access.
 Memory width has direct effect on overall performance.
4.3.3.2 Memory Types:
 There are many different types of memory, the following are the popular memory devices
1. ROM
2. Flash ROM
3. DRAM
4. SRAM
5. SDRAM

ROM (Read only Memory):
 ROM is least flexible memory.
 It contains data which is stored at production time, it cannot be reprogrammed
 ROM is used to hold Boot-Code
Flash ROM:
 Flash ROM can be written to as well as read.
 It is used to hold device firmware.
 Erasing and writing of Flash ROM are completely software controlled
DRAM (Dynamic Random Access Memory):
 DRAM is inexpensive RAM
 DRAM needs to be refreshed every few milliseconds.
 DRAM controller refreshes the DRAM
SRAM (Static Random Access Memory):
 SRAM is faster than DRAM
 SRAM does not require refreshing
 SRAM is expensive
 SRAM is used for Cache memory.
SDRAM (Synchronous Dynamic Random Access Memory):
 SDRAM synchronizes itself with processor bus.
 SDRAM operates at higher clocker speeds.
4.3.4.1 Memory Controller:
 Memory controllers connect different types of memory to processor bus.
 On power-up, memory controller actives the memory device from which initialization
code is executed.
4.3.4.2 Interrupt Controller:
 Interrupt controller controls the interrupts requests of I/O devices
 There are two types of interrupt controllers 1. Standard Interrupt controller 2. Vector
Interrupt Controller

Standard Interrupt Controller:
 It sends an interrupt signal to the processor core when an external device request
servicing.
 Interrupt requests from individual or set of devices can be enabled or disabled
 Interrupt handler finds the device requires servicing by reading the register in interrupt
controller.
Vector Interrupt Controller:
 VIC is more powerful than standard interrupt controller.
 VIC prioritizes the interrupts and simplifies the determination of interrupting device.
 VIC forwards the interrupt signal to the core if the priority of a new interrupt is higher
than the currently executing interrupt handler.
4.4. Embedded System Software:
Embedded system needs four software components to control device
4.4.1 Initialization (Boot) code:
 Initialization code is the first code executed.
 Initialization code performs three tasks
1. Initial hardware configuration
2. Diagnostics
3. Booting
Initial Hardware configuration:
 Initial hardware configuration sets up target hardware so it can boot an operating system.
Diagnostics:
 Diagnostic code tests the target hardware to check whether it is in working order.
 The main purpose of diagnostic code is fault identification and isolation.
Application
Operating System
Initialization Device Drivers
Hardware Device

Booting:
 Booting loads an image (operating system code) to RAM and handing control over to that
image.
 Usually image is compressed, after booting the compressed image to RAM, it will be
decompressed.
4.4.2 Operating System:
 Operating system controls peripherals, memory and processing time.
 It allocates system resources to different applications.
 ARM processors supports over 50 operating systems, there are two types of operating
systems 1. RTOS (Real-Time Operating System) 2. Platform Operating Systems
RTOS:
 RTOS provides guaranteed response times to events.
 Hard real time application requires guaranteed response time.
 Systems running RTOS don not have secondary storage.
 E.g. SYMBIAN, ECOS
Platform operating system:
 It is used for non-real time applications.
 Platform operating systems have secondary storage, memory management unit is
required.
 Linux operating system is an example for platform operating system.
4.4.3 Applications:
 Code dedicated to perform particular task is called application code.
 An embedded system can have one or several active applications running simultaneously.
ARM Core Data Flow Model:
 All functional units of ARM are connected by data buses.
 ARM uses LOAD-STORE architecture.
 LOAD instruction copy data from memory to registers in processor
 STORE instruction copy data from registers to memory.
 There are no data processing instructions that directly manipulate data in memory. Data
processing is carried out only in registers.
 Rn and Rm are two source registers.
 Rd is destination register

Sign Extend Hardware: it converts the signed 8-bit and 16-bit numbers to 32-bit values
Instruction Decoder: it translates instructions before they are executed
Register File: it is a storage bank made up of 32-bit registers; registers are used to hold the data
ALU: takes register values Rn and Rm through A and B buses and computes the result and
stored in register Rd through result bus.
MAC (Multiply and Accumulate Unit): it takes register values Rn and Rm and computes the
result.
Barrel shifter: it is used to preprocess Rm which is one of the operands of the ALU
Address Register: it is used to hold the address of the memory location generated by ALU
Incrementer: it updates the address register to access the data from successive memory
locations.
4.5 Registers:

• General purpose registers hold either data or address.
• They are identified with letter ‘r’ prefixed to the register number.
• There are 18 active registers: 16 data registers and 2 processor status registers.
• The data registers visible to programmer as r0-r15
• r13, r14, r15 are assigned to a particular task or special function.
• r13 is used as stack pointer (SP) which points to top of the stack
• r14 is used as Link register (lr) which is used to hold the return address when subroutine
is called.
• r15 is used as program counter(PC) which contains the address of the next instruction.
4.6 Current Program Status Register:
• It is used to control internal operations
• CPSR is 32-bit register
• Shaded parts are reserved for future expansion
• CPSR is divided into four fields; each field has 8-bits, flags, status, extension, and
control.
• Control field contains processor mode, state and interrupt mask bits.
Processor Modes:
There are seven processor modes, six privileged mode, and one non-privileged mode
1. User mode
2. Fast interrupt request
3. Interrupt Request
4. Supervisor
5. Undefined
6. Abort

Abort mode: Processor enters Abort mode, when there is a failed attempt to access memory.
Supervisor mode: Operating system operates in supervisor mode.
System mode: It is special version of user mode, that allows full read-write access to CPSR.
Undefined Mode: It is used when processor encounters as instruction that is undefined.
User mode: It is used for programs and applications
Fast interrupt request & interrupt request mode: these mode are used when interrupt is
raised by the devices
Banked Registers:
• Figure below shows all 37 registers in register file.
• 20 registers are hidden registers or Banked registers, which are available only when
processor is in particular mode.
• Every mode except user mode can change mode by writing directly to the mode bits of
the cpsr.
• A banked register maps one-one onto a user mode register.
• If mode is changed, a banked register from new mode will replace existing register.

Mode Change from User-Mode to Interrupt-Request Mode:
• When an interrupt occurs due to an external device raising an interrupt to the processor
core, processor switches to interrupt request mode, this mode banks the user register r13,
r14, and user registers are replaced with r13_irq and r14_irq
• R13_irq contains stack pointer for interrupt request mode.
• R14_irq contains return address.
• The saved program status register (spsr) stores the previous mode’s CPSR
The figure below shows mode change from user mode to interrupt request mode.
State and Instruction Sets:
• Arm operates in three different states1. ARM State 2. Thumb State 3. Jazelle State
• ARM 32-bit instruction set is only active when processor is in ARM state.
• Thumb 16-bit instruction set is active when processor is in Thumb state.
• In Jazelle state, java byte codes can be executed.
• In CPSR, if J and T bits are zero, processor is in ARM state.
• When T=1, processor is in Thumb state, if J=1, processor is in Jazelle mode

Interrupt Masks:
• CPSR has 2 interrupt mask bits I and F, these bits are used to enable or disable two
interrupt request levels Interrupt request (IRQ) and Fast Interrupt Request (FIQ)
Condition Flags:
• Conditional flags are updated by the results of an instruction, if an instruction has ‘S’
suffix.
E.g. if SUBS instruction results in a register value of 0, then the Z flag in the cpsr is set.
Conditional Execution:
• An instruction is only executed when a specific condition is satisfied.
• The condition attribute is post-fixed to the instruction.
E.g. MOVEQ R0,R1 this instruction moves the R1 value to R0 only if ZF=1
The table below shows the conditional execution code mnemonics
In the above table, in condition flags column, capital letter indicates 1, lowercase letter indicates
0

4.7 Pipeline:
• A pipeline is a mechanism a RISC processor uses to execute instructions.
• Pipeline speeds up the execution by fetching the next instruction while other instruction
is being decoded and executed.
ARM three stage pipeline:
1. Fetch loads an instruction from memory
2. Decode identifies the instruction to be performed
3. Execute process the instruction and writes the result back to a register.
E.g.
In first cycle, the processor fetches ADD instruction from memory
In second cycle, the processor fetches SUB instruction and decodes the ADD instruction
In third cycle, ADD instruction is executed, SUB is Decoded, CMP is fetched
Below figures show ARM9 five –stage pipeline and ARM10 six-stage pipeline

Pipeline Executing Characteristics:
• An instruction gets executed only when it passes completely through execute stage.
E.g.
In the above example, MSR instruction is used to enable IRQ instructions, MSR instructions
enables the interrupt only when ADD instruction enters the execute stage of the pipeline.
In the Execute stage, PC (program counter) always points to address of the instruction being
executed plus two instructions ahead. In the above example, while LDR is getting executed PC
value is 0x8008
4.8 Exceptions, Interrupts, and the Vector Table
• When an exception or interrupt occurs, the processor makes PC to point to a particular
memory address, the address is within a special address range called vector table, the
instructions in vector table are branch instructions that jump to specific routines designed
to handle exception or interrupt.
• The memory address 0x00000000 is reserved for the vector table, in some processors the
address 0xffff0000 is used for vector table

The table below shows the interrupt vector table.
Reset Vector: it is location of first instruction executed by the processor when power is applied.
Undefined Instruction vector: it is used when processor cannot decode an instruction.
Software Interrupt Vector: it is used when you execute SWI instruction.
Prefetch abort Vector: it occurs when processor attempts to fetch an instruction from an
address without the correct access permissions.
Data abort vector: it occurs when an instruction attempts to access data in memory with out
correct access permissions.
Interrupt Request Vector: it is used by external hardware to interrupt the normal execution
flow of the processor.
Fast interrupt request Vector: it is similar to interrupt request but is reserved for hardware
requiring faster response times.
4.9 Core Extensions:
• Core extensions are the components placed next to the ARM core
• Core extensions improve performance, manage resources, and provide extra
functionality.
• There are three extensions
1. Cache
2. Tightly coupled memory (TCM)
3. Co-processor

Cache:
• Cache is memory placed between main memory and core.
• It improves overall performance of the processor by reducing number of main memory
access.
• ARM processors use single-level cache internal to the processor.
• ARM has two forms of cache
1. Von-Neumann-style cores
2. Harvard Style Cores
Von-Neumann Architecture cores:
• This architecture combines both data and instruction into a single Unified Cache as
shown in figure below.
• This technology is called glue logic that connects the memory system to the AMBA bus
logic and control.

Harvard Architecture with TCMs:
• Harvard architecture has separate caches for data and instructions.
• TCM is fast SRAM located close to core and guarantees the clock cycles required to
fetch instructions or data.
• TCMs appear as memory in the address map and can be accessed as fast memory.
Memory Management:
• ARM processors use three different types of memory management hardware
1. Non-Protected Memory
2. Memory Protection Unit (MPU)
3. Memory Management Unit (MMU)
Non-Protected Memory:
• It is fixed and provides very little flexibility
• It is used for small, simple embedded systems that requires no protection.
MPU:
• it uses limited number of memory regions
• These regions are controlled with a set of special coprocessor registers.
• MPU is used for systems that require memory protection but don’t have a complex
memory.
MMU:
• MMU uses a set of translation tables to provide control over memory.
• These tables are stored in main memory and provide virtual to physical address map.
• MMUs are designed for more sophisticated platform operating system that supports
multitasking.

Coprocessors:
• It is an extra processor attached to ARM processor.
• More than one coprocessor can be added to ARM using coprocessor interface.
• Coprocessor extends the instruction set by providing special group of new instructions.
• If the decoder sees a coprocessor instruction then it forwards it to coprocessor, if
coprocessor is not present then undefined instruction exception occurs.
Important Questions
1. Explain RISC Design Philosophy
2. Give Differences between CISC and RISC
3. Explain the feature of ARM Design Philosophy
4. Explain the ARM instruction set suitable for Embedded Systems
5. Briefly explain the embedded system Hardware with neat diagram.
6. Define i) Memory width ii) types of memory
7. Explain the different types of Interrupt Controllers
8. Explain the three phases of Initialization (Boot) code.
9. Explain about ARM registers available in user mode.
10. Explain CPSR with neat diagram
11. With an example explain how processor changes the mode from user mode to Interrupt
request mode.
12. With neat diagram briefly explain about banked Registers.
13. Explain ARM7 three-stage pipeline with an example.
14. Explain Von-Neumann Style core and Harvard style core
15. Explain different types of memory management units.
16. Define conditional execution and give an example.
17. Explain conditional flags and interrupt mask bits of the CPSR
18. Explain about ARM processor Modes and ARM States.

15CS44 MP & MC Module 4

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