Architecture Of TMS320C50 DSP Processor

Architecture Of TMS320C50 DSP Processor

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  TECHNICAL AND VOCATIONALEDUCATION AND TRAINING INSTITUTE Department of Electronics and Communication Technology Architecture of TMS320C50 DSP Processor PREPARED BY: - Tariku Mehdi Dec, 25, 2018 Addis Ababa, Ethiopia
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  Introduction A digital signalprocessor (DSP) is a specialized microprocessor designed specifically for digital signal processing, generally in real time computing. They contain special architecture and instruction set so as to execute computation- intensive DSP algorithms more efficiently. Some advanced microprocessors may have performances close to that of P-DSPs. However, in terms of low power requirements, cost, real time I/O compatibility and availability of high-speed on- chip memories, the P-DSPs have an advantage over the advanced microprocessors or RISC processors. The programmable DSPs (P-DSPs) can be divided into two broad categories. They are (i) General purpose DSPs and (ii) Special purpose DSPs. 1. General purpose DSPs: These are basically high speed microprocessors with architecture and instruction sets optimized for DSP operations. They include fixed point processors such as Texas instruments TMS320C5X, TMS320C54X and Motorola DSP563X and floating point processors such as Texas instruments TMS320C4X, TMS320C67XX, and analog devices ADSP21XXX. 2. Special purpose DSPs: This type of processors consists of hardware The factors that influence the selection of DSP for a given application are architectural features, execution speed, and type of arithmetic and word length. Some of the areas of the applications of P-DSPs are: communication systems, audio signal processing, control and data acquisition, biometric information processing, image/video processing, etc. In this seminar assignment we will discuss about Architecture of TMS320C50 on the following literature.
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  Architecture of TMS320C50 TheTMS320C5X generation of the Texas instruments TMS320C50 digital signal processor is fabricated with CMOS IC technology. It is a fixed point, 16-bit processor running at 40 MHz The single instruction execution time is 50 nsec. Its architectural design is based on the combination of advanced Harvard architecture, on-chip peripherals and on-chip memory. The TMS320C50 has a highly specialized instruction set. These features enable the operational flexibility and the device speed, which together with the cost effectiveness make the signal processor as the suitable device for a wide range of
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  applications. The TMS320C50has a programmable memory map which can vary for each application. On-chip memory includes 10K words of the RAM and 2K words of the ROM. All C5X DSPs have the same CPU structure. However, they have different on-chip memory configuration and on-chip peripherals. The functional block diagram of TMS320CX is shown in Figure. It can be divided into four sub blocks. They are: (1) Bus structure, (2) Central processing unit, (3) On- chip memory and (4) On-chip peripherals. 1. Bus structure Separate program and data buses in the advance Harvard architecture of C5X maximize the processing power and provide a high degree of parallelism. Many DSP applications are accomplished using single cycle multiply/accumulate instruction with a data move option. The C5X included the control mechanism to manage interrupts, repeated operations and function calling. The ‘C5X’ architecture has four buses: 1. Program bus (PB) 2. Program read bus (PRB) 3. Data read bus (DB) 4. Data read address bus (DRB) The program bus carries the instruction code and immediate operands from program memory to the CPU. The program address bus provides address to program memory space for both read and write. The data read bus interconnects various elements of the CPU to data memory space. The data read address bus provides the address to access the data memory space. 2. Central processing unit The CPU consists of the following elements: 1. Central arithmetic logic unit (CALU) 2. Parallel logic unit (PLU) 3. Auxiliary register arithmetic unit (ARAU) 4. Memory mapped registers 5. Program controller
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  2.1. Central ArithmeticLogic Unit(CALU) The CPU uses the CALU to perform 2’s complement arithmetic. It consists of the following: 1. Parallel multiplier (16 X 16 bit) 2. Accumulator (32 bit) 3. Accumulator buffer (ACCB) (32 bit) 4. Product register (PREG) 5. Shifters 6. Arithmetic logic unit (ALU) All 32 bit signed/unsigned multiplication operations can be performed in parallel multiplier within one machine cycle. All multiply instructions except the MPYU (multiply unsigned) instruction perform a signed multiply operation in the multiplier. One of the operands to the multiplier is from the 16-bit temporary register O (TREGO) and the second input is from the program bus or data bus. The product register (PREG) holds the product. The 32 bit ALU along with 16-bit accumulator carries out arithmetic and logic operations executing most of them in one machine cycle. Here the accumulator provides one of the inputs to the ALU, whereas the product register, accumulation buffer, or scaling shifter output provides the second input. The results of operations performed in ALU are stored in accumulator. The scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifters produce a left shift of 0 to 16 bits on the input data. A 5-bit register TREGI specifies the number of bits by which the scaling shifter should shift or the shift count is specified by a constant embedded in the instruction word. 2.2. Parallel logic unit (PLU) The parallel logic unit (PLU) is another logic unit that executes logic operations on data without affecting the contents of the accumulator. The multiplier bit in a status/control register or any memory location can be directly set, clear, test or toggled by the PLU. After executing the logical operation, the PLU writes the result of the operation to the same memory location from which the first operand was fetched. 2.3. Auxiliary register arithmetic unit (ARAU) The C5X consists of a register file containing eight auxiliary registers (ARO-AR7) each of 16-bit length, a 3-bit auxiliary register pointer (ARP) and an unsigned 16 bit ALU. The auxiliary register file is connected to the auxiliary register arithmetic unit.
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  2.4. Memory MappedRegisters The C5X has 96 registers mapped into page 0 of the data memory space. This memory mapped register space contains various controls and status registers including those for CPU, serial port, timer and software wait generators. Additionally, the first sixteen I/O port locations are mapped into this data memory space, allowing them to be accessed either as data memory using single word instruction or as I/O locations with two-word instruction. 2.5. Program Controller The program controller contains logic circuitry that decodes the operational instructions, manages the CPU pipeline, stores the status of CPU operation and decodes the conditional operations. It consists of the following elements: (i) Program counter (PC) (ii) Status and control registers (iii) Hardware stack iv) Program memory addresses generation (v) Instruction registers 3. On-Chip Memory The C5X structure has a total memory address range of 224K words _ 16 bits. The memory space is divided into four memory segments.  64K word program memory space: It contains the instruction to be executed.  64K word local data memory space: It stores data used by the instruction.  64K word input/output ports: It interfaces to external memory mapped peripherals.  32K word global data memory space: It can share data with other peripherals within the system. The large on-chip memory of C5X includes: 1. Program read only memory 2. Data/Program single access RAM (SARAM) 3. Data/Program dual access RAM (DARAM)
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  4. On-Chip peripherals AllC5X DSPs have the same CPU structure; however, they have different on-chip peripherals connected to their CPUs. A TMS320C50 digital signal processor contains the following on-chip peripherals. 1. Clock generator 2. Hardware timer 3. Software programmable wait stage generators 4. General purpose I/O pins 5. Parallel I/O ports 6. Serial port interface 7. Buffered serial port 8. TDM serial port 9. Host port interface 10. User-maskable interrupts Summary The DSP processors available on the market today vary drastically in their ability to meet the five key requirements of DSP processing. In fact, some DSP-oriented processors, like the TMS320C50, are better high-speed microcontrollers than they are DSP processors. Analyzing the requirements of your DSP system and matching them to the capabilities of a DSP architecture will assure efficient operation. Overall the straightforward architecture and the algebraic syntax of the instruction set for the ADSP-2115 processor allows the programmer to spend more time concentrating on a complex DSP algorithm instead of spending time optimizing code for an unnecessarily complex architecture.
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  Reference 1. Digital SignalProcessing, A. Anand Kumar, 2013 2. Considerations for Selecting a DSP Processor (ADSP-2115 vs. TMS320C5x), One technology way, Norwood, Masachuset. 3. Datasheet TMS320C50 Texas Instrument SPRS030A April 1995 revised April 1996.