![• B<address> provides a branch relative from the pc.
• LDR pc, [pc, #offset]—This load register instruction
loads the handler address from memory to the pc.
• LDR pc, [pc, #-0xff0]—This load register instruction
loads a specific interrupt service routine address from
address 0xfffff030 to the pc.
• MOV pc, #immediate—This move instruction copies
an immediate value into the pc.
MOV pc, #immediate](https://image.slidesharecdn.com/exceptionandinterruptsarm-190907075203/85/ARM-Exception-and-interrupts-4-320.jpg)
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ARM Exception and interrupts
- 1. ARM Exceptions & ARM Interrupt Controller 1
- 2. Mapping exceptions to modes 2 Exception Condition that needs to halt the normal sequential execution of instructions
- 3. 3 Figure: ARM Vector table Exception Priority:
- 4. • B<address> provides a branch relative from the pc. • LDR pc, [pc, #offset]—This load register instruction loads the handler address from memory to the pc. • LDR pc, [pc, #-0xff0]—This load register instruction loads a specific interrupt service routine address from address 0xfffff030 to the pc. • MOV pc, #immediate—This move instruction copies an immediate value into the pc. MOV pc, #immediate
- 5. RESET: Happens when the processor powers up. Initializes the system, sets up stacks for different processor modes. Highest priority exception Upon entry into the reset handler the CPSR is in SVC mode and both IRQ and FIQ bits are set to 1, masking any interrupts DATAABORT: 2nd highest priority. Happens when we try to read/write into an invalid address or access with the wrong access permission. Upon entry into the Data Abort Handler, IRQ’s will be disabled (I-bit set 1), and FIQ will be enabled (F-bit set 0). FIQ: Highest priority interrupt IRQ & FIQs are disabled till FIQ is handled. 5
- 6. 6 IRQ: 2nd Highest priority interrupt IRQ handler is entered only if there is no FIQ & Data Abort on-going. Undefined Instruction: Undefined Instruction exception occurs when an instruction not in the ARM or Thumb instruction set reaches the execute stage of the pipeline and none of the other exceptions have been flagged Same priority as SWI as one can happen at a time. Meaning as the instruction being executed cannot both be an SWI instruction and an undefined instruction at the same time. Pre-Fetch Abort: Similar to data abort, but happens on address fetch failure. On entry to the handler, IRQs are disabled, but FIQs remain enabled and can happen during a Pre-Fetch abort. SWI: A Software Interrupt (SWI) exception occurs when the SWI instruction is executed and none of the other higher- priority exceptions have been flagged.
- 7. • saves the cpsr to the spsr of the exception mode • saves the pc to the lr of the exception mode • sets the cpsr to the exception mode • sets pc to the address of the exception handler CPSR LR.exp SPSR.exp PC PC CPSR User mode Exception mode ARM Exception handling Return from Exception:
- 8. 8 Locating the offending instruction:
- 9. This example shows that a typical method of returning from an IRQ and FIQ handler is to use a SUBS instruction: handler <handler code> ... SUBS pc, r14, #4 ; pc=r14-4 Because there is an S at the end of the SUB instruction and the pc is the destination register, the cpsr is automatically restored from the spsr register. This example shows another method that subtracts the offset from the link register r14 at the beginning of the handler. handler SUB r14, r14, #4 ; r14-=4 ... <handler code> ... MOVS pc, r14 ; return After servicing is complete, return to normal execution occurs by moving the link register r14 into the pc and restoring cpsr from the spsr.
- 10. The final example uses the interrupt stack to store the link register. This method first subtracts an offset from the link register and then stores it onto the interrupt stack. handler SUB r14, r14, #4 ; r14-=4 STMFD r13!,{r0-r3, r14} ; store context ... <handler code> ... LDMFD r13!,{r0-r3, pc}ˆ ; return To return to normal execution, the LDM instruction is used to load the pc. The ˆ symbol in the instruction forces the cpsr to be restored from the spsr.
- 11. ARM Interrupt handling 11 Interrupts SWI instructionIRQ and FIQ • Software Interrupts are normally reserved to call privileged operating system routines. Eg: Change a program running in user mode to a privileged mode. • Interrupt Requests are normally assigned for general-purpose interrupts. IRQ exception has a lower priority and higher interrupt latency • Fast Interrupt Requests are normally reserved for a single interrupt source that requires a fast response time
- 12. The interval of time from an external interrupt request signal being raised to the first fetch of an instruction of a specific interrupt service routine (ISR). Two main methods to minimize interrupt latency • use a nested interrupt handler - achieved by re-enabling the interrupts as soon as the interrupt source has been serviced but before the interrupt handling is complete. • Prioritization - ignore interrupts of the same or lower priority than the interrupt you are handling, so only a higher-priority task can interrupt your handler. Interrupt latency
- 13. • When an IRQ occurs, the processor moves into state 2. • Sets the IRQ =1, disabling any further IRQ exceptions. • FIQ has a higher priority and therefore doesn't get disabled when a low-priority IRQ exception is raised. • The cpsr processor mode changes to IRQ mode. • spsr_irq = cpsr. • PC = r14_irq. • pc = IRQ entry +0x18 in the vector table. • In state 3 the software handler takes over • Upon completion, the processor mode reverts back to the original user mode code in state 1. Interrupt request IRQ Figure: State-Machine for an IRQ
- 14. Interrupt request FIQ • In state 3 the software handler takes over • Upon completion, the processor mode reverts back to the original user mode code in state 1. • FIQ is ideal for servicing a single-source, high-priority, low-latency interrupt. • When an FIQ occurs, the processor moves into state 2. • Sets the IRQ =1 and FIQ =1, disabling any further IRQ and FIQ exceptions. • The cpsr processor mode changes to FIQ mode. • No need to save registers r8 to r12 • spsr_fiq = cpsr. • r14_fiq = pc. • pc = FIQ entry +0x1C in the vector table.
- 15. The immediate value on the data processing BIC or ORR instruction has to be changed to 0xc0 to enable or disable both interrupts.
- 16. Stack memory layout The main advantage of layout B over A is that B does not corrupt the vector table when a stack overflow occurs, and so the system has a chance to correct itself when an overflow has been identified.
- 17. Supervisor mode stack LDR r13, SVC_NewStack ; r13_svc ... SVC_NewStack DCD SVC_Stack IRQ mode stack MOV r2, #NoInt|IRQ32md MSR cpsr_c, r2 LDR r13, IRQ_NewStack ; r13_irq ... IRQ_NewStack DCD IRQ_Stack NoInt EQU 0xc0 ; Disable interrupt User mode stack MOV r2, #Sys32md MSR cpsr_c, r2 LDR r13, USR_NewStack ; r13_usr ... USR_NewStack DCD USR_Stack
- 18. Non-nested Interrupt Handler • The interrupts are disabled until control is returned back to the interrupted task or process. • Can service only a single interrupt at a time. 1. Disable interrupt/s—When the IRQ exception is raised, the ARM processor will disable further IRQ exceptions from occurring. 2. Save context—On entry the handler code saves a subset of the current processor mode non banked registers. 3. Interrupt handler—The handler then identifies the external interrupt source and executes the appropriate interrupt service routine (ISR). 4. Interrupt service routine—The ISR services the external interrupt source and resets the interrupt. 5. Restore context—The ISR returns back to the interrupt handler, which restores the context. 6. Enable interrupts— pc = lr−4 cpsr = spsr_{mode}
- 19. What happens when an exception happens? 1. Store the CPSR to the SPSR of the exception mode. 2. PC is stored in the LR of the exception mode. 3. Link register is set to a specific address based on the current instruction.. For e.g. for ISR, LR = last executed instruction + 8 4. Update the CPSR about the exception 5. Set the PC to the address of the exception handler. 19
Editor's Notes
- #3: FIQ: Fast Interrupt Requests are normally reserved for a single interrupt source that requires a fast response time—for example, direct memory access specifically used to move blocks of memory
- #6: Undefined Instruction: The ARM processor “asks” the coprocessors if they can handle this as a coprocessor instruction. Since coprocessors follow the pipeline, instruction identification can take place in the execute stage of the core. If none of the coprocessors claims the instruction, an Undefined Instruction exception is raised
- #20: 1. It is important to understand the compiler’s procedure calling convention because it will influence both the registers saved and the order they are saved onto the stack. 2. ARM compilers preserves registers r4 to r11 within a subroutine call so there is no need to preserve them unless they will be used by the interrupt handler. 2. It is safe to call a C function only when the registers have been saved onto the interrupt stack. Why do we have to correct the LR on entry to the ISR? Due to the pipelined nature of ARM whenever an IRQ happens the LR will be pointing to current instruction+4. So on entry to the ISR we need to adjust the IRQ_LR to point to the correct instruction.