Chip specification

Final Project
System on Chip Specification
TramelBlaze, UART & MIB
CECS 460: System on Chip Design
Paul Valenzuela
018469189
Submitted On:
May 12, 2020
COLLEGE OF ENGINEERING
Department of Computer Engineering and Computer Science

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Paul Valenzuela
Date:
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Document Name:
Final Specification
This document contains information proprietary to the CSULB
student that created the file – any reuse without adequate approval and
documentation is prohibited.
In submitting this file for class work at CSULB I am confirming that this is
my work and the work of no one else.
In the event, other sources are utilized I will document
which portion of code and who is the author.
In submitting this project, I acknowledge that plagiarism in student
project work is subject to dismissal from the class.
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TABLE OF CONTENTS
I. INTRODUCTION.................................................................................................................................... 6
I.1 PURPOSE ............................................................................................................................................. 6
II. EXTERNAL DOCUMENTS.................................................................................................................. 7
II.1 TRAMELBLAZE ................................................................................................................................ 7
II.1.1 Detailed Block Diagram ............................................................................................................... 7
II.1.2 Data Transmission........................................................................................................................ 8
II.1.3 Instructions ................................................................................................................................... 9
II.1.4 Software Design.......................................................................................................................... 10
II.2 NEXYS A7 ........................................................................................................................................ 11
II.2.1 Hardware.................................................................................................................................... 11
II.2.2 Input / Output.............................................................................................................................. 12
II.2.3 UART Configuration................................................................................................................... 12
III. REQUIREMENTS............................................................................................................................... 13
III.1 INTERFACE......................................................................................................................................... 13
III.2 PHYSICAL .......................................................................................................................................... 14
IV. TOP LEVEL DESIGN......................................................................................................................... 15
IV.1 DESCRIPTION..................................................................................................................................... 15
IV.2 TOP LEVEL DIAGRAM........................................................................................................................ 15
IV.3 DETAILED LEVEL DIAGRAM.............................................................................................................. 16
IV.4 DATA FLOW DESCRIPTION ................................................................................................................ 17
IV.5 INPUT / OUTPUT................................................................................................................................. 17
IV.6 PIN ASSIGNMENT............................................................................................................................... 18
IV.7 ELECTRICAL CHARACTERISTICS........................................................................................................ 18
IV.8 CLOCK .............................................................................................................................................. 18
IV.9 RESET................................................................................................................................................ 18
IV.10 SOFTWARE....................................................................................................................................... 19
V. EXTERNALLY DEVELOPED BLOCKS .......................................................................................... 30
V.1AISO................................................................................................................................................... 30
V.1.1 Description.................................................................................................................................. 30
V.1.2 Top Level Diagram...................................................................................................................... 30
V.1.3 Input / Output.............................................................................................................................. 30
V.1.4 Register Map ............................................................................................................................... 30
V.2 TRAMELBLAZE................................................................................................................................... 31
V.2.1 Description.................................................................................................................................. 31
V.2.2 Top Level Diagram...................................................................................................................... 31
V.2.3 Input / Output.............................................................................................................................. 31
V.2.4 Register Map ............................................................................................................................... 31
VI. INTERNALLY DEVELOPED BLOCKS.......................................................................................... 32
VI.1 MEMORY BLOCK INTERFACE ............................................................................................................ 32
VI.1.1 Description................................................................................................................................. 32
VI.1.2 Top Level Diagram .................................................................................................................... 32
VI.1.3 Input / Output............................................................................................................................. 33
VI.1.5 Register Map.............................................................................................................................. 33
VI.1.5 State Machine ............................................................................................................................ 34
VI.2 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER............................................................ 35
VI.2.1 Description................................................................................................................................. 35
VI.2.3 Detailed Level Diagram............................................................................................................. 36
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VI.2.4 Input / Output............................................................................................................................. 37
VI.3 TRANSMIT ENGINE ............................................................................................................................ 38
VI.3.1 Description................................................................................................................................. 38
VI.3.4 Verification ................................................................................................................................ 39
VI.3.5 Input / Output............................................................................................................................. 40
VI.3.6 Register Map.............................................................................................................................. 40
VI.4 TRANSMIT SHIFT REGISTER............................................................................................................... 41
VI.4.1 Description................................................................................................................................. 41
VI.4.3 Input / Output............................................................................................................................. 41
VI.5 TRANSMIT BIT10 BIT9 DECODER ...................................................................................................... 42
VI.5.1 Description................................................................................................................................. 42
VI.5.3 Input / Output............................................................................................................................. 42
VI.5.4 Logic Table ................................................................................................................................ 42
VI.6 TRANSMIT CONTROLLER................................................................................................................... 43
VI.6.1 Description................................................................................................................................. 43
VI.6.3 Input / Output............................................................................................................................. 43
VI.7 TRANSMIT BIT COUNTER................................................................................................................... 44
VI.7.1 Description................................................................................................................................. 44
VI.7.3 Input / Output............................................................................................................................. 44
VI.8 TRANSMIT BIT TIME COUNTER.......................................................................................................... 45
VI.8.1 Description................................................................................................................................. 45
VI.8.3 Input / Output............................................................................................................................. 45
VI.9 RECEIVE ENGINE ............................................................................................................................... 46
VI.9.1 Description................................................................................................................................. 46
VI.9.4 Verification ................................................................................................................................ 47
VI.9.5 Input / Output............................................................................................................................. 48
VI.9.6 Register Map.............................................................................................................................. 48
VI.10 RECEIVE SHIFT REGISTER................................................................................................................ 49
VI.10.1 Description............................................................................................................................... 49
VI.10.2 Top Level Diagram .................................................................................................................. 49
VI.10.3 Input / Output........................................................................................................................... 49
VI.11 RECEIVE STATE MACHINE............................................................................................................... 50
VI.11.1 Description............................................................................................................................... 50
VI.11.3 State Transition Diagram......................................................................................................... 50
VI.11.4 Input / Output........................................................................................................................... 50
VI.12 RECEIVE CONTROLLER.................................................................................................................... 51
VI.12.1 Description............................................................................................................................... 51
VI.12.3 Input / Output........................................................................................................................... 51
VI.13 RECEIVE BIT COUNTER ................................................................................................................... 52
VI.13.1 Description............................................................................................................................... 52
VI.13.3 Input / Output........................................................................................................................... 52
VI.13.4 Logic Table .............................................................................................................................. 52
VI.14 RECEIVE BIT TIME COUNTER .......................................................................................................... 53
VI.14.1 Description............................................................................................................................... 53
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VI.14.3 Input / Output........................................................................................................................... 53
VI.15 BAUD RATE DECODER..................................................................................................................... 54
VI.15.1 Description............................................................................................................................... 54
VI.15.3 Input / Output........................................................................................................................... 54
VI.15.3 Register Map............................................................................................................................ 54
VI.16 POSITIVE EDGE DETECT .................................................................................................................. 55
VI.16.1 Description............................................................................................................................... 55
VI.16.3 Input / Output........................................................................................................................... 55
VI.16.4 Register Map............................................................................................................................ 55
VI.17 RS FLOP .......................................................................................................................................... 56
VI.17.1 Description............................................................................................................................... 56
VI.17.3 Input / Output........................................................................................................................... 56
VI.17.4 Register Map............................................................................................................................ 56
VI.18 READ ADDRESS DECODE................................................................................................................. 57
VI.18.1 Description............................................................................................................................... 57
VI.18.3 Input / Output........................................................................................................................... 57
VI.18.4 Register Map............................................................................................................................ 57
VI.19 WRITE ADDRESS DECODE ............................................................................................................... 58
VI.19.1 Description............................................................................................................................... 58
VI.19.3 Input / Output........................................................................................................................... 58
VI.19.4 Register Map............................................................................................................................ 58
VII. CHIP LEVEL VERIFICATION....................................................................................................... 59
VII.1 TRANSMIT ENGINE........................................................................................................................... 59
VII.2 UART ENGINE................................................................................................................................. 60
VIII. APPENDIX........................................................................................................................................ 62
VIII.1 AISO.............................................................................................................................................. 62
VIII.2 TRAMELBLAZE-TOP ....................................................................................................................... 63
VIII.3 UART............................................................................................................................................. 65
VIII.4 UART DECODE .............................................................................................................................. 67
VIII.5 TRANSMIT ENGINE.......................................................................................................................... 68
VIII.6 RECEIVE ENGINE ............................................................................................................................ 71
VIII.7 ADDRESS DECODE .......................................................................................................................... 75
VIII.8 POSITIVE EDGE DETECT.................................................................................................................. 76
VIII.9 RS FLOP.......................................................................................................................................... 77
VIII.10 SEVEN SEGMENT DISPLAY DRIVER............................................................................................... 78
VIII.11 ANODE SHIFT REGISTER ............................................................................................................... 79
VIII.12 ROTATOR...................................................................................................................................... 80
VIII.13 SELECT 2 BIT ................................................................................................................................ 81
VIII.14 MULTIPLEXOR 4 TO 1.................................................................................................................... 82
VIII.15 HEX DECODER.............................................................................................................................. 83
VIII.16 TRAMELBLAZE ............................................................................................................................. 95
VIII.17 MEMORY INTERFACE BLOCK...................................................................................................... 103
VIII.18 TOP LEVEL MODULE................................................................................................................... 107
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I. Introduction
The Chip Specification document explains the Universal Asynchronous Receiver Transmitter (UART)
data transmission module and Memory Interface Block (MIB) memory manager module as used in a terminal
communication project. The transmit engine and receive engine work together to communicate the SOPC with
the terminal. ASCII values are output to the terminal, and sent from the terminal to be interpreted by the
TramelBlaze. These engines combined form the UART engine. In addition, A Memory Interface Block gives
the TramelBlaze the ability to access Micron Memory from the Nexys A7.
I.1 Purpose
This project was essential in understanding how the Transmit and Receive engine of UART
data transmission worked. This meant input can be put into the terminal and data was output back
out and displayed on the terminal. In addition, this project was the first time a Memory
Interface Block was used to manage the memory addresses and data that communicated with
the Micron Memory. This document will go in depth about what each module within the project does.
This includes top level diagrams, a description, details on the I/O ports, logic tables, and
register map tables. A chip level test is then added at the end to indicate that the project
fulfilled all requirements.
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II. External Documents
II.1 TramelBlaze
II.1.1 Detailed Block Diagram
These documents explain the architecture, instruction set, and logic of the TramelBlaze and its interfaces. It
helped to create the design of the project and the Programmable Read-Only Memory (PROM) within the design.
The TramelBlaze is a 16-Bit PicoBlaze emulator. The PicoBlaze is an embedded 8-bit RISC microcontroller. The
PicoBlaze had similar logic, architecture, and instruction set to the TramelBlaze. The PicoBlaze documentation provided the
basis for our TramelBlaze programming and usage.
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II.1.2 Data Transmission:
Memory:
The TramelBlaze is able to run using 4 different types of memory.
1. 512 x 16 Scratch RAM - This is where interpreted data is stored
2. 128 x 16 Stack RAM - Holds temporary data storage that behaves as a FILO buffer
3. 4096 x 16 TB ROM - Instructions are stored in the TramelBlaze ROM
4. 16 x 16 Register Array
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II.1.3 TramelBlaze Instructions:
An essential part of learning to program
The TramelBlaze is understanding the
Instructions that can be performed on
The scratch RAM memory, and the registers.
These diagrams demonstrate
how to send and grab data from the
TramelBlaze. It also shows each operation
and how to perform them on the registers.
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II.1.4 Software Design
Trambler Directives
 Assembler directives are “instructions” added to the assembly language program that are intended to communicate with the
assembler – they are not instructions to be converted into machine language instructions
 ADDRESS – default address is 000. This directive changes where the instructions are placed in the range 000…FFF
 EQU – Equate a label with a constant value to be substituted prior to final assembly
 END – End of the source
Source Code Organization
 TramelBlaze code should be organized into six main portions:
 Declarations – define all constants and string substitutions
 Initialization – all setup required before enabling interrupts and entering main loop
 Main Loop – routine where the processor spends most of its time. Cycling is achieved by JUMP at the end
of the loop
 Service Routines – all of the routines needed to implement the functionality of the software (typically
executed with interrupt enables.
 Interrupt Service Routine (ISR) – routine invoked when interrupt occurs. Best to minimize time spent in
ISE with interrupts disabled.
 Vector to ISE found at FFE/FFF
Top Level Design
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II.2 Nexys A7
II.2.1 Hardware
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II.2.2 Input/Output
This figure shows the switch, LED,
Button, and Seven Segment Display
connections of the Nexys A7. This shows
the pin names and how to
connect them to the top module
through the constraint file
II.2.3 Nexys A7 UART Configuration
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III. Requirements
III.1 Interface Requirements
This project uses three components: the TramelBlaze, the UART Engine, and the Memory Interface Block.
These components are instantiated within the top module. The MIB takes characters from the Receive Engine of the UART,
and places them in Micron Memory. Once a special character is received, a certain value is transmitted to the terminal. For
example, ‘*’ causes hometown transmission. To accomplish this, the TramelBlaze takes the ASCII values stored in Micron
Memory and outputs the values to the terminal using the Transmit Engine. Before any input can be received by the Transmit
Engine however, a banner displaying ‘WELCOME CECS !’ is transmitted to the terminal.
Since UART Protocol is being used, Baud Rate is an essential part of data communication. All components
involved need to operate at the same bit transmitting/receiving frequency. The switches of the Nexys A7 control the Baud
Rate and UART Parity values.
Baud Switches Baud Rate Bit Time Nexys A7 Count
0000 300 0.0033333333 3333333
0001 1200 0.000833333 83333
0010 2400 0.000041667 41667
0011 4800 0.000208333 20833
0100 9600 0.000104167 10417
0101 19200 5.20833E-05 5208
0110 38400 2.60417E-05 2604
0111 57600 1.73611E-05 1736
1000 115200 8.68056E-06 868
1001 230400 4.34028E-06 434
1010 460800 2.17014E-06 217
1011 921600 1.08507E-06 109
This logic table describes how switches[3:1] are in charge of the number of bits and the parity bit. Switch[3] decides
whether the data is 8 or 7 bits. Switch[2] is in charge of if there is a parity bit. Switch[1] manages either even
or odd parity.
Switches[3:1] Data Size (Bits) Parity
000 7 None
001 7 None
010 7 Even
011 7 Odd
100 8 None
101 8 None
110 8 Even
111 8 Odd
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III.2 Physical Requirements
This table demonstrates how the switches are the input values for BAUD[3:0], eight, pen, ohel.
Eight: This input signal connects to switch[3] and indicates whether or not the data being
transmitted is 8 bits wide. ‘1’ for yes, ‘0’ for no.
PEN: This input signal connects to switch[2] and indicates whether or not the data has parity
enabled. ‘1’ for yes, ‘0’ for no.
OHEL: This input signal connects to switch[1] and indicates what kind of parity the data has.
‘1’ means odd parity, ‘0’ means even.
BTNU BTND BTNC BTNL BTNR
Reset N/A N/A N/A N/A
Only one button is used in this design to connect to the AISO block. When this button is pressed,
a global reset is sent to the AISO block. The output of the AISO block is then sent to all flops in the
design.
LEDS[7] LEDS[6] LEDS[5] LEDS[4] LEDS[3] LEDS[2] LEDS[1] LEDS[0]
The LEDs are used to walk a ‘1’ through them from LSB to MSB. The walking LED effect
demonstrates that the system is running.
Switches[7] Switches[6] Switches[5] Switches[4] Switches[3] Switches[2] Switches[1] Switches[0]
Baud[3] Baud[2] Baud[1] Baud[0] Eight PEN OHEL N/A
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IV. Top Level Design
IV.1 Description
The top level module connects all the modules together. This is done by instantiating the AISO ,
TramelBlaze Top, UART, Seven Segment Display, RS Flop, and two Address Decoders. The inputs/outputs are
connected to the FPGA.
IV.2 Top Level Diagram
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IV.3 Detailed Level Diagram
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IV.4 Data Flow Description
This project required that the user was able to interact with the terminal using the UART processor.
This project is important because it fully incorporated the UART design. The program
will display the banner “WELCOME CECS !” and then it will wait for the user input from the terminal. If the
terminal notices an input, it will check which character has been input. If it detects “*”, a hometown will be
printed. If it detects “@”, the terminal will print the amount of characters stored from previous inputs. If a
<backspace> is detected, a backspace occurs. Lastly if <cr> is detected, a new prompt is printed. In addition,
a ‘1’ is walked through the LEDs to indicate that the program is running. This project was also the first
time a Memory Interface Block was used to manage the memory addresses and data that communicated
with the Micron Memory. The TramelBlaze will be able to grab data from the terminal and place
those characters into a location in the memory
IV.5 Input/Output
Signal Size I/O Connection
clk 1 Input 100MHz Oscillator
reset 1 Input AISO
switches 7 Input Nexys A7 Switches[7:0]
TX 1 Output Nexys A7 Transmit USB
RX 1 Input Nexys A7 Receive USB
memoryAddress 23 Output Micron Memory
currentStatus 8 Output Micron Memory
cCE 1 Output Micron Memory
cWE 1 Output Micron Memory
cOE 1 Output Micron Memory
cADV 1 Output Micron Memory
CRE 1 Output Micron Memory
cUB 1 Output Micron Memory
cLB 1 Output Micron Memory
MIBInOut 16 Output Micron Memory
anode 8 Output Nexys A7 Anode
cathode 8 Output Nexys A7 Cathode
LEDs 8 Output Nexys A7 LED[7:0]
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IV.6 Pin Assignments
Input Signals Assignment Output Signals Assignment
clk E3 leds[0] H17
reset M18 leds [1] K15
rx C4 leds [2] J13
eight R15 leds[3] N14
pen M13 leds[4] R18
Ohel L16 leds[5] V17
baud[0] R17 leds[6] U17
baud[1] T18 leds[7] U16
baud[2] U18 tx D4
baud[3] R13
IV.7 Electrical Requirements
 Buttons
 3.3V equates to logic ‘1’
 0V equates to logic ‘0’
 Switches
 1.8 V equates to logic ‘1’
 0V equates to logic ‘0’
IV.8 Clock
The Nexys A7 clock is regulated by a 100MHz crystal oscillator. All flops in this design use the clock and update their
register values at rising clock edges.
IV.9 Resets
The Reset of the project is connected to Pin M18 of the Nexys A7 board. It is a button and every time that button is pressed,
the reset signal is sent to the AISO block which sends a synchronized reset signal to all flops in the design.
Source Code: Appendix VIII.18
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IV.10 Software
1 ; Paul Valenzuela
2 ; 018469189
3 ; CECS 460
4 ; This code transmits
5 ; '<CR><LF>WELCOME CECS !' banner then
6 ; prompt on reset and detect four chars
7 ; that choose to DISPLAY hometown (*)
8 ; amount of characters in line (@)
9 ; backspace (BACKSP)
10 ; new prompt (<CR>)
11 ; Also 8 onboard walking LEDS indicate that
12 ; the code is working correctly
13
14
15 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
16 ; Define and initialize global variables
17 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
18 ZERO EQU 0000
19 ONE EQU 0001
20 TWO EQU 0002
21 THREE EQU 0003
22 FOUR EQU 0004
23 FIVE EQU 0005
24 LEDDELAY EQU BA03
25 TOP EQU 0028
26 BACKSP EQU 0008
27 CARRET EQU 000D
28 PROMPTCHECK EQU 0010
29 BNCHK EQU 0014
30 HTCHK EQU 0020
31 ASTSYM EQU 002A
32 ATSYM EQU 0040
33
34 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
35 ; Define Registers
36 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
37 TEMP EQU R0 ; Temp to hold temporary data
38 POINTER EQU R1 ; Pointer to RAM
39 TXCHECK EQU R2 ; TX Check
40 VALUE EQU R3 ; Check if UART Ready
41 LEDCOUNT2 EQU R4 ; Counter for LED Delay
42 LEDS EQU R5 ; LEDs
43 COUNTER EQU R6 ; Counter
44 LEDCOUNT EQU R7 ; Counter for LED Delay
45 STATUS EQU R8 ; Status of RX and TX
46 ERROR EQU R9 ; Check possible errors
47 DIVISOR EQU RA ; Divisor for ASCII Convert
48 QUOTIENT EQU RB ; Quotient for ASCII Convert
49 TXSTATE EQU RC ; Transmit State
50 WORKS EQU RD ; Checks if value is valid
51 COUNT EQU RE ; Temporarily holds counter
52
53
54 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
55 ; Initialize variables and RAM
56 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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57 INIT
58 ENINT
59 LOAD POINTER, ZERO ; Pointer = 0
60 LOAD VALUE, ZERO ; Value = 0
61 LOAD LEDS, ONE ; LEDS = 0001
62 LOAD LEDCOUNT2, ZERO ; LEDcount2 = 0
63 LOAD LEDCOUNT, ZERO ; LEDcount = 0
64 LOAD TXSTATE, ZERO ; TXState = 0
65 LOAD STATUS, ZERO ; Status = 0
66 LOAD COUNTER, ZERO ; Counter = 0
67 CALL BANNER ; Insert Banner into Scratch RAM
68 CALL PROMPT ; Insert Prompt into Scratch RAM
69 CALL HOMETOWN ; Insert Hometown into Scratch RAM
70 CALL BACKSPACE ; Insert <bs> into Scratch RAM
71 CALL HEXCONVERT ; Initialize Binary to ASCII Converter
72
73
74 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
75 ; Main Routine that cycles through LED
76 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
77 MAIN
78 OUTPUT LEDS, ONE ; Output LED values to board
79 COMP LEDS, 0080 ; LEDS == 0080 ?
80 CALLZ RESETLEDS ; If true call reset LEDS
81 RL LEDS ; Shift LEDS left 1 bit
82 CALL LEDCOUNTER ; Call subroutine to slow LEDs
83 JUMP MAIN ; Super Loop Main
84
85 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
86 ; Resets LED value to "0000 0001"
87 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
88 RESETLEDS
89 LOAD LEDS, ONE ; LEDS = 0001
90 RETURN
91
92
93 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
94 ; Counter that delays the walking '1' in LED value
95 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
96 LEDCOUNTER
97 ADD LEDCOUNT, ONE ; Increment counter1
98 NOP ; Wait
99 COMP LEDCOUNT, LEDDELAY ; Check once counter1 reaches 11
100 JUMPC LEDCOUNTER ; Loop until true
101 LOAD LEDCOUNT, ZERO ; Reset counter1
102 ADD LEDCOUNT2, ONE ; Increment counter2
103 COMP LEDCOUNT2, FOUR ; Check once counter2 reaches 4
104 JUMPNZ LEDCOUNTER ; Loop until true
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105 LOAD LEDCOUNT2, ZERO ; Reset counter2
106 RETURN
107
108 ; ISR ADDRESS
109 ADDRESS 0300
110
111 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
112 ; Interrupt Service Routine
113 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
114 ISR
115 STORE POINTER, 0031 ; RAM[65] = Pointer
116 INPUT STATUS, ONE ; Read the Status Value
117
118 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
119 ; Checks if txReady is active
120 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
121 LOAD TEMP, STATUS ; Temp = status
122 COMP TXSTATE, FOUR ; TXState == 4 ?
123 JUMPZ RXCHECK ; If true, check if RX is ready
124 AND TEMP, TWO ; Temp = Temp & 0002
125 COMP TEMP, TWO ; TXReady ?
126 JUMPNZ FALSEINTERRUPT ; If False, Exit
127
128 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
129 ; Store temp value into SCRATCH RAM[POINTER]
130 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
131 STORERAM
132 STORE TEMP, POINTER ; RAM[Pointer] = Temp
133 ADD POINTER, ONE ; Pointer += 1
134 RETURN
135
136
137 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
138 ; Place initial banner in RAM[0] (<CARRET><LF>WELCOME CECS !) (16 Characters)
139 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
140 BANNER
141 LOAD TEMP, 000D ; Temp = <CARRET>
142 CALL STORERAM
143 LOAD TEMP, 000A ; Temp = <lf>
144 CALL STORERAM
145 LOAD TEMP, 0057 ; Temp = 'W'
146 CALL STORERAM
147 LOAD TEMP, 0045 ; Temp = 'E'
148 CALL STORERAM
149 LOAD TEMP, 004C ; Temp = 'L'
150 CALL STORERAM
151 LOAD TEMP, 0043 ; Temp = 'C'
152 CALL STORERAM
153 LOAD TEMP, 004F ; Temp = 'O'
154 CALL STORERAM
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155 LOAD TEMP, 004D ; Temp = 'M'
156 CALL STORERAM
158 CALL STORERAM
159 LOAD TEMP, 0020 ; Temp = ' '
160 CALL STORERAM
162 CALL STORERAM
164 CALL STORERAM
166 CALL STORERAM
167 LOAD TEMP, 0053 ; Temp = 'S'
168 CALL STORERAM
169 LOAD TEMP, 0020 ; Temp = ' '
170 CALL STORERAM
171 LOAD TEMP, 0021 ; Temp = '!'
172 CALL STORERAM
173 RETURN
174
175 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
176 ; Place prompt in RAM[16] (<CARRET><LF>--> )
177 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
178 PROMPT
179 LOAD TEMP, 000D ; Temp = <CARRET>
180 CALL STORERAM
181 LOAD TEMP, 000A ; Temp = <lf>
182 CALL STORERAM
183 LOAD TEMP, 002D ; Temp = '-'
184 CALL STORERAM
185 LOAD TEMP, 002D ; Temp = '-'
186 CALL STORERAM
187 LOAD TEMP, 003E ; Temp = '>'
188 CALL STORERAM
189 LOAD TEMP, 0020 ; Temp = ' '
190 CALL STORERAM
191 RETURN
192
193 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
194 ; Place 'La Quinta' (hometown) in RAM[22] (11 Characters)
195 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
196 HOMETOWN
197 LOAD TEMP, 004C ; Temp = 'L'
198 CALL STORERAM
199 LOAD TEMP, 0041 ; Temp = 'A'
200 CALL STORERAM
201 LOAD TEMP, 0020 ; Temp = ' '
202 CALL STORERAM
203 LOAD TEMP, 0051 ; Temp = 'Q'
204 CALL STORERAM
205 LOAD TEMP, 0055 ; Temp = 'U'
206 CALL STORERAM
207 LOAD TEMP, 0049 ; Temp = 'I'
208 CALL STORERAM
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Final Specification
209 LOAD TEMP, 004E ; Temp = 'N'
210 CALL STORERAM
211 LOAD TEMP, 0054 ; Temp = 'T'
212 CALL STORERAM
213 LOAD TEMP, 0041 ; Temp = 'A'
214 CALL STORERAM
215 LOAD TEMP, 0020 ; Temp = ' '
216 CALL STORERAM
217 RETURN
218
219
220 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
221 ; Place Backspace command in RAM[33] (<BACKSP> ' ' <BACKSP>)
222 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
223 BACKSPACE
224 LOAD TEMP, 0008 ; Temp = <BACKSP>
225 CALL STORERAM
226 LOAD TEMP, 0020 ; Temp = ' '
227 CALL STORERAM
228 LOAD TEMP, 0008 ; Temp = <BACKSP>
229 CALL STORERAM
230 RETURN
231
232 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
233 ; Checks if rxReady is active
234 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
235 RXCHECK
236 LOAD TEMP, STATUS ; Temp = Status
237 AND TEMP, ONE ; Temp = Temp & 0001
238 COMP TEMP, ONE ; Temp == 0001 ? (RXReady?)
239 JUMPNZ FALSEINTERRUPT ; If false, go to false ISR
240
241 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
242 ; Locates and outputs error
243 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
244 LOAD ERROR, STATUS ; Error = status
245 AND ERROR, 001C ; Check error status
246 SR0 ERROR ; Shift error right
247 SR0 ERROR ; Shift error right
248 OUTPUT ERROR, TWO ; Output new error
249
250 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
251 ; Read data and set it to temp
252 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
253 INPUT VALUE, ZERO ; Value = IN_PORT[0]
254 LOAD TEMP, VALUE ; Temp = Value
255
256 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
257 ; Check if <CARRET> was entered in the prompt
258 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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259 ENTERCHECK
260 COMP TEMP, CARRET ; Temp == <CARRET> ?
261 JUMPNZ BSCHECK ; If true, jump to enter subroutine
262 LOAD TXSTATE, THREE ; TXState = 3
263 LOAD POINTER, 0010 ; Pointer = 16
264 FETCH VALUE, POINTER ; Value = RAM[16]
267 JUMP TRANSMIT ; Transmit values
268
269 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
270 ; Check if <BS> was entered in the prompt
271 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
272 BSCHECK
273 COMP TEMP, BACKSP ; Temp == <BACKSP> ?
274 JUMPNZ ASTERICKS ; If true, jump to backspace subroutine
275 COMP COUNTER, ZERO ; Counter == 0 ?
276 JUMPZ FALSEINTERRUPT ; If true jump to false ISR
277 LOAD TXSTATE, FIVE ; TXState = 5
278 SUB COUNTER, ONE ; Counter -= 1
279 LOAD TXCHECK, 0023 ; TXCheck = 35
284 JUMP TRANSMIT
285
286 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
287 ; Check if '*' was entered in the prompt
288 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
289 ASTERICKS
290 COMP TEMP, ASTSYM ; Temp == '*' ?
291 JUMPNZ ATYSYMBOL ; If true, jump to display hometown
292 LOAD TXSTATE, TWO ; TXState = 2
297 JUMP TRANSMIT
298
299 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
300 ; Check if '@' was entered in the prompt
301 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
302 ATYSYMBOL
303 COMP TEMP, ATSYM ; Temp == '@' ?
304 JUMPNZ INCREMENT ; If true, check if counter maxed out
305 CALL HEXCONVERT ; Update Counter
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312 JUMP TRANSMIT
313
314 INCREMENT
315 COMP COUNTER, TOP ; Counter == Top ?
316 JUMPZ FALSEINTERRUPT ; If true, jump to false ISR
317 ADD COUNTER, ONE ; Counter += 1
318
319 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
320 ; Transmit data to terminal
321 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
322 TRANSMIT
323 OUTPUT VALUE, ZERO ; Transmit value
324 FETCH POINTER, 0031 ; Pointer = RAM[21]
325 RETEN
326
327
328 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
329 ; Output value to terminal
330 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
331 DISPLAY
332 FETCH POINTER, 0030 ; Pointer = 64
334 OUTPUT VALUE, ZERO ; Transmit Value
337 COMP POINTER, TXCHECK ; Pointer == TXCheck ?
338 JUMPZ PROMPTCHECK ; If true, check TXState
339 JUMP FALSEINTERRUPT ; Jump to false ISR
340
341
342 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
343 ; Displays hometown string in ASCII
344 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
345 PRINTH
346 COMP TXSTATE, FIVE ; TXState == 5 ?
347 JUMPZ DISPLAY ; If true, transmit values
348 COMP TXSTATE, TWO ; TXState == 2 ?
349 JUMPNZ PRINTPROMPT ; If false check if TXState == 3
352 JUMP DISPLAY ; Transmit Values
353
354 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
355 ; Displays banner
356 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
357 PRINTBANNER
358 COMP TXSTATE, ZERO ; TXState == 0 ?
359 JUMPNZ FALSEINTERRUPT ; If false, exit
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364 JUMP DISPLAY
365
366 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
367 ; Displays prompt
368 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
369 PRINTPROMPT
370 COMP TXSTATE, THREE ; TXState == 3 ?
371 JUMPNZ PRINTBANNER ; If false, check if TXState == 4
374 JUMP DISPLAY ; Transmit Values
375
376 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
377 ; Checks if TXCheck is 36 or 22
378 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
379 PROMPTCHECK
380 COMP TXCHECK, 0023 ; txCheck == 36?
381 JUMPZ TXSTATE4 ; If so, jump to TXSTATE4
382
383 COMP TXCHECK, 0016 ; txCheck == 22?
384 JUMPNZ PROMPTCHANGE ; If not, display prompt
385 LOAD COUNTER, ZERO ; Counter
386
387 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
388 ; Ensures TXState is 4
389 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
390 TXSTATE4
391 LOAD TXSTATE, FOUR ; txState = 4
393 RETEN
394
395 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
396 ; Changes Pointer Location
397 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
398 PROMPTCHANGE
400 STORE POINTER, 0030 ; RAM[64] = RAM[Pointer]
402 LOAD TXSTATE, THREE ; txState = 3
403 RETEN
404
405 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
406 ; Faulty interrupt caused by an error
407 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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408 FALSEINTERRUPT
410 RETEN
411
412
413 ADDRESS 0400
414
415
416
417
418 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
419 ; Converts binary value of counter to ASCII to output to terminal
420 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
421 HEXCONVERT
422 LOAD WORKS, ZERO ; Works = 0
424 LOAD DIVISOR, 2710 ; Divisor = 10,000
425 LOAD QUOTIENT, ZERO ; Quotient = 0
426 LOAD COUNT, COUNTER ; Count = Counter
427
428 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
429 ; Check if using the correct divisor value
430 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
431 CHECK
432 COMP COUNTER, DIVISOR ; Counter < Divisor ?
433 JUMPC CHANGEDIVISOR ; If true, jumpt to changedivisor subroutine
434 ADD QUOTIENT, ONE ; Quotient += 1
435 SUB COUNTER, DIVISOR ; Counter -= Divisor
436 JUMP CHECK ; Jump to check subroutine
437
438
439
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Makes sure quotient value is WORKS, then jumps to subroutine that changes divisor
440 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
441 CHANGEDIVISOR
442 COMP WORKS, ONE ; Works == 1 ?
443 JUMPZ QUOTASCII ; If true, jump to quotient to ascii conversion
444 COMP QUOTIENT, ZERO
445 JUMPZ SETSPACE ; If true, jump to add a hexi space subroutine
446 LOAD WORKS, ONE ; Works = 1
447
448
449
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Convert quotient value to ASCII
450
451
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
QUOTASCII
452 ADD QUOTIENT, 0030 ; Change quotient to ascii
453 JUMP DIVIDE
454
455 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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456 ; Adds a space between banner and <count> value
457 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
458 SETSPACE
459 ADD QUOTIENT, 0020 ; Make quotient a ' '
460
461 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
462 ; Algorithm that divides binary value by 10,000, 1,000, 100, then 10 to convert it to
463 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
464 DIVIDE
465 STORE QUOTIENT, POINTER ; RAM[POINTER] = Quotient
466 LOAD QUOTIENT, ZERO ; Quotient = 0
468 COMP DIVISOR, 000A ; Divisor == 10 ?
469 JUMPZ LASTVALUE ; If true, jump to lastvalue subroutine
470 COMP DIVISOR, 0064 ; Divisor == 100 ?
471 JUMPZ TEN ; If true, jump to ten subroutine
472 COMP DIVISOR, 03E8 ; Divisor == 1,000 ?
473 JUMPZ HUNDRED ; If true, jump to hundred subroutine
474 JUMP THOUSAND ; Else, jump to thousand subroutine
475
476 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
477 ; Stores the 1's place of the counter into SCRATCH RAM
478 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
479 LASTVALUE
480 ADD QUOTIENT, COUNTER ; Quotient += counter
481 ADD QUOTIENT, 0030 ; Convert quotient to ASCII
482 STORE QUOTIENT, POINTER ; RAM[POINTER] = quotient
484 LOAD COUNTER, COUNT ; Counter = count
485 RETURN
486
487 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
488 ; Subrountine to change divisor to 1000
489 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
490 THOUSAND
491 LOAD DIVISOR, 03E8 ; Divisor = 1,000
492 JUMP CHECK
493
494 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
496 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
497 HUNDRED
498 LOAD DIVISOR, 0064 ; Divisor = 100
499 JUMP CHECK
500
501 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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503 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
504 TEN
505 LOAD DIVISOR, 000A ; Divisor = 10
506 JUMP CHECK 507
508 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
509 ; Vector to Interrupt Service Routine - NO CHANGES HERE
510 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
511 ADDRESS 0FFE ; Interrupt At Vector Address 0FFE
512 ENDIT
513 JUMP ISR ; Jump to ISR
514 END
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V. External Developed Blocks
V.1 Asynchronous In, Synchronous Out (AISO)
V.1.1 Description V.1.2 Top Level Diagram
This block prevents metastability by creating
a synchronized reset signal. The reset input
of this block is connected to a button on the
Nexys A7 board. The output resets every signal.
V.1.3 Input/Output
Signal I/O Connected to
clk Input 100MHz Crystal Oscillator
reset Input Button
sRst Output mRst
V.1.4 Register Map
Register Usage Description
{d2,q2} Synchronize Once resets, sends a single pulse to all modules
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V.2 TramelBlaze
V.2.1 Description V.2.2 Top Level Diagram
The TramelBlaze is 16-bit soft-core
microcontroller that emulates the PicoBlaze.
The TramelBlaze reads and performs actions
based on instructions provided by the ROM.
The TramelBlaze is used in this project to
receive and transmit ASCII values to a Serial
terminal. The WRITE_STROBE and
READ_STROBE communicate with the
UART which helps to establish whether
the design will be using the transmit
or receive engine.
V.2.3 Input/Output
Signal I/O Connection
CLK Input 100MHz Crystal Oscillator
RESET Input AISO
INTERRUPT Input RS Flop
IN_PORT[15:0] Input UART
PORT_ID[15:0] Output UART + AddressDecoder
OUT_PORT[15:0] Output UART
READ_STROBE Output UART
WRITE_STROBE Output UART
INTERRUPT_ACK Output RS Flop
V.2.4 Register Map
TB_ROM[15:0] Read Only Memory Holds Instructions for TramelBlaze to execute
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VI. Internally Developed Blocks
VI.1 Memory Block Interface
VI.1.1 Description
The Memory Interface Block consists of a state machine and control flops. The state machine
inputs are the PORT_ID values. There are three possible states: MEMWRITE, MEMREAD, IDLE. The
outputs of each state are CE, WE, OE, and T. The flops of the MIB then use these signals to control the
memory addresses and the data being communicated between them and the Micron Memory. Prior to this,
the TramelBlaze Read Only Memory had been in charge of this data flow.
VI.1.2 Top Level Diagram
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VI.1.3 Input/Output
Signal Size (Bits) Input/Output Connection
clk 1 Input 100MHz Crystal Oscillator
rst 1 Input AISO
READ 1 Input TramelBlaze
WRITE 1 Input TramelBlaze
PORT_ID 16 Input TramelBlaze
memoryDataIn 16 Input Micron Memory
OUT_PORT 16 Input TramelBlaze
cCE 1 Output Micron Memory
cWE 1 Output Micron Memory
cOE 1 Output Micron Memory
cADV 1 Output Micron Memory
cCRE 1 Output Micron Memory
cUB 1 Output Micron Memory
cLB 1 Output Micron Memory
memoryAddress 23 Output Micron Memory
memoryDataOut 16 Output Micron Memory
IN_PORT 16 Output TramelBlaze
VI.1.4 Register Map
Register Module Description
cCE MIB Chip Enable Signal to Micron Memory
cWE MIB Write Enable Signal to Micron Memory
cOE MIB Output Enable Signal to Micron Memory
cIOBUF_T MIB Controller for IOBUF
cADV MIB Address Valid Signal for Micron Memory
CRE MIB Control Register Enable Signal for Micron Memory
cUB MIB Upper Byte Signal for Micron Memory
cLB MIB Lower Byte Signal for Micron Memory
memoryAddress MIB Memory Address Location
memoryDataOut MIB Data to Micron Memory
IN_PORT MIB Data from TramelBlaze
state MIB State of MIB
nState MIB Next State of MIB
WCLK MIB Counter to Stay in Write State for 130ns
RCLK MIB Counter to Stay in Read State for 130ns
nCE MIB Chip Enable Next State
nWE MIB Write Enable Next State
nOE MIB Output Enable Next State
nIOBUF_T MIB T Next State
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VI.1.5 State Machine
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VI.2 Universal Asynchronous Receiver and Transmitter (UART)
VI.2.1 Description
The UART module is built by five components: the Transmit Engine, the Receive Engine, the
Baud Rate Decoder, and two Positive Edge Detectors. The Transmit Engine shifts serial data out to the
Transmit Line through the micro-USB connection. The Receive Engine shifts serial data into a register. It
then takes the data in the register and sends it to the TramelBlaze to be processed. A UART module
communicates data between modules without a clock to synchronize data transmission. In order to make
sure the data is valid, a common frequency is required. This is accomplished by both engines sharing the
Baud Rate. The Baud Rate is determined by decoding the switch values from the Nexys A7 board. Baud
Rate represents the speed that data is transmitted and received.
The UART block communicated to the TramelBlaze when the receive engine/transmit engine us
ready to interpret data. This signal is communicated by an interrupt signal. The Interrupt reaches the
TramelBlaze and causes it to enter the Interrupt Service Routine. This signal sent from the UART is
called UARTready.
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VI.2.3 Detailed Level Diagram
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VI.2.4 Input/Output
Signal Size(Bits) I/O Connection
rst 1 Input AISO
rx 1 Input Nexys A7 USB
switches 8 Input Nexys A7 Switches
WRITE 8 Input Address Decoder
READ 8 Input Address Decoder
UARTready 1 Output TramelBlaze
tx 1 Output Nexys A7 USB
UART_DS 8 Output TramelBlaze
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VI.3 Transmit Engine
VI.3.1 Description
The Transmit Engine consists of five components: Bit Counter, Bit Time Counter, Shift Register,
Bit 10/9 Decoder, and the Transmit Controller. These components combine to help transmit data to the
computer terminal. The Bit Time Counter will decide the speed at which the transmit engine will shift
data out. The speed is set by the output of the Baud Rate Decoder. The Bit Counter makes sure the
register only shifts out 11 bits of data. The Shift Register helps to shift data outwards from the least
significant bit (LSB) to most significant bit (MSB). The Transmit Controller is in charge of setting the
values of the wires between the components. These wires tell the counters when to reset, and are in charge
of other circumstances such as parity enable, and the UART Interrupt. Lastly, the Bit 10/9 Decoder
decides what values to insert into bit 9 and bit 10 of the shift register. These values depend on how many
bits wide the signal to transmit is. All of these components are essential to build the Transmit Engine.
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VI.3.4 Verification
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VI.3.5 Input / Output
Signal Size (Bits) I/O Connection
rst 1 Input AISO
load 1 Input Address Decoder
eight 1 Input Nexys A7 Switch[3]
pen 1 Input Nexys A7 Switch[2]
ohel 1 Input Nexys A7 Switch[1]
k 19 Input Baud Rate Decoder
txReady 1 Output Nexys A7 USB
VI.3.6 Register Map
bit10 Decoder Bit 10 into the Shift Register
bit9 Decoder Bit 9 into the Shift Register
doit Transmit Controller Allows counter to increment
load1 Transmit Controller Delays data transmission by 1 clock period
nTX [10:0] Shift Register Holds data to be shifted out into board
lData [7:0] Shift Register Grabs data from TramelBlaze
bitTimeCount [18:0] Bit Time Counter Baud Rate Counter
bitCount [3:0] Bit Counter How many bits to shift Counter
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VI.4 Transmit Shift Register
VI.4.1 Description
The shift register is sent data from OUT_PORT on the TramelBlaze and shifts data outwards 1 bit
at a time in the output value tx. The tx usually has a value of ‘1’. The ‘start bit’ for the transmit engine is a
‘0’. So when a ‘0’ is initially sent, the tx will start outputting the register data 1 bit at a time. When the
module is reset, the shift register will continue to output 11 bits of ‘1’, to show its inactive state. The data
is sent out from LSB to MSB. With the first bit always being a ‘0’. The bit after the MSB will either be
the parity bit or the stop bit. But data transmission always ends with a ‘1’ stop bit. When the bit time
counter is done counting, a ‘1’ is sent to the TX engine and the UART interprets this as the end of the
data transmission.
VI.4.3 Input/Output
Rst 1 Input AISO
load 1 Input TX Controller
btu 1 Input TX Bit Time Counter
nTX 11 Input Bit10/9 Decoder, TX Controller
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VI.5 Bit 10 Bit 9 Decoder
VI.5.1 Description
This module oversaw deciding what values bit10 and bit9 receive. This is because these
bits depend entirely on the number of bits being transmitted and the parity of the transmission.
The data will either be 7 or 8 bits. This directly effects what bit9 will be. Also, if there is a parity,
the parity bit will be placed in bit9 or bit10, depending on how many bits the data is. All of these
conditions are evaluated and assigned based on the decoder. The inputs of the decoder are eight,
pen, and ohel.
VI.5.3 Input/Output
lData 8 Input TX Controller
bit10 1 Output TX Shift Register
bit9 1 Output TX Shift Register
VI.5.4 Logic Table
eight pen ohel bit10 bit9
0 0 0 1 1
0 0 1 1 1
0 1 0 1 ^lData[6:0]
0 1 1 1 ~^lData[6:0]
0 0 0 1 lData[7]
1 0 1 1 lData[7]
1 1 0 ^lData[7:0] lData[7]
1 1 1 ~^lData[7:0] lData[7]
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VI.6 Transmit Controller
VI.6.1 Description VI.6.2 Top Level Diagram
The transmit controller is in
charge of the wires between the flops
and indicative signals. This includes
doit, done, btu, etc. It communicates
between the flops and tells them how
to behave. It is also in charge of telling
the shift register when to load new
data with the load1 signal.
VI.5.3 Input/Output
clk 1 Input 100MHz Clock Oscillator
rst 1 Input AISO
done 1 Input TX Bit Count
load 1 Input Address Decoder
txReady 1 Output PED
load1 1 Output TX Shift Register
doit 1 Output Both TX Counters
lData 8 Output TX Shift Register
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VI.7 Transmit Bit Counter
This counter counts from 0-11 in decimal.
Each increment is to indicate how many
bits have been transmitted. It increments
every time the “doit” and “btu” signals
are high. This means that the bit time counter
has reached its value. This is important
because a bit is only sent every time the
bit time counter has reached its comparable value.
VI.7.3 Input/Output
rst 1 Input AISO
doit 1 Input TX Controller
btu 1 Input TX Bit Time Counter
done 1 Output TX Controller
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VI.8 Transmit Bit Time Counter
The bit time counter is used to
transmit bits at a very specific baud
rate. The bit time counter increments
at every clock signal and will continue
to increment until it reaches its indicated
baud rate. The bit time counter resets when
the “done” signal is high. This means that
the baud rate has been reached and a bit
is ready to transmit.
VI.8.3 Input/Output
clk 1 Input 100 MHz Clock Oscillator
rst 1 Input AISO
doit 1 Input TX Controller
btu 1 Output TX Shift Register
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VI.9 Receive Engine
VI.9.1 Description
The Receive engine works in the opposite direction of the transmit engine. It inputs data 1 bit at a
time and shifts them into a shift register. It then interprets this data and sends it to the TramelBlaze via
IN_PORT. The receive engine consists of 5 components: a Bit Time Counter, a Bit Counter, a State
Machine, Receive Controller, and the Receive Shift Register. All these components combine to allow the
UART to receive data 1 bit at a time and interpret it into a valid ASCII value. It is important that the
shifted data is shifted at the correct baud rate for the appropriate amount of times. The shift register grabs
data from the rx input and shifts it into a register. However, the number of bits of data and parity bit need
to be taken into consideration. Due to this, the data needs to be remapped accordingly.
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VI.9.4 Verification
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VI.9.5 Input/Output
clk 1 Input 100 MHz Crystal Oscillator
rst 1 Input AISO
READ 8 Input Address Decoder
rxStatus 8 Output TramelBlaze
rxReady 1 Output UART PED
UART_RDATA 8 Output TramelBlaze
VI.9.6 Register Map
start State Machine Detection of start bit
nStart State Machine Holds next start value
done State Machine Resets counter values
doit State Machine Allows counter to count
nDoit State Machine Holds the next doit value
Parity_error Receive Controller Indicates a parity error
Framing_error Receive Controller Indicates a framing error
Overflow_error Receive Controller Indicates an overflow error
State State Machine State that holds done + start values
nState State Machine Registers the next State
nRX Shift Register Register holding raw data from Nexys Board
shiftedReg Right Justify Register Register with proper parity bit
BitTimeCount Bit Time Counter Baud Rate Counter
BitCount Bit Counter How many times register shift counter
newK Baud Rate Divider Baud Rate Decoder
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VI.10 Receive Shift Register
The shift register is a shift register that operates
under specific conditions. The 2 MSBs will either
be 0s or the data interpreted from the rx line,
depending on the values of eight and pen.
This module uses a switch case statement to assess
the values of eight and pen. If both values are high,
the data is not shifted. If only one of the values is high,
the data is shifted once to the right. If both are inactive,
the data is shifted twice to the right.
VI.10.3 Input/Output
rst 1 Input AISO
shiftHigh 1 Input RX Controller
shiftedReg 10 Output RX Controller
UART_RDATA 8 Output TramelBlaze
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VI.11 Receive State Machine
The state machine is implemented using
a Modified Moore technique. The state machine
guarantees that the start bit remains low-active
until it is mid-bit time. At this point, data collection
will continue at normal bit time until all the
data is received. This state machine outputs start
and doit. Start means that the engine has just
received the start bit. Doit means that the engine
is receiving actual data. The state machine
conditions are rx, done, and btu.
VI.11.3 State Transition Diagram
clk 1 Input 100 MHz Crystal Oscillator
rst 1 Input AISO
btu 1 Input RX Bit Time Counter
done 1 Input RX Bit Counter
start 1 Output RX Bit Time Counter
doit 1 Output Both RX Counters
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VI.12 Receive Controller
The receive controller is in charge of
the wires between the flops and indicative signals.
This includes doit, done, btu, etc. It communicates
between the flops and tells them how to behave.
It in charge of when to divide the baud value
by 2, and communicating the status of the
receive engine. An example being when
there is an overflow/parity/framing error.
rst 1 Input AISO
done 1 Input RX Bit Counter
shiftedReg 10 Input Receive Shift Register
rxReady 1 Output TramelBlaze
parity_error 1 Output UART
framing_error 1 Output UART
overflow_error 1 Output UART
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VI.13 Receive Bit Counter
This counter counts from 0-11 in decimal.
Each increment is to indicate how many bits
have been received. It increments every time
the “doit” and “btu” signals are high. This means
that the bit time counter has reached its value.
This is important because a bit is only grabbed every
time the bit time counter has reached its comparable
value. In addition, the Receive Bit Counter has to
constantly change the comparable value depending
on how many bits are received. This
depends on the values of pen and eight.
rst 1 Input AISO
doit 1 Input State Machine
btu 1 Input RX Bit Time Counter
done 1 Output State Machine
VI.13.4 Logic Table
eight pen == ?
0 0 9
0 1 10
1 0 11
1 1 11
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VI.14 Receive Bit Time Counter
The bit time counter is used to receive bits
at a very specific baud rate. The bit
time counter increments at every clock
signal and will continue to increment until
it reaches its indicated baud rate. The bit time
counter resets when the “done” signal is high.
This means that the baud rate has been
reached and a bit is ready to be received. The
only difference is that this bit time counter
counts to a value of k/2, where k is the
interpreted baud rate.
clk 1 Input 100 MHz Clock Oscillator
rst 1 Input AISO
doit 1 Input State Machine
start 1 Input State Machine
btu 1 Output RX Controller
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VI.15 Baud Rate Decoder
The Baud Rate Decoder is a 4 to 19-bit
Decoder that chooses the speed that the UART
communicates data. The 4 inputs of the decoder come
from switches[7:4] on the Nexys A7 board.
switches 4 Input Nexys A7 Switches[7:4]
k 19 Output Transmit + Receive Engine
VI.15.4 Register Map
k[18:0] Constant The rate that data is sent/received
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VI.16 Positive Edge Detect
This block detects a rising edge on
A given signal. It is used in the UART block to
detect when txReady and rxReady reach a
rising edge.
rst 1 Input AISO
in 1 Input Transmit + Receive Engine
yes 1 Output UART
q[1:0] PED Sends PED values when flop goes from {1,0} to {0,1}
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VI.17 RS Flop
The RS Flop behaves as a typical
RS flop. It holds a value until each rising
clock signal. If input s is high, the flop
outputs 1. The flop will then hold this value
until the flop reset or functional reset are high.
rst 1 Input AISO
funcrst 1 Input TramelBlaze
set 1 Input Transmit PED + Receive PED
q 1 Output TramelBlaze
q Interrupt Output interrupt when set high
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VI.18 Address Decode (READ)
This module determines the values
of READ[7:0] based on READ_STROBE
and PORT_ID[15:0]. It helps the UART
understand which values to send to the
TramelBlaze.
READ_STROBE 1 Input TramelBlaze
PORT_ID[15] 1 Input TramelBlaze
READS 8 Output Receive Engine
VI.9.1 Register Map
enable {READ_STROBE &
PORT_ID[15]}
Determines whether to write to TramelBlaze
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VI.19 Address Decode (WRITE)
This module determines the values
of WRITE[7:0] based on WRITE_STROBE
and PORT_ID[15:0]. It helps the UART
understand which values to grab from the
TramelBlaze.
WRITE_STROBE 1 Input TramelBlaze
WRITE 8 Output Transmit Engine
VI.9.4 Register Map
enable {WRITE_STROBE &
PORT_ID[15]}
Determines whether to read from TramelBlaze
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VII. Chip Level Verification
VII.1 Transmit Engine
As demonstrated by the screenshot above, the transmit engine works appropriately by transmitting a
banner to the terminal and incrementing the counter every time the banner is printed
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VII.2 UART Engine
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Input
The following keyboard inputs were entered into the terminal:
1. *
2. 12345<cr>
3. 12345@
4. 01234567@
5. <cr>
6. Paull
7. <bs>
8. <cr>
9. The Backspace Works…
Requirements
This demonstrates that the UART engine works as expected. It is able to receive data from the terminal,
interpret that data, and transmit new data to the terminal. In this specific design,
 “*” - Prints hometown
 <cr> - Creates newline
 “@” - Counts the amount of characters entered
 <bs> - Deletes the previous character
Verified
As shown above, all of the inputs gave the expected outputs. This means that the UART design satisfied
its requirements.
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VIII.Appendix
VIII.1 AISO
1 `timescale 1ns / 1ps
2 //******************************************************************************//
3 // File name: AISO.v //
4 // //
5 // Created by Paul Valenzuela on 9/16/19. //
6 // Copyright (C) 2018 Paul Valenzuela. All rights reserved. //
7 // //
8 // //
9 // In submitting this file for class work at CSULB //
10 // I am confirming that this is my work and the work //
11 // of no one else. In submitting this code I acknowledge that //
12 // plagiarism in student project work is subject to dismissal //
13 // from the class //
14 //******************************************************************************//
15 //******************************************************************************//
16 // AISO.v //
17 // //
18 // The AISO block ensures that all the blocks within the design share a //
19 // synchronous reset input. The AISO block works by converting the input //
20 // of reset into two flops. This makes sure that reset is stable and //
21 // helps prevent metastability //
22 // //
23 // @input clk, rst, //
24 // @output sRst //
25 // //
26 //******************************************************************************//
27 module AISO(clk, rst, sRst);
28 //Declare Variables
29 input wire clk,rst;
30 output wire sRst;
31 reg d2, q2;
32
33 //Sequential Block
34 always@(posedge clk,posedge rst)
35 //If Rst is on, both flops input 0
36 if(rst)
37 d2 <= 1'b0;
38 //Otherwise, the first flop gets 1 and the second gets the output of the first
flop
39 else
40 {d2,q2} <= {1'b1,d2};
41
42 //Output wire is assigned to the inverted output of the second flop
43 assign sRst = ~q2;
44
45 endmodule
46
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VIII.2 TramelBlaze Top
1 //****************************************************************//
2 // This document contains information proprietary to the //
3 // CSULB student that created the file - any reuse without //
4 // adequate approval and documentation is prohibited //
5 // //
6 // Class: CECS 460 //
7 // Project name: TRAMBLAZE PROCESSOR //
8 // File name: tramelblaze_top3.0_sim.v //
9 // Release: 3.0 Release Date 02mar2017 //
10 // Release: 5.0 Release Date 07nov2017 //
11 // to be used for simulation only //
12 // assumes following hierarchy //
13 // project //
14 // assembler//
15 // design (file in design looks in assembler for instr) //
16 // //
17 // Created by John Tramel on 20Feburary2016 //
18 // Copyright 2016 John Tramel. All rights reserved. //
19 // //
20 // Abstract: Top level for TRAMBLAZE processor //
21 // Edit history: 2016JAN25 - created //
22 // 20FEB - top created for processor and memory //
23 // tramelblaze_top //
24 // - tramelblaze //
25 // - tramelblaze_mem //
26 // 14feb2020 - modified path for sim.sim for Vivado //
27 // assumes Assembler directory same level as project //
28 // Top Level Directory //
29 // Assembler //
30 // code.tba, code.lst, sim.sim //
31 // Project //
32 // vivado project file //
33 // 18apr202 - startup error with memory - 1st instruction //
34 // not executed properly. Believe I fixed it //
35 // //
38 // of no one else. //
39 // //
40 // In the event other code sources are utilized I will //
41 // document which portion of code and who is the author //
42 // //
43 // In submitting this code I acknowledge that plagiarism //
44 // in student project work is subject to dismissal from the class //
45 //****************************************************************//
46
47 `timescale 1ns/1ns
48
49 module tramelblaze_top (CLK, RESET, IN_PORT, INTERRUPT,
50 OUT_PORT, PORT_ID, READ_STROBE, WRITE_STROBE, INTERRUPT_ACK);
51
52 input CLK;
53 input RESET;
54 input [15:0] IN_PORT;
55 input INTERRUPT;
56
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57 output [15:0] OUT_PORT;
58 output [15:0] PORT_ID;
59 output READ_STROBE;
60 output WRITE_STROBE;
61 output INTERRUPT_ACK;
62
63 wire [15:0] INSTRUCTION;
64 wire [11:0] ADDRESS;
65
66 tramelblaze tramelblaze
67 (
68 .CLK(CLK),
69 .RESET(RESET),
70 .IN_PORT(IN_PORT),
71 .INTERRUPT(INTERRUPT),
72
73 .OUT_PORT(OUT_PORT),
74 .PORT_ID(PORT_ID),
75 .READ_STROBE(READ_STROBE),
76 .WRITE_STROBE(WRITE_STROBE),
77 .INTERRUPT_ACK(INTERRUPT_ACK),
78
79 .ADDRESS(ADDRESS),
80 .INSTRUCTION(INSTRUCTION)
81 );
82
83
84 reg [15:0] memory [0:4095];
85 reg [15:0] ADDRESSQ;
86 /*
87 initial
88 $readmemh("/assembler/sim.sim",memory);
89
90 always@(*) INSTRUCTION = memory[ADDRESSQ];
91
92 always @(posedge CLK,posedge RESET)
93 if (RESET) ADDRESSQ <= 12'b0;
94 else ADDRESSQ <= ADDRESS; 95 */
96
97
98 tb_rom tb_rom
99 (
100 .clk (CLK), // input clka
101 .a (ADDRESS), // input [11 : 0] addra
102 .spo (INSTRUCTION) // output [15 : 0] douta
103 );
104
105 endmodule
106
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VIII.3 UART
2 //******************************************************************************//
3 // File name: UART.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // UART.v //
17 // //
18 // This module serves as the Universal Asynchronous //
19 // Receiver Transmitter block. It does this by holding an instantiation //
20 // of the transmit block and UART decoder. //
21 // //
22 // @input clk, rst, [7:0] READS, [7:0] WRITE, OUT_PORT[7:0], switches, rx //
23 // @output txReady, tx,
UART_DS //
24 // //
25 //******************************************************************************//
26 module UART(clk,rst,WRITE,READS,OUT_PORT,UARTready,tx,rx,switches,UART_DS);
27
28 input clk, rst, rx;
29 input [7:0] OUT_PORT, WRITE, READS;
30 output wire UARTready, tx;
31 output reg [7:0]UART_DS;
32 wire [7:0] UART_RDATA;
33 input [7:0] switches;
34
35 wire [18:0] k;
36 wire txReady, rxReady, txReadyYes, rxReadyYes;
37 wire [7:0] UART_STATUS;
38 wire [7:0] rxStatus;
39 reg [7:0] BAUD_VAL;
40
41
42 // Transmit
43 transmit transmit_engine(.clk(clk), .rst(rst),
44 .load(WRITE[0]), .k(k[18:0]),
45 .eight(switches[3]), .pen(switches[2]),
46 .ohel(switches[1]), .OUT_PORT(OUT_PORT[7:0]),
47 .txReady(txReady), .tx(tx));
48
49
50 // Recieve
51 recieve recieve_engine(.clk(clk), .rst(rst),
52 .eight(switches[3]),.pen(switches[2]),.ohel(switches[1]),
53 .READ(READS[7:0]),.k(k[18:0]),
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54 .rxReady(rxReady),.rx(rx),
55 .UART_RDATA(UART_RDATA[7:0]),
56 .rxStatus(rxStatus[7:0]));
57
58 // Assign K Value based on decoder
59 uart_decode decoder(.switches(switches[7:4]),.k(k[18:0]));
60
61 // PED txReady
62 posEdgeDetect txr(.clk(clk), .rst(rst), .in(txReady), .yes(txReadyYes));
63
64 // PED rxReady
65 posEdgeDetect rxr(.clk(clk), .rst(rst), .in(rxReady), .yes(rxReadyYes));
66
67 // UART Ready
68 assign UARTready = (txReadyYes || rxReadyYes);
69
70 // UART Status
71 assign UARTStatus = {rxStatus[7:2], txReady, rxStatus[0]};
72
73 // Decide which values to write to Tramelblaze
74 always@(*)
75 if(READS[0])
76 UART_DS = UART_RDATA;
77 else if(READS[1])
78 UART_DS = UART_STATUS;
79 else
80 UART_DS = 8'b0;
81
82 endmodule
83
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VIII.4 UART Decode
2 //******************************************************************************//
3 // File name: uart_decode.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // uart_decode.v //
17 // //
18 // The uart_decode module decodes values from switches to determine //
19 // baud rate //
20 // //
21 // @input [3:0] switches //
22 // @output [18:0] k //
23 // //
24 //******************************************************************************//
25 module uart_decode(switches,k);
26
27 input [ 3:0] switches; // Switches [7:4]:
28 output reg [18:0] k; // output as seen in transmit engine diagram
29
30 always @(*) begin
31 case (switches)
32 4'b0000: k = 19'd333333; //300 -- RATE
33 4'b0001: k = 19'd83333; //1200
34 4'b0010: k = 19'd41667; //2400
35 4'b0011: k = 19'd20833; //4800
36 4'b0100: k = 19'd10417; //9600
37 4'b0101: k = 19'd5208; //19200
38 4'b0110: k = 19'd2604; //38400
39 4'b0111: k = 19'd1736; //57600
40 4'b1000: k = 19'd868; //115200
41 4'b1001: k = 19'd434; //230400
42 4'b1010: k = 19'd217; //460800
43 4'b1011: k = 19'd109; //921600
44 default: k = 19'd333333; //300
45 endcase
46 end
47 endmodule
48
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VIII.5 Transmit Engine
2 //******************************************************************************//
3 // File name: transmit.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // transmit.v //
17 // //
18 // The transmit module serves as the top level for the trasnmit block. //
19 // It consists of several components and will later be used in the UART //
20 // block //
21 // //
22 // @input clk, rst, load, eight, pen, ohel, [7:0] OUT_PORT, [19:0] k //
23 // @output txReady, tx //
24 // //
25 //******************************************************************************//
26 module transmit(clk, rst, load, k, eight, pen, ohel, OUT_PORT, txReady, tx);
27 input clk, rst, load, eight, pen, ohel;
28 input [7:0] OUT_PORT;
29 input [18:0] k;
30
31 output reg txReady;
32 output wire tx;
33
34 wire btu, done;
35 reg bit10, bit9, doit, load1;
36 reg [10:0] nTX;
37 reg [7:0] lData;
38 reg [18:0] bitTimeCount;
39 reg [3:0] bitCount;
40
41
42 // Bit Counter
43 always@(posedge clk, posedge rst)
44 if (rst)
45 bitCount <= 4'b0;
46 else if(done)
48 else if({doit,btu} == 2'b11)
49 bitCount <= bitCount + 4'b1;
50 else
51 bitCount <= bitCount;
52
53 assign done = (bitCount == 4'b1011);
54
55
56 // DOIT Signal
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58 if (rst)
59 doit <= 1'b0;
60 else if(done)
61 doit <= 1'b0;
62 else if(load1)
63 doit <= 1'b1;
64 else
65 doit <= doit;
66
67 // Bit Time Counter
69 if (rst)
70 bitTimeCount <= 19'b0;
71 else if(btu)
73 else if(doit)
74 bitTimeCount <= bitTimeCount + 19'b1;
75 else
76 bitTimeCount <= bitTimeCount;
77
78 assign btu = (bitTimeCount == k) ? 1'b1 : 1'b0;
79
80
81 // LOAD1 Signal
83 if (rst)
84 load1 <= 1'b0;
85 else
86 load1 <= load;
87
88 // Loadable 8-Bit Register
90 if (rst)
91 lData <= 8'b0;
92 else if(load)
93 lData <= OUT_PORT[7:0];
94 else
95 lData <= lData;
96
97 // Decoder
98 always@(*)
99 case({eight,pen,ohel})
100 3'b000: {bit10,bit9} = 2'b11;
101 3'b001: {bit10,bit9} = 2'b11;
102 3'b010: {bit10,bit9} = {1'b1,(^lData[6:0])};
103 3'b011: {bit10,bit9} = {1'b1,(~(^lData[6:0]))};
104 3'b100: {bit10,bit9} = {1'b1,lData[7]};
105 3'b101: {bit10,bit9} = {1'b1,lData[7]};
106 3'b110: {bit10,bit9} = {(^lData[7:0]),lData[7]};
107 3'b111: {bit10,bit9} = {(~(^lData[7:0])),lData[7]};
108 default: {bit10,bit9} = 2'b0;
109 endcase
110
111
112 // Shift Register
113 always @(posedge clk, posedge rst)
114 begin
115 if(rst)
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116 nTX <= 11'b11111111111;
117 else if(btu)
118 nTX <= {1'b1, nTX[10:1]};
119 else if(load1)
120 nTX <= {bit10,bit9,lData[6:0],2'b01};
121 else
122 nTX <= nTX;
123 end
124
125 // Transmit tx signal
126 assign tx = (nTX[0]);
127
128 // TXREADY Signal
130 if (rst)
131 txReady <= 1'b1;
132 else if (load)
134 else if (done)
136 else
137 txReady <= txReady;
138
139 endmodule
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VIII.6 Receive Engine
2 //******************************************************************************//
3 // File name: recieve.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // recieve.v //
17 // //
18 // The recieve module serves as the trasnmit block for UART communiaction. //
19 // It consists of several components and will later be used in the UART //
20 // block //
21 // //
22 // @input clk, rst, READ, [19:0] k, [7:0] switches, rx //
23 // @output rxReady, [7:0]rxStatus, [7:0] UART_RDATA //
24 // //
25 //******************************************************************************//
26 module recieve(clk, rst, READ, k, rx, eight, pen, ohel, rxStatus, rxReady, UART_RDATA);
27 input clk, rst, rx, eight, pen, ohel;
28 input [18:0] k;
29 input [7:0] READ;
30 output reg rxReady;
31 output reg [7:0] UART_RDATA, rxStatus;
32
33 wire btu, shiftHigh;
34 reg start, nStart,done, doit, nDoit, parity_error, framing_error, overflow_error;
35 reg [1:0] state, nState;
36 reg [9:0] nRX, shiftedReg;
37 reg [18:0] bitTimeCount;
38 reg [3:0] bitCount;
39 reg [18:0] newK;
40
41 // Assign new K Value
42 always@(*)
43 if ({start,doit} == 2'b11)
44 newK = k >> 1;
45 else
46 newK = k;
47
48 // Assign btu wire
49 assign btu = (bitTimeCount == newK);
50
51 // Bit Time Counter
53 if (rst)
55 else if (btu)
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57 else if (doit)
58 bitTimeCount <= bitTimeCount + 19'b1;
59 else
60 bitTimeCount <= bitTimeCount;
61
62 // Done is based on which bitCount value is reached
63 always@(*)
64 case({pen,eight})
65 2'b00: done = (bitCount == 4'b1001);
66 2'b01: done = (bitCount == 4'b1010);
67 2'b10: done = (bitCount == 4'b1010);
68 2'b11: done = (bitCount == 4'b1011);
69 default: done = (bitCount == 4'b1001);
70 endcase
71
72 // Bit Counter
74 if (rst)
76 else if (done)
78 else if ({doit,btu} == 2'b11)
79 bitCount <= bitCount + 4'b1;
80 else
81 bitCount <= bitCount;
82
83 // Assign Shift High
84 assign shiftHigh = (~start & btu);
85
86 // Fill Shift Register with RX values
88 if (rst)
89 nRX <= 10'b0;
90 else if (shiftHigh)
91 nRX <= {rx,nRX[9:1]};
92 else
93 nRX <= nRX;
94
95 // Right Justify Module
96 always@(*)
97 case({eight,pen})
98 2'b00:
99 begin
100 shiftedReg = {2'b0, nRX[9:2]};
101 UART_RDATA = {1'b0, nRX[6:0]};
102 end
103 2'b01:
104 begin
106 UART_RDATA = {1'b0, nRX[6:0]};
107 end
108 2'b10:
109 begin
111 UART_RDATA = { nRX[7:0] };
112 end
113 2'b11:
114 begin
115 shiftedReg = { nRX[9:0] };
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116 UART_RDATA = { nRX[7:0] };
117 end
118 default:
119 begin
121 UART_RDATA = {1'b0, nRX[6:0]};
122 end
123 endcase
124
125 // Assign RX Status
126 always@(*)
127 rxStatus = {3'b0, overflow_error, framing_error, parity_error, 1'b0, rxReady};
128
129 // Parity Error RS flop
131 if (rst)
132 parity_error <= 1'b0;
133 else if (READ[0])
134 parity_error <= 1'b0;
135 else if ({done,pen} == 2'b11)
136 case ({eight,ohel})
137 2'b00 : parity_error <= shiftedReg[7] ^ (^(shiftedReg[6:0]));
138 2'b01 : parity_error <= shiftedReg[7] ^ (~^(shiftedReg[6:0]));
139 2'b10 : parity_error <= shiftedReg[8] ^ (^(shiftedReg[7:0]));
140 2'b11 : parity_error <= shiftedReg[8] ^ (~^(shiftedReg[7:0]));
141 endcase
142 else
143 parity_error <= parity_error;
144
145 // Framing Error RS Flop
147 if (rst)
148 framing_error <= 1'b0;
150 framing_error <= 1'b0;
151 else if(done)
152 case({eight,pen})
153 2'b00 : framing_error <= ~shiftedReg[7];
157 endcase
158 else
159 framing_error <= framing_error;
160
161 // Overflow Error RS Flop
163 if(rst)
164 overflow_error <= 1'b0;
167 else if (rxReady & done)
169 else
170 overflow_error <= overflow_error;
171
172 // RXReady RS Flop
174 if (rst)
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175 rxReady <= 1'b0;
178 else if (done)
180 else
181 rxReady <= rxReady;
182
183 // Flop to register State values
185 if (rst)
186 {state, start,doit} <= 4'b0;
187 else
188 {state, start,doit} <= {nState, nStart,nDoit};
189
190 // Finite State Machine Logic
191 always@(*)
192 case({state, rx, btu, done})
193 5'b00_0_0_0: {nState, nDoit, nStart} = 4'b01_1_1;
217 default: {nState, nDoit, nStart} = 4'b11_0_1;
218 endcase
219
220
221 endmodule
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VIII.7 Address Decode
2 //******************************************************************************//
3 // File name: address_decode.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // address_decode.v //
17 // //
18 // The address_decode block decodes the contents of PORT_ID[2:0] and //
19 // PORT_ID[15] and write/read_strobe. //
20 // //
21 // @input strobe, enable, s2,s1,s0 //
22 // @output q //
23 // //
24 //******************************************************************************//
25 module address_decode(strobe,enable,s2,s1,s0,q);
26 input strobe, enable, s2,s1,s0;
27 output reg [7:0] q;
28 wire enable2;
29
30 assign enable2 = (~enable && strobe);
31
32 always@(*)
33 if(~enable2)
34 q = 8'b0;
35 else
36 case({s2,s1,s0})
37 3'b000: q = 8'b0000_0001;
38 3'b001: q = 8'b0000_0010;
39 3'b010: q = 8'b0000_0100;
40 3'b011: q = 8'b0000_1000;
41 3'b100: q = 8'b0001_0000;
42 3'b101: q = 8'b0010_0000;
43 3'b110: q = 8'b0100_0000;
44 3'b111: q = 8'b1000_0000;
45 default: q = 8'b0000_0000;
46 endcase
47 endmodule
48
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VIII.8 Positive Edge Detect
2 //******************************************************************************//
3 // File name: posEdgeDetect.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //************************************************************************************//
16 // posEdgeDetect.v //
17 //
//
18 // The PED block outputs a 1 when it encounters a positive edge from the input //
19 // It accomplishes this by using two d-flops. The output from both flops is //
20 // sent into an AND gate, with the output of the second flop being inverted. //
21 // This means that PED will only output 1 when q1 is 1 and q2 is still 0. //
22 // //
23 // @input clk, rst, in //
24 // @output yes //
25 // //
26 //************************************************************************************//
27 module posEdgeDetect( clk, rst, in, yes);
29 input wire clk, rst, in;
30 reg q1, q2;
31 output wire yes;
32
33 //Output wire yes is assigned to be and AND gate between the output of the first
34 //flop and the inverted output of the second flop
35 assign yes = (q1 & ~q2);
36
39 //If reset, both flops get 0
40 if(rst)
41 {q1,q2} <= 2'b0;
42 //Otherwise, the first flop gets the value of input and the second gets the
output
43 //of the first flop
44 else
45 {q1,q2} <= {in,q1};
46
47
48
49 endmodule
50
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VIII.9 RS Flop
2 //**********************************************************************************//
3 // File name: SRFlop.v //
4 // //
7 // //
8 // //
14 //**********************************************************************************//
15 //**********************************************************************************//
16 // SRFlop.v //
17 // //
18 // This module is an SR Flop That sets or resets the output based on the //
19 // input reset. //
20 // //
21 // @input clk, rst, funcrst, set //
22 // @output q //
23 // //
24 //**********************************************************************************//
25 module SRFlop(clk,rst,funcrst, set,q);
26 input wire clk, rst,funcrst, set;
27 output reg q;
28
29 // Standard SR Flop
31 if(rst)
32 q<=1'b0;
33 else if(funcrst)
34 q<= 1'b0;
35 else if(set)
36 q<=1'b1;
37 else
38 q<= q;
39
40 endmodule
41
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VIII.10 Seven Segment Display Driver
2 //******************************************************************************//
3 // File name: seven_segment_display.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // seven_segment_display.v //
17 // //
24 //******************************************************************************//
25 module seven_segment_display(clk,rst,data,anode,cathode);
26 input clk,rst;
27 input [15:0] data;
28 output wire [7:0] anode, cathode;
29
30 wire rotate;
31 wire [1:0] sel2;
32 wire [3:0] hexValue;
33
34 // Seven Segment Display Driver
35 rotator rotator1 (.clk(clk), .rst(rst), .rotate(rotate));
36 anodeShiftReg anoder(.clk(clk), .rst(rst), .pulse(rotate), .anode(anode[7:0]));
37 sel2Bit selector (.clk(clk), .rst(rst), .pulse(rotate), .sel(sel2[1:0]));
38 mux4to1 multiplector(.sel(sel2[1:0]), .inVal(data[15:0]), .hexVal(hexValue[3:0]));
39 hexDecoder decoder(.hexVal(hexValue[3:0]), .cathode(cathode[7:0]));
40
41 endmodule
42
18 // This block connects the components to create the seven segment display //
19 // on the Nexys A7 board. //
20 // //
21 // @input clk, rst, [15:0] data //
22 // @output [8;0] anode, [8:0] cathode //
23 // //
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VIII.11 Anode Shift Register
2 //**********************************************************************************//
3 // File name: anodeShiftReg.v //
4 // //
7 // //
8 // //
14 //**********************************************************************************//
15 //**********************************************************************************//
16 // anodeShiftReg.v //
17 // //
18 // The Anode Shift Register block creates serves as a register that sends //
19 // a trailing 0 through the Anode values. The Anode is a low active //
20 // component, meaning that it is on when the value is 0. So whenever the value //
21 // at that specific bit is 0, that is the anode that is being manipulated. //
22 // This block helps to ensure that the anodes are being refreshed at every //
23 // instance of rotate. This Shift Register Only Uses The First 4 Anodes. //
24 // //
25 // @input clk, rst, pulse //
26 // @output [7:0] anode //
27 // //
28 //**********************************************************************************//
29 module anodeShiftReg(clk,rst,pulse,anode);
30 //Declare variables
31 input wire clk,rst,pulse;
32 output reg [7:0] anode;
33 reg [7:0] nAnode;
34
36 always @(posedge rst, posedge clk)
37 //If reset, the anode register gets only the first bit active
38 if(rst) anode <= 8'hFE;
39 //Otherwise, if pulse is active, the anode register gets the value of nAnode
register
40 else if(pulse) anode <= nAnode;
41
42 //Combinational Block
43 always @(*)
44 //Switch Case allows the 0 bit to shift to the left at every instance of pulse
45 case(anode)
46 8'hFE: nAnode = 8'hFD;
47 8'hFD: nAnode = 8'hFB;
48 8'hFB: nAnode = 8'hF7;
49 8'hF7: nAnode = 8'hFE;
50 default: nAnode = 8'hFF;
51 endcase
52
53 endmodule
54
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VIII.12 Rotator
1 `timescale 1ns / 1ns
2 //******************************************************************************//
3 // File name: rotate.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // rotate.v //
17 // //
18 // The pulse block creates a specific 2ms wide clock pulse signal. //
19 // It accomplishes this by counting up every 1ns all the way to //
20 // 199,999. Once the counter reaches that number, 1 pulse signal //
21 // is sent out. //
22 // //
23 // @input clk, rst, //
24 // @output rotate //
25 // //
26 //******************************************************************************//
27 module rotator( clk,rst,rotate);
29 input wire clk, rst;
30 output wire rotate;
31 reg [17:0] counter;
32
33 //Ouput wire rotate is only 1 when the counter has reached that value
34 assign rotate = (counter == 18'd199_999);
35
38 //If rst, the counter gets 0
39 if (rst) counter <= 18'b0;
40 //Otherwise the counter increments by 1
41 else counter <= counter + 18'b1;
42
43
44 endmodule
45
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VIII.13 Select 2 Bit
2 //******************************************************************************//
3 // File name: sel2Bit.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // sel2Bit.v //
17 // //
18 // The sel2Bit block is a 2-bit register that increments by 1 at every //
19 // instance of rotate. This is a useful register because its value will //
20 // be used to guide the mux in the seven-seg display driver //
21 // //
22 // @input clk, rst, pulse //
23 // @output [1:0] sel //
24 // //
25 //******************************************************************************//
26 module sel2Bit(clk, rst, pulse, sel);
28 input wire clk,rst,pulse;
29 output reg [1:0] sel;
30 reg [1:0] nSel;
31
34 //If reset, the select register gets 0
35 if(rst)
36 sel <= 2'b0;
37 //Otherwise, the select register gets the value of nSel register
38 else
39 sel <= nSel;
40
42 always @(*)
43 //If pulse is active, select increments up by 1
44 if(pulse)
45 nSel = sel + 2'b1;
46 //Otherwise select remanins the same
47 else
48 nSel = sel;
49
50
51 endmodule
52
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VIII.14 Multiplexor 4 to 1
2 //******************************************************************************//
3 // File name: mux4to1.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // mux4to1.v //
17 // //
18 // The mux8to1 block grabs 4 bits of data from a 16-bit input. //
19 // The mux chooses which data to grab based on the 2-bit select value. //
20 // With select, each value represents 4 bits of data out of the 16-bit. //
21 // The 4 bits that are grabbed are then output to the hexDecoder
//
22 // //
23 // @input sel, [15:0]inVal //
24 // @output [3:0]hexVal //
25 // //
26 //******************************************************************************//
27 module mux4to1(sel, inVal, hexVal);
29 input wire [2:0] sel;
30 input wire [15:0] inVal;
31 output reg [3:0] hexVal;
32
34 always@(*)
35 //Case Statement of select means that the value of select decides which
36 //4 bits of the 16-bit register are selected and output
37 case(sel)
38 2'b00: hexVal = inVal[3:0];
39 2'b01: hexVal = inVal[7:4];
40 2'b10: hexVal = inVal[11:8];
41 2'b11: hexVal = inVal[15:12];
42 default: hexVal = inVal[3:0];
43 endcase
44
45 endmodule
46
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VIII.15 Hex Decoder
2 //******************************************************************************//
3 // File name: hexDecoder.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // hexDecoder.v //
17 // //
18 // The hexDecoder block converts 4bit values into readable hexadecimal //
19 // values on a cathode. It accomplishes this by setting specific cathode //
20 // either on or off, which will translate to the cathode looking like the //
21 // hexadecimal value it is representing. The cathode bits are low active //
22 // //
23 // @input [3:0] hexVal //
24 // @output [7:0] cathode //
25 // //
26 //******************************************************************************//
27 module hexDecoder(hexVal, cathode);
29 input wire [3:0] hexVal;
30 output reg [7:0] cathode;
31
33 always @(*)
34 //Case statement of hexVal serves as a decoder
35 //Whatever hexadecimal value is stored in hexVal
36 //is converted into a readable cathode value
37 case(hexVal)
38 4'h0: cathode[7:0] = 8'b11000000;
39 4'h1: cathode[7:0] = 8'b11111001;
40 4'h2: cathode[7:0] = 8'b10100100;
41 4'h3: cathode[7:0] = 8'b10110000;
42 4'h4: cathode[7:0] = 8'b10011001;
43 4'h5: cathode[7:0] = 8'b10010010;
44 4'h6: cathode[7:0] = 8'b10000010;
45 4'h7: cathode[7:0] = 8'b11111000;
46 4'h8: cathode[7:0] = 8'b10000000;
47 4'h9: cathode[7:0] = 8'b10010000;
48 4'ha: cathode[7:0] = 8'b10001000;
49 4'hb: cathode[7:0] = 8'b10000011;
50 4'hc: cathode[7:0] = 8'b11000110;
51 4'hd: cathode[7:0] = 8'b10100001;
52 4'he: cathode[7:0] = 8'b10000110;
53 4'hf: cathode[7:0] = 8'b10001110;
54 //The default ouputs a "0"
55 default: cathode[7:0] = 8'b10000000;
56 endcase
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57
58 endmodule
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VIII.16 TramelBlaze
1 //****************************************************************//
2 // This document contains information proprietary to the //
3 // CSULB student that created the file - any reuse without //
4 // adequate approval and documentation is prohibited //
5 // //
6 // Class: CECS 460 //
7 // Project name: TRAMBLAZE PROCESSOR //
8 // File name: tramelblaze.v //
9 // Release: 1.0 Release Date 17Feb2016 //
10 // Release: 1.1 Release Date 25Feb2016 //
11 // Release: 1.4 Release Date 04Mar2016 //
12 // Release: 1.5 Release Date 17Mar2016 //
13 // Release: 1.6 Release Date 04May2016 //
14 // Release: 2.0 Release Date 29Aug2016 //
17 // Release: 4.0 Release Date 23aug2017 //
18 // Release: 5.0 Release Date 07nov2017 //
19 // Release: 5.0 Release Date 26jan2020 - Vivado Version //
20 // //
21
22
//
//
Created by John Tramel on 25January2016.
Copyright 2016 John Tramel. All rights reserved.
//
//
23 // Copyright 2017 John Tramel. All rights reserved. //
24 // //
25 // Abstract: Top level for TRAMBLAZE processor //
26 // Edit history: 2016JAN25 - created //
27 // 2016FEB25 - corrected SHIFT/ROTATE //
28 // made sure that CARRY set correctly //
29 // 2016FEB29 - added MEMHIOL //
30 // MEMHIOL=1 memory access, =0 I/O access //
31 // added 512 x 16 scratchpad ram //
32 // added 1st FETCH/STORE States //
33 // 2016MAR03 - 512x16 scratch ram debugged //
34 // 2016MAR03 - 512x16 scratch ram debugged //
35 // 2016MAR17 - 128x16 stack ram debugged //
36 // 04May2016 - Stack RAM address fix //
37 // 28Feb2017 - Removed MEMHIOL //
38 // 30Mar2017 - Fixed NOP -thanks Chou Thao //
39 // //
42 // of no one else. //
43 // //
44 // In the event other code sources are utilized I will //
45 // document which portion of code and who is the author //
46 // //
47 // In submitting this code I acknowledge that plagiarism //
48 // in student project work is subject to dismissal from the class //
49 //****************************************************************//
50
51 `timescale 1ns/1ns
52
53 module tramelblaze (CLK, RESET, IN_PORT, INTERRUPT,
54 OUT_PORT, PORT_ID, READ_STROBE, WRITE_STROBE, INTERRUPT_ACK,
55 ADDRESS, INSTRUCTION);
56
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57 input CLK;
58 input RESET;
59 input [15:0] IN_PORT;
60 input INTERRUPT;
61
62 output [15:0] OUT_PORT;
63 output [15:0] PORT_ID;
64 output READ_STROBE;
65 output WRITE_STROBE;
66 output INTERRUPT_ACK;
67
68 output [11:0] ADDRESS;
69 input [15:0] INSTRUCTION;
70
71 reg [15:0] inst_reg; // instruction register
72 reg [15:0] const_reg; // constant register
73 reg [15:0] pc; // program counter
74 reg [15:0] regfile [0:15]; // 16 x 16 register file
75 reg [16:0] alu_out; // output of ALU
76 reg [16:0] alu_out_reg; // output of ALU registered
77 reg [ 3:0] stateX,stateQ; // state machine variable
78 wire [11:0] ADDRESS; // ADDRESS to instruction memory
79 reg [15:0] address_mux; // mux to select next address
80 reg int_enable; // enable interrupt
81 reg int_proc; // processor interrupt
82 wire carryPX; // preserve carry bit
83 reg carryPQ; // preserve carry bit
84 wire zeroPX; // preserve zero bit
85 reg zeroPQ; // preserve zero bit
86 reg zeroX,zeroQ; // flag
87 reg carryX,carryQ; // flag
88 reg loadKX,loadKQ; // load constant register
89 reg ldirX,ldirQ; // load instruction register
90 wire ldk; // load constant register
91 reg ldpcX,ldpcQ; // load program counter
92 reg ldflagX,ldflagQ; // load carry and zero registers
93 reg ldflagPX,ldflagPQ; // preserve load carry and zero registers
94 reg wtrfX,wtrfQ; // write register file
95 reg wtsrX,wtsrQ; // write scratchpad ram
96 reg sel_alubX,sel_alubQ; // select alu operand b
97 reg pushX,pushQ; // push pc address onto stack
98 reg popX,popQ; // pop pc address from stack
99 reg enintX,enintQ; // enable interrupts
100 reg disintX,disintQ; // disable interrupts
101 reg [1:0] sel_pcX,sel_pcQ; // select pc source
102 reg sel_portidX,sel_portidQ; // select source for port id
103 reg [2:0] sel_rfwX,sel_rfwQ; // select reg write data source
104 reg [2:0] flag_selX,flag_selQ; // select source to change zero/carry
105 reg [4:0] alu_opX,alu_opQ; // select which operation alu does
106 reg enableportidX,enableportidQ; // allow port id to switch
107 reg enableinportX,enableinportQ; // allow in port to be read
108 reg enableoutportX,enableoutportQ; // allow out port to switch
109 reg readstrobeX,readstrobeQ; // set read strobe output
110 reg writestrobeX,writestrobeQ; // set write strobe output
111 reg interruptackX,interruptackQ; // interrupt acknowledge
112 wire [15:0] pc_min1; // program counter minus one
113 wire [15:0] stackWdata; // data written into stack
114
115 wire [6:0] opcode; // current opcode being executed
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116 wire [3:0] regX_adrs, regY_adrs; // address to x and y registers
117 reg [15:0] rf_wdata; // data to write into register file
118 wire [15:0] stackRdata; // contents of stack pointed to (last write)
119 wire [15:0] alu_a; // input to ALU A
120 wire [15:0] alu_b; // input to ALUB
121 wire INTERRUPT_ACK;
122 wire READ_STROBE;
123 wire WRITE_STROBE;
124 wire [15:0] regA; // output of register file - A
125 wire [15:0] regB; // output of register file - B
126 wire [15:0] scratch_dout; // scratch pad ram output
127 wire [8:0] scratch_adrs;
128 wire [15:0] scratch_din;
129 wire [ 6:0] stackAdrs;
130 reg [ 6:0] stackPointQ;
131 wire [ 6:0] stackPointD;
132
133 // assume instruction memory is 8K deep (000 - FFF)
134
135 parameter INTERRUPT_ADDRESS = 16'H0FFE;
136
137 // parameters for STATES
138
139 parameter FETCH = 5'H00, DECODE = 5'H01, SECOND = 5'H02, THIRD = 5'H03, EXECUTE =
5'H04,
140 ENDIT = 5'H05, ENDCALL = 5'H06, ENDRET = 5'H07, ENDRET2 = 5'H08, ENDRET3 =
5'H09,
141 OUTPUT_XK_2 = 5'H0A, OUTPUT_XY_2 = 5'H0B, INPUT_XP_2 = 5'H0C, INPUT_XY_2 =
5'H0D,
142 FETCH_XK_2 = 5'H0E, FETCH_XY_2 = 5'H0F, STORE_XK_2 = 5'H10, STORE_XY_2 = 5'H11;
143
144 // parameters for ALU OPERATIONS
145
146 parameter NOTHING = 5'H00, ADD = 5'H01, ADDC = 5'H02, AND = 5'H03,
147 SUB = 5'H04, OR = 5'H05, RLX = 5'H06, RRX = 5'H07,
148 SL0X = 5'H08, SL1X = 5'H09, SLAX = 5'H0A, SLXX = 5'H0B,
149 SR0X = 5'H0C, SR1X = 5'H0D, SRAX = 5'H0E, SRXX = 5'H0F,
150 XOR = 5'H10, SUBC = 5'H11;
151
152 // parameters for OPCODES
153 //
154 parameter NOP = 7'H00, ADD_XK = 7'H02, ADD_XY = 7'H04,
155 ADDCY_XK = 7'H06, ADDCY_XY = 7'H08, AND_XK = 7'H0A,
156 AND_XY = 7'H0C, CALL_AAA = 7'H0E, CALLC_AAA = 7'H10,
157 CALLNC_AAA = 7'H12, CALLZ_AAA = 7'H14, CALLNZ_AAA = 7'H16,
158 COMP_XK = 7'H18, COMP_XY = 7'H1A, DISINT = 7'H1C,
159 ENINT = 7'H1E, INPUT_XY = 7'H20, INPUT_XP = 7'H22,
160 JUMP_AAA = 7'H24, JUMPC_AAA = 7'H26, JUMPNC_AAA = 7'H28,
161 JUMPZ_AAA = 7'H2A, JUMPNZ_AAA = 7'H2C, LOAD_XK = 7'H2E,
162 LOAD_XY = 7'H30, OR_XK = 7'H32, OR_XY = 7'H34,
163 OUTPUT_XY = 7'H36, OUTPUT_XK = 7'H38, RETURN = 7'H3A,
164 RETURN_C = 7'H3C, RETURN_NC = 7'H3E, RETURN_Z = 7'H40,
165 RETURN_NZ = 7'H42, RETURN_DIS = 7'H44, RETURN_EN = 7'H46,
166 RL_X = 7'H48, RR_X = 7'H4A, SL0_X = 7'H4C,
167 SL1_X = 7'H4E, SLA_X = 7'H50, SLX_X = 7'H52,
168 SR0_X = 7'H54, SR1_X = 7'H56, SRA_X = 7'H58,
169 SRX_X = 7'H5A, SUB_XK = 7'H5C, SUB_XY = 7'H5E,
170 SUBC_XK = 7'H60, SUBC_XY = 7'H62, TEST_XK = 7'H64,
171 TEST_XY = 7'H66, XOR_XK = 7'H68, XOR_XY = 7'H6A,
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Document Name:
Final Specification
172 FETCH_XK = 7'H70, FETCH_XY = 7'H72, STORE_XK = 7'H74,
173 STORE_XY = 7'H76;
174
175 assign READ_STROBE = readstrobeQ;
176 assign WRITE_STROBE = writestrobeQ;
177 assign INTERRUPT_ACK = interruptackQ;
178
179 //////////////////////////////
180 // address register - PC //
181 //////////////////////////////
182
183 assign ADDRESS = pc[11:0];
184
185 always @(posedge CLK, posedge RESET)
186 if (RESET)
187 pc <= 16'b0;
188 else
189 if (ldpcQ)
190 pc <= address_mux;
191
192 always @(*)
193 case(sel_pcQ)
194 2'b00: address_mux = pc + 16'b1;
195 2'b01: address_mux = stackRdata;
196 2'b10: address_mux = const_reg;
197 2'b11: address_mux = INTERRUPT_ADDRESS;
198 endcase
199
200 //////////////////////////////
201 // address stack //
202 //////////////////////////////
203
204 assign ldsp = popQ | pushQ;
205
207 if (RESET) stackPointQ <= 7'b0; else
208 if (ldsp) stackPointQ <= stackPointD;
209
210 assign pc_min1 = pc - 16'b1;
211 assign stackWdata = int_proc ? pc_min1 : pc;
212
213
214 assign stackAdrs = pushQ ? stackPointQ : stackPointQ - 7'b1;
215 assign stackPointD = pushQ ? stackAdrs + 7'b1 : stackAdrs;
216
217 stack_ram stkr (
218 .a (stackAdrs),
219 .d (stackWdata),
220 .we (pushQ),
221 .clk (CLK),
222 .spo (stackRdata)
223 );
224
225 //////////////////////////////
226 // instruction register //
227 //////////////////////////////
228
229 assign opcode = inst_reg[14:8]; // opcode for instruction decode
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Final Specification
230 assign regY_adrs = inst_reg[7:4];
231 assign regX_adrs = inst_reg[3:0];
232 assign ldk = inst_reg[15] && (stateQ==DECODE);
233
235 if (RESET) inst_reg <= 16'b0; else
236 if (ldirQ) inst_reg <= INSTRUCTION;
237
238 //////////////////////////////
239 // constant register //
240 //////////////////////////////
241
243 if (RESET) const_reg <= 16'b0; else
244 if (loadKQ) const_reg <= INSTRUCTION;
245
246 //////////////////////////////
247 // interrupt control //
248 //////////////////////////////
249
251 if (RESET) int_enable <= 1'b0; else
252 if (enintQ) int_enable <= 1'b1; else
253 if (disintQ) int_enable <= 1'b0;
254
256 if (RESET) int_proc <= 1'b0; else
257 if (INTERRUPT_ACK) int_proc <= 1'b0; else
258 if (int_enable & INTERRUPT) int_proc <= 1'b1;
259
260 //////////////////////////////
261 // register file operations //
262 //////////////////////////////
263
264 assign regA = regfile[regX_adrs];
265 assign regB = regfile[regY_adrs];
266
267 always @(*)
268 case (sel_rfwQ)
269 3'b000: rf_wdata = alu_out[15:0];
270 3'b001: rf_wdata = IN_PORT & {16{enableinportQ}};
271 3'b010: rf_wdata = const_reg;
272 3'b011: rf_wdata = regB;
273 3'b100: rf_wdata = scratch_dout;
274 default: rf_wdata = alu_out[15:0];
275 endcase
276
278 if (RESET) begin
279 regfile[0] <= 16'b0;
280 regfile[1] <= 16'b0;
281 regfile[2] <= 16'b0;
282 regfile[3] <= 16'b0;
283 regfile[4] <= 16'b0;
284 regfile[5] <= 16'b0;
285 regfile[6] <= 16'b0;
286 regfile[7] <= 16'b0;
287 regfile[8] <= 16'b0;
288 regfile[9] <= 16'b0;
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Final Specification
289 regfile[10] <= 16'b0;
290 regfile[11] <= 16'b0;
291 regfile[12] <= 16'b0;
292 regfile[13] <= 16'b0;
293 regfile[14] <= 16'b0;
294 regfile[15] <= 16'b0;
295 end else
296 if (wtrfQ) begin
297 regfile[regX_adrs] <= rf_wdata;
298 end
299
300 //////////////////////////////
301 // CARRY/ZERO operations //
302 //////////////////////////////
303
304 assign zeroPX = zeroQ;
305 assign carryPX = carryQ;
306
308 if (RESET) {zeroPQ,carryPQ} <= 2'b0; else
309 if (ldflagPQ) {zeroPQ,carryPQ} <= {zeroPX,carryPX};
310
312 if (RESET) {zeroQ,carryQ} <= 2'b0; else
313 if (ldflagQ) {zeroQ,carryQ} <= {zeroX,carryX};
314
315 always @(*)
316 case(flag_selQ)
317 3'h0: {zeroX, carryX} = {zeroQ, carryQ};
318 3'h1: {zeroX, carryX} = {~|alu_out[15:0],1'b0};
319 3'h2: {zeroX, carryX} = {~|alu_out[15:0],alu_out[16]};
320 3'h3: {zeroX, carryX} = {zeroPQ, carryPQ};
323 3'h6: {zeroX, carryX} = {~|(alu_a & alu_b),^(alu_a & alu_b)};
324 default: {zeroX, carryX} = {zeroQ, carryQ};
325 endcase
326
327 //////////////////////////////
328 // ALU operations //
329 //////////////////////////////
330
331 assign alu_a = regA;
332 assign OUT_PORT = regA & {16{enableoutportQ}};
333 assign alu_b = (sel_alubQ) ? const_reg : regB;
334 assign PORT_ID = (sel_portidQ) ? (const_reg & {16{enableportidQ}}) : (alu_b &
{16{enableportidQ}});
335
337 if (RESET) alu_out_reg <= 17'b0;
338 else alu_out_reg <= alu_out;
339
340 always @(*)
341 case(alu_opQ)
342 NOTHING: alu_out = alu_out_reg; // noop so no change
343 ADD: alu_out = alu_a + alu_b; // ADD
344 ADDC: alu_out = alu_a + alu_b + carryQ; // ADDC
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Document Name:
Final Specification
363 ///////////////////////////////
364 // Scratchpad RAM Instance //
365 // 512x16 Scratchpad Memory //
366 ///////////////////////////////
367
368 assign scratch_din = alu_a;
369 assign scratch_adrs = alu_b[8:0];
370
371 scratch_ram sr (
372 .clk (CLK),
373 .we (wtsrQ),
374 .a (scratch_adrs),
375 .d (scratch_din),
376 .spo (scratch_dout)
377 );
378
379 ///////////////////////////////
380 // Instruction Control Logic //
381 ///////////////////////////////
382
383
385 if (RESET) begin
386 stateQ <= FETCH; // start up state variable
387 ldirQ <= 1'b1; // load instruction register
388 ldpcQ <= 1'b1; // load program counter
389 ldflagQ <= 1'b0; // load carry and zero registers
390 ldflagPQ <= 1'b0; // load preserve carry and zero registers
391 loadKQ <= 1'b0; // load constant register
392 wtrfQ <= 1'b0; // write register file
393 wtsrQ <= 1'b0; // write scratch pad ram
394 sel_alubQ <= 1'b0; // select alu operand b
395 pushQ <= 1'b0; // push pc address onto stack
396 popQ <= 1'b0; // pop pc address from stack
397 enintQ <= 1'b0; // enable interrupts
398 disintQ <= 1'b0; // disable interrupts
399 sel_pcQ <= 2'b0; // select pc source
400 sel_portidQ <= 1'b0; // select source for port id
401 sel_rfwQ <= 3'b0; // select reg write data source
402 flag_selQ <= 2'b0; // select source to change zero/carry
345 SUB: alu_out = alu_a - alu_b; // SUB (COMP)
346 SUBC: alu_out = alu_a - alu_b - carryQ; // SUBC
347 AND: alu_out = alu_a & alu_b; // AND
348 OR: alu_out = alu_a | alu_b; // OR
349 XOR: alu_out = alu_a ^ alu_b; // XOR
350 RLX: alu_out = {alu_a[15],alu_a[14:0],alu_a[15]}; // RL rX
351 RRX: alu_out = {alu_a[ 0],alu_a[0],alu_a[15:1]}; // RR rX
352 SL0X: alu_out = {alu_a[15],alu_a[14:0],1'b0}; // SL0 rX
353 SL1X: alu_out = {alu_a[15],alu_a[14:0],1'b1}; // SL1 rX
354 SLAX: alu_out = {alu_a[15],alu_a[14:0],carryQ}; // SLA rX
355 SLXX: alu_out = {alu_a[15],alu_a[14:0],alu_a[0]}; // SLX rX
356 SR0X: alu_out = {alu_a[ 0],1'b0,alu_a[15:1]}; // SR0 rX
357 SR1X: alu_out = {alu_a[ 0],1'b1,alu_a[15:1]}; // SR1 rX
358 SRAX: alu_out = {alu_a[ 0],carryQ,alu_a[15:1]}; // SRA rX
359 SRXX: alu_out = {alu_a[ 0],alu_a[15],alu_a[15:1]}; // SRX rX
360 default: alu_out = 16'b0;
361 endcase
362
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Final Specification
403 alu_opQ <= 5'b0; // select which operation alu does
404 enableportidQ <= 1'b0; // allow port id to switch
405 enableinportQ <= 1'b0; // allow in port to be read
406 enableoutportQ <= 1'b0; // allow out port to switch
407 readstrobeQ <= 1'b0; // set read strobe output
408 writestrobeQ <= 1'b0; // set write strobe output
409 interruptackQ <= 1'b0; // set interrupt ack
410 end
411 else
412 begin
413 stateQ <= stateX; // update up state variable
414 ldirQ <= ldirX; // load instruction register
415 ldpcQ <= ldpcX; // load program counter
416 ldflagQ <= ldflagX; // load carry and zero registers
417 ldflagPQ <= ldflagPX; // load preserve carry and zero registers
418 loadKQ <= loadKX; // load constant register
419 wtrfQ <= wtrfX; // write register file
420 wtsrQ <= wtsrX; // write scratch pad ram
421 sel_alubQ <= sel_alubX; // select alu operand b
422 pushQ <= pushX; // push pc address onto stack
423 popQ <= popX; // pop pc address from stack
424 enintQ <= enintX; // enable interrupts
425 disintQ <= disintX; // disable interrupts
426 sel_pcQ <= sel_pcX; // select pc source
427 sel_portidQ <= sel_portidX; // select source for port id
428 sel_rfwQ <= sel_rfwX; // select reg write data source
429 flag_selQ <= flag_selX; // select source to change zero/carry
430 alu_opQ <= alu_opX; // select which operation alu does
431 enableportidQ <= enableportidX; // allow port id to switch
432 enableinportQ <= enableinportX; // allow in port to be read
433 enableoutportQ <= enableoutportX; // allow out port to switch
434 readstrobeQ <= readstrobeX; // set read strobe output
435 writestrobeQ <= writestrobeX; // set write strobe output
436 interruptackQ <= interruptackX; // set interrupt ack
437 end
438
439 /////////////////////////////////////////
440 // State Machine Decision Making Block //
441 /////////////////////////////////////////
442
443 always@(*)
444 begin
445 ldirX = 1'b0; // load instruction register
446 ldpcX = 1'b0; // load program counter
447 ldflagX = 1'b0; // load carry and zero registers
448 ldflagPX = 1'b0; // load preserve carry and zero registers
449 loadKX = 1'b0; // load constant register
450 wtrfX = 1'b0; // write register file
451 wtsrX = 1'b0; // write scratch pad ram
452 sel_alubX = 1'b0; // select alu operand b
453 pushX = 1'b0; // push pc address onto stack
454 popX = 1'b0; // pop pc address from stack
455 enintX = 1'b0; // enable interrupts
456 disintX = 1'b0; // disable interrupts
457 sel_pcX = 2'b0; // select pc source
458 sel_portidX = 1'b0; // select source for port id
459 sel_rfwX = 3'b0; // select reg write data source
460 flag_selX = 2'b0; // select source to change zero/carry
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Final Specification
461 alu_opX = 5'b0; // select which operation alu does
462 enableportidX = 1'b0; // allow port id to switch
463 enableinportX = 1'b0; // allow in port to be read
464 enableoutportX = 1'b0; // allow out port to switch
465 readstrobeX = 1'b0; // set read strobe output
466 writestrobeX = 1'b0; // set write strobe output
467 interruptackX = 1'b0; // set interrupt ack
468 stateX = FETCH;
469
470 case(stateQ)
471 FETCH: begin
472 if (int_proc) begin
473 sel_pcX=2'b11; // goto interrupt
474 ldpcX=1'b1; // update new pc
475 pushX =1'b1; // push next pc onto stack
476 disintX=1'b1; // entering interrupt clear interrupt
477 ldflagPX=1'b1; // preserve the flag registers
478 interruptackX=1'b1; // set interrupt ack
479 stateX=ENDRET2; // let int_proc reset
480 end
481 else begin
482 ldpcX=1'b0;
483 ldirX=1'b0;
484 stateX=DECODE;
485 end
486 end
487
488 DECODE: begin
489 if(ldk) begin
490 loadKX=1'b1;
491 stateX=SECOND;
492 end
493 else begin
494 stateX=EXECUTE;
495 end
496 end
497
498 SECOND: begin
499 ldpcX=1'b1;
500 stateX=THIRD;
501 end
502
503 THIRD: begin
504 stateX=EXECUTE;
505 end
506
507 EXECUTE: begin
508 case(opcode)
509 NOP:stateX=ENDIT;
510
511 ADD_XK: begin
512 wtrfX=1'b1;
513 sel_alubX=1'b1;
514 flag_selX=3'b010;
515 ldflagX=1'b1;
516 alu_opX=ADD;
517 stateX=ENDIT;
518 end
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Final Specification
519
520 ADD_XY: begin
521 wtrfX=1'b1;
523 alu_opX=ADD;
524 ldflagX=1'b1;
525 stateX=ENDIT;
526 end
527
528 ADDCY_XK: begin
529 wtrfX=1'b1;
530 sel_alubX=1'b1;
532 ldflagX=1'b1;
533 alu_opX=ADDC;
534 stateX=ENDIT;
535 end
536
537 ADDCY_XY: begin
538 wtrfX=1'b1;
540 ldflagX=1'b1;
541 alu_opX=ADDC;
542 stateX=ENDIT;
543 end
544
545 AND_XK: begin
546 wtrfX=1'b1;
547 sel_alubX=1'b1;
549 ldflagX=1'b1;
550 alu_opX=AND;
551 stateX=ENDIT;
552 end
553
554 AND_XY: begin
555 wtrfX=1'b1;
556 alu_opX=AND;
558 ldflagX=1'b1;
559 stateX=ENDIT;
560 end
561
562 CALL_AAA: begin
563 pushX=1'b1;
564 sel_pcX=2'b10;
565 ldpcX=1'b1;
566 stateX=ENDCALL;
567 end
568
569 CALLC_AAA: begin
570 if(carryQ) begin
571 pushX=1'b1;
572 sel_pcX=2'b10;
573 ldpcX=1'b1;
574 stateX=ENDCALL;
575 end else
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Final Specification
576 stateX=ENDIT;
577 end
578
579 CALLNC_AAA: begin
580 if(!carryQ) begin
581 pushX=1'b1;
582 sel_pcX=2'b10;
583 ldpcX=1'b1;
584 stateX=ENDCALL;
585 end else
586 stateX=ENDIT;
587 end
588
589 CALLZ_AAA: begin
590 if(zeroQ) begin
591 pushX=1'b1;
592 sel_pcX=2'b10;
593 ldpcX=1'b1;
594 stateX=ENDCALL;
595 end else
596 stateX=ENDIT;
597 end
598
599 CALLNZ_AAA: begin
600 if(!zeroQ) begin
601 pushX=1'b1;
602 sel_pcX=2'b10;
603 ldpcX=1'b1;
604 stateX=ENDCALL;
605 end else
606 stateX=ENDIT;
607 end
608
609 COMP_XK: begin
610 alu_opX=SUB;
611 sel_alubX=1'b1;
613 ldflagX=1'b1;
614 stateX=ENDIT;
615 end
616
617 COMP_XY: begin
618 alu_opX=SUB;
620 ldflagX=1'b1;
621 stateX=ENDIT;
622 end
623
624 DISINT: begin
625 disintX=1'b1;
626 stateX=ENDCALL;
627 end
628
629 ENINT: begin
630 enintX=1'b1;
631 stateX=ENDCALL;
632 end
633
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Final Specification
634 STORE_XY:begin
635 wtsrX=1'b1;
636 stateX=ENDIT;
637 end
638
639 STORE_XK: begin
640 sel_alubX=1'b1;
641 wtsrX=1'b1;
642 stateX=ENDIT;
643 end
644
645 FETCH_XY:begin
646 stateX=FETCH_XY_2;
647 end
648
649 FETCH_XK: begin
650 sel_alubX=1'b1;
651 stateX=FETCH_XK_2;
652 end
653
654 INPUT_XY:begin
655 enableportidX=1'b1;
656 enableinportX=1'b1;
657 stateX=INPUT_XY_2;
658 end
659
660 INPUT_XP: begin
663 sel_portidX=1'b1;
664 stateX=INPUT_XP_2;
665 end
666
667 JUMP_AAA: begin
668 sel_pcX=2'b10;
669 ldpcX=1'b1;
670 ldirX=1'b1;
671 stateX=ENDCALL;
672 end
673
674 JUMPC_AAA: begin
676 sel_pcX=2'b10;
677 ldpcX=1'b1;
678 ldirX=1'b1;
679 end
680 stateX=ENDCALL;
681 end
682
683 JUMPNC_AAA: begin
685 sel_pcX=2'b10;
686 ldpcX=1'b1;
687 ldirX=1'b1;
688 end
689 stateX=ENDCALL;
690 end
691
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Document Name:
Final Specification
692 JUMPZ_AAA: begin
693 if(zeroQ) begin
694 sel_pcX=2'b10;
695 ldpcX=1'b1;
696 ldirX=1'b1;
697 end
698 stateX=ENDCALL;
699 end
700
701 JUMPNZ_AAA: begin
703 sel_pcX=2'b10;
704 ldpcX=1'b1;
705 ldirX=1'b1;
706 end
707 stateX=ENDCALL;
708 end
709
710 LOAD_XK: begin
711 sel_rfwX=3'b010;
712 wtrfX=1'b1;
713
714 stateX=ENDIT;
715 end
716
717 LOAD_XY: begin
719 wtrfX=1'b1;
720 stateX=ENDIT;
721 end
722
723 OR_XK: begin
724 wtrfX=1'b1;
726 alu_opX=OR;
727 sel_alubX=1'b1;
728 ldflagX=1'b1;
729 stateX=ENDIT;
730 end
731
732 OR_XY: begin
733 wtrfX=1'b1;
735 alu_opX=OR;
736 ldflagX=1'b1;
737 stateX=ENDIT;
738 end
739
740 OUTPUT_XK: begin
743 enableoutportX=1'b1;
744 stateX=OUTPUT_XK_2;
745 end
746
747 OUTPUT_XY: begin
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Final Specification
750 stateX=OUTPUT_XY_2;
751 end
752
753 RETURN: begin
754 popX=1'b1;
755 stateX=ENDRET;
756 end
757
758 RETURN_C: begin
760 popX=1'b1;
761 stateX=ENDRET;
762 end else
763 stateX=ENDIT;
764 end
765
766 RETURN_NC: begin
768 popX=1'b1;
769 stateX=ENDRET;
770 end else
771 stateX=ENDIT;
772 end
773
774 RETURN_Z: begin
775 if(zeroQ) begin
776 popX=1'b1;
777 stateX=ENDRET;
778 end else
779 stateX=ENDIT;
780 end
781
782 RETURN_NZ: begin
784 popX=1'b1;
785 stateX=ENDRET;
786 end else
787 stateX=ENDIT;
788 end
789
790 RETURN_DIS: begin
792 ldflagX=1'b1;
793 disintX=1'b1;
794 popX=1'b1;
795 stateX=ENDRET;
796 end
797
798 RETURN_EN: begin
800 ldflagX=1'b1;
801 enintX=1'b1;
802 popX=1'b1;
803 stateX=ENDRET;
804 end
805
806 RL_X: begin
807 wtrfX=1'b1;
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Final Specification
808 alu_opX=RLX;
810 ldflagX=1'b1;
811 stateX=ENDIT;
812 end
813
814 RR_X: begin
815 wtrfX=1'b1;
816 alu_opX=RRX;
818 ldflagX=1'b1;
819 stateX=ENDIT;
820 end
821
822 SL0_X: begin
823 wtrfX=1'b1;
824 alu_opX=SL0X;
826 ldflagX=1'b1;
827 stateX=ENDIT;
828 end
829
830 SL1_X: begin
831 wtrfX=1'b1;
832 alu_opX=SL1X;
834 ldflagX=1'b1;
835 stateX=ENDIT;
836 end
837
838 SLA_X: begin
839 wtrfX=1'b1;
840 alu_opX=SLAX;
842 ldflagX=1'b1;
843 stateX=ENDIT;
844 end
845
846 SLX_X: begin
847 wtrfX=1'b1;
848 alu_opX=SLXX;
850 ldflagX=1'b1;
851 stateX=ENDIT;
852 end
853
854 SR0_X: begin
855 wtrfX=1'b1;
856 alu_opX=SR0X;
858 ldflagX=1'b1;
859 stateX=ENDIT;
860 end
861
862 SR1_X: begin
863 wtrfX=1'b1;
864 alu_opX=SR1X;
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Final Specification
866 ldflagX=1'b1;
867 stateX=ENDIT;
868 end
869
870 SRA_X: begin
871 wtrfX=1'b1;
872 alu_opX=SRAX;
874 ldflagX=1'b1;
875 stateX=ENDIT;
876 end
877
878 SRX_X: begin
879 wtrfX=1'b1;
880 alu_opX=SRXX;
882 ldflagX=1'b1;
883 stateX=ENDIT;
884 end
885
886 SUB_XK: begin
887 wtrfX=1'b1;
888 sel_alubX=1'b1;
889 alu_opX=SUB;
891 ldflagX=1'b1;
892 stateX=ENDIT;
893 end
894
895 SUB_XY: begin
896 wtrfX=1'b1;
898 alu_opX=SUB;
899 ldflagX=1'b1;
900 stateX=ENDIT;
901 end
902
903 SUBC_XK: begin
904 wtrfX=1'b1;
905 sel_alubX=1'b1;
906 alu_opX=SUBC;
908 ldflagX=1'b1;
909 stateX=ENDIT;
910 end
911
912 SUBC_XY: begin
913 wtrfX=1'b1;
914 alu_opX=SUBC;
916 ldflagX=1'b1;
917 stateX=ENDIT;
918 end
919
920 TEST_XK: begin
921 sel_alubX=1'b1;
922 alu_opX=AND;
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Document Name:
Final Specification
924 ldflagX=1'b1;
925 stateX=ENDIT;
926 end
927
928 TEST_XY: begin
929 alu_opX=AND;
931 ldflagX=1'b1;
932 stateX=ENDIT;
933 end
934
935 XOR_XK: begin
936 wtrfX=1'b1;
937 sel_alubX=1'b1;
938 alu_opX=XOR;
940 ldflagX=1'b1;
941 stateX=ENDIT;
942 end
943
944 XOR_XY:begin
945 wtrfX=1'b1;
946 alu_opX=XOR;
948 ldflagX=1'b1;
949 stateX=ENDIT;
950 end
951
952 default:stateX=FETCH;
953
954 endcase
955 end
956
957 INPUT_XP_2: begin
960 readstrobeX=1'b1;
963 wtrfX=1'b1;
964 stateX=ENDIT;
965 end
966
967 INPUT_XY_2:begin
970 readstrobeX=1'b1;
972 wtrfX=1'b1;
973 stateX=ENDIT;
974 end
975
976 OUTPUT_XK_2: begin
980 writestrobeX=1'b1;
981 stateX=ENDIT;
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Final Specification
982 end
983
984 OUTPUT_XY_2: begin
987 writestrobeX=1'b1;
988 stateX=ENDIT;
989 end
990
991 FETCH_XK_2:begin
993 wtrfX=1'b1;
994 stateX=ENDIT;
995 end
996
997 FETCH_XY_2:begin
999 wtrfX=1'b1;
1000 stateX=ENDIT;
1001 end
1002
1003 ENDCALL: begin
1004 stateX=ENDIT;
1005 end
1006
1007 ENDRET: begin
1008 sel_pcX=2'b01;
1009 ldpcX=1'b1;
1010 stateX=ENDRET2;
1011 end
1012
1013 ENDRET2: begin
1014 stateX=ENDRET3;
1015 end
1016
1017 ENDRET3: begin
1018 ldpcX=1'b1;
1019 ldirX=1'b1;
1020 stateX=FETCH;
1021 end
1022
1023 ENDIT: begin
1024 ldpcX=1'b1;
1025 ldirX=1'b1;
1026 stateX=FETCH;
1027 end
1028
1029 endcase
1030 end
1031
1032 endmodule//TRAMBLAZE.v
1033
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Document Name:
Final Specification
VIII.17 Memory Interface Block (MIB)
2 //******************************************************************************//
3 // File name: MIB.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // MIB.v //
17 // //
18 // This module manages the memory addresses and the data coming to and //
19 // from the Micron Memory //
20 // //
21 // @input clk, rst, READ, WRITE, PORT_ID[15:0], memoryDataIn[15:0], //
22 // OUT_PORT[15:0] //
23 // //
24 // @output cCE, cWE, cOE, cIOBUT_T, cADV, CRE_HiE, cUB, cLB //
25 // memoryAddress[22:0], memoryDataOut[15:0], IN_PORT[15:0] //
26 // //
27 //******************************************************************************//
28 module MIB(clk, rst, PORT_ID, READ, WRITE, OUT_PORT, memoryDataIn, cCE, cWE,
29 cOE, cIOBUT_T, cADV, CRE_HiE, cUB, cLB,
30 memoryAddress, memoryDataOut, IN_PORT);
31
32 input clk, rst;
33 input READ, WRITE;
34 input [15:0] PORT_ID;
35 input [15:0] memoryDataIn;
36 input [15:0] OUT_PORT;
37
38 output reg[22:0] memoryAddress;
39 output reg [15:0] memoryDataOut;
40 output reg [15:0] IN_PORT;
41
42 output reg cCE, cWE, cOE, cIOBUT_T, cADV, CRE_HiE, cUB, cLB;
43
44 reg [6:0] writeAddressR0;
45 reg [15:0] writeAddressR1, WD_R;
46 reg [15:0] RD_R;
47 reg [3:0] state, nState;
48 reg [3:0] WCLK, RCLK;
49
50 wire writeDone, readDone;
51 reg nCE, nWE, nOE, nIOBUF_T, nADV, nCRE, nUB, nLB;
52
53
54 parameter
55 IDLE = 4'h0,
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Final Specification
56 MEM_WRITE = 4'h1,
57 MEM_READ = 4'h2,
58 WADDR1 = 16'h11,
59 WADDR2 = 16'h12,
60 WDATA = 16'h13,
61 RDATA = 16'h14,
62 MEMREAD = 16'h15,
63 MEMWRITE = 16'h16;
64
66 begin
67 if(rst)
68 begin
69 state <= IDLE;
70 {cCE, cWE, cOE, cIOBUT_T} <= 4'b1_1_1_1;
71 // signal always 0
72 {cADV, CRE_HiE, cUB, cLB } <= 4'b0_0_0_0;
73 end
74 else
75 begin
76 state <= nState;
77 {cCE, cWE, cOE, cIOBUT_T} <= {nCE, nWE, nOE, nIOBUF_T};
78 end
79 end
80
81 always@(*)
82 case(state)
83
84 MEM_WRITE:
85 begin
86 {nCE, nWE, nOE, nIOBUF_T} = 4'b0_0_1_0;
87 if(WCLK == 4'b1100) nState = IDLE;
88 else nState = MEM_WRITE;
89 end
90 IDLE:
91 begin
93
94 if((PORT_ID == 16'h16) && WRITE)
95 nState = MEM_WRITE;
96 else if((PORT_ID == 16'h15) && READ)
97 nState = MEM_READ;
98 else
99 nState = IDLE;
100 end
101 default:
102 begin
104
105 if(PORT_ID == 16'h14 && WRITE)
106 nState = MEM_WRITE;
107 else if(PORT_ID == 16'h15 && READ)
108 nState = MEM_READ;
109 else
110 nState = state;
111 end
112 endcase
113
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Final Specification
115 begin
116 if(rst)
117 begin
118 WCLK <= 4'b0;
119 RCLK <= 4'b0;
120 end
121 else if(state == IDLE)
122 begin
123 WCLK <= 4'b0;
124 RCLK <= 4'b0;
125 end
126
127 else if(state == MEM_WRITE) WCLK <= WCLK + 4'b1;
128 else if(state == MEM_READ ) RCLK <= RCLK + 4'b1;
129
130 else begin
131 WCLK <= WCLK;
132 RCLK <= RCLK;
133 end
134
135 end
136
138 if(rst) RD_R <= 16'h0000;
139 else if(RCLK == 4'b1011) RD_R <= memoryDataIn;
140 else RD_R <= RD_R;
141
143 if(rst)
144 begin
145 writeAddressR0 <=7'h0;
146 writeAddressR1 <= 16'h0;
147 WD_R <= 16'h0;
148 memoryAddress <=16'h0;
149 memoryDataOut <= 16'h0;
150 IN_PORT <= 16'h0;
151 end
152 else
153 case(PORT_ID)
154 WADDR1: if(WRITE) writeAddressR0 <= OUT_PORT[6:0];
155 else writeAddressR0 <= writeAddressR0;
156 WADDR2: if(WRITE) writeAddressR1 <= OUT_PORT;
157 else writeAddressR1 <= writeAddressR1;
158 WDATA: if(WRITE) WD_R <= OUT_PORT;
159 else WD_R <= WD_R;
160 RDATA: IN_PORT <= RD_R;
161 MEMREAD: if(READ)
0,
162 begin
163
164
memoryAddress <= {writeAddressR
writeAddressR1};
memoryDataOut <= WD_R;
165 end
166 else
167 begin
168 memoryAddress <= memoryAddress;
169 memoryDataOut <= memoryDataOut;
170 end
171 default:
172 begin
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Final Specification
173 writeAddressR0 <= writeAddressR0;
174 writeAddressR1 <= writeAddressR1;
175 WD_R <= WD_R;
176 memoryAddress <= memoryAddress;
177 memoryDataOut <= memoryDataOut;
178 IN_PORT <= IN_PORT;
179 end
180
181 endcase
182
183
184
185 endmodule
186
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VIII.16 Top Module
1 `timescale 1ns / 1ns
2 //******************************************************************************//
3 // File name: top_module.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // top_module.v //
17 // //
18 // This module serves as the top level module for project 5 //
19 // involving the UART engine. It connects all the pieces together. //
20 // It also uses a Memory Interface Block. //
21 // //
22 // @input clk, reset, [7:0] switches , rx //
23 // @output [7:0] anode, [7:0] cathode, [7:0] leds, tx,[22:0] memoryAddress //
24 // currentStatus [7:0], nCE, nWE, nOE, nADV, CRE, nUB, //
25 // nLB, MIBInOut [15:0] //
26 // //
27 //******************************************************************************//
28 module top_module(clk, reset,switches,tx,rx,anode,cathode,leds,
29 memoryAddress, currentStatus, nCE, nWE, nOE,
30 nADV, CRE, nUB, nLB, MIBInOut);
31
32 // Inputs
33 input wire clk, reset,rx;
34 input wire [7:0] switches;
35
36 // Outputs
37 output wire [7:0] anode, cathode;
38 output tx;
39 output reg [7:0] leds;
40
41 // MIB Outputs
42 output [22:0] memoryAddress;
43 output [7:0] currentStatus;
44 output nCE, nWE, nOE, nADV, CRE, nUB, nLB;
45 output [15:0] MIBInOut;
46
47 // Wires For Connections Between Modules
48 wire mRst;
49 wire [1:0] sel2;
50 wire [3:0] hexValue;
51 wire [15:0] counter;
52 wire [15:0] OUT_PORT;
53 wire [15:0] IN_PORT;
54 wire [15:0] PORT_ID;
55 wire READ_STROBE;
56 wire WRITE_STROBE;
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Final Specification
57 wire INTERRUPT_ACK;
58 wire INTERRUPT;
59
60 // Wires for MIB
61 wire [15:0] MIBIn, MIBOut;
62 wire curCE, curWE, curOE, curADV, curCRE, curUB, curLB;
63 wire OE;
64
65 wire ped, UARTready, load;
66
67 reg [15:0] data;
68
69
70 wire [7:0] WRITE;
71 wire [7:0] READS;
72 wire [7:0] UART_DS;
73
74 assign IN_PORT[15:8] = 8'b0;
75
76 // Synchronous Reset
77 AISO syncReset(.clk(clk),.rst(reset),.sRst(mRst));
78
79
80 // Tramelblaze Processor That Increments and Holds 16-Bit Value
81 tramelblaze_top tramelblaze_top1
82 (
83 .CLK(clk),
84 .RESET(mRst),
85 .IN_PORT(IN_PORT[15:0]),
86 .INTERRUPT(INTERRUPT),
87 .OUT_PORT(OUT_PORT[15:0]),
88 .PORT_ID(PORT_ID[15:0]),
89 .READ_STROBE(READ_STROBE),
90 .WRITE_STROBE(WRITE_STROBE),
91 .INTERRUPT_ACK(INTERRUPT_ACK)
92 );
93
94 // Memory Interface Block (MIB)
95 MIB memoryblock(.clk(clk), .rst(rst), .PORT_ID(PORT_ID),
96 .READ(READ_STROBE), .WRITE(WRITE_STROBE),
97 . OUT_PORT (OUT_PORT[15:0]), .memoryDataIn(MIBOut),
98 .cCE(nCE), .cWE(nWE), .cOE(nOE),
99 .cIOBUF_T(IOBUF_T_LoE), .cADV(nADV),
100 .CRE(CRE), .cUB(nUB),
101 .cLB(nLB), .memoryAddress(memoryAddress),
102 .MIBInput(MIBIn), .IN_PORT (IN_PORT));
103
104
105
106 // UART Engine
107 UART uart(.clk(clk),.rst(mRst), .WRITE(WRITE[7:0]), .READS(READS[7:0]),
108 .OUT_PORT(OUT_PORT[7:0]), .rx(rx),
109 .UARTready(UARTready),.tx(tx),.switches(switches[7:0]),
110 .UART_DS(IN_PORT[7:0]));
111
112
113 // SR Flop
114 SRFlop interrupt_flop(.clk(clk),.rst(mRst), .funcrst(INTERRUPT_ACK),
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Final Specification
.set(UARTready), .q(INTERRUPT));
115
116 // Seven-Segment Display Driver
117 seven_segment_display display(.clk(clk), .rst(mRst), .data(data[15:0]),
.anode(anode[7:0]), .cathode(cathode[7:0]));
118
119 // Address Decoders
120 address_decode
write_decode(.strobe(WRITE_STROBE),.enable(PORT_ID[15]),.s2(PORT_ID[2]),.s1(PORT_ID[1
]),.s0(PORT_ID[0]),.q(WRITE[7:0]));
121 address_decode
read_decode(.strobe(READ_STROBE),.enable(PORT_ID[15]),.s2(PORT_ID[2]),.s1(PORT_ID[1])
,.s0(PORT_ID[0]),.q(READS[7:0]));
122
123
124 // 8 bit register for leds
125 always@(posedge clk, posedge mRst)
126 if (mRst)
127 leds <= 8'b0;
128 else if(WRITE[1])
129 leds <= OUT_PORT[7:0];
130 else
131 leds <= leds;
132
133 // 16 bit register for sev seg display
134 always@(posedge clk, posedge mRst)
135 if (mRst)
136 data <= 16'b0;
137 else if(WRITE[2])
138 data <= OUT_PORT[15:0];
139 else
140 data <= data;
141
142 endmodule
143
144
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