Connection Machine
- 1. Connection MachineArchitectureGreg Faust, Mike Gibson, Sal ValenteCS-6354 Computer ArchitectureFall 20091
- 2. Historic Timeline1981: MIT AI-Lab Technical Memo on CM1982: Thinking Machines Inc. Founded 1985: Danny Hillis wins ACM “Best PhD” Award1986: CM-1 Ships1987: CM-2 Ships1991: CM-5 Announced1991: CM-5 Ships1994: TMI Chapter 11 – Sun/Oracle pick bonesHeavily DARPA funded/backed$16M+ Direct Contracts plus subsidized CM sales2
- 3. Involved NotablesDanny Hillis – CM inventor and TMI FounderCharles Leiserson – Fat tree inventorRichard Feynman – Noble Prize winning PhysicistMarvin Minsky – MIT AI Lab “Visionary”Guy Steele – Common Lisp, Grace Hopper AwardStephen Wolfram – Mathematica inventorDoug Lenat – Mind/Body problem philosopherGreg Papadopoulos – MIT Media lab, Sun CTOvarious others3
- 4. CM-1 and CM-2 ArchitectureOriginal design goal to support neuron like simulationsUp to 64K single bit processors (actually 3 bits in and 2 out)16 Processors/chip, 32chips/PCB, 16 PCBs/cube, 8cubes/hypercubeHypercube architecture – Each 16-Proc chip a hyper-nodeEach proc has 4K bits of bit addressable RAMDistributed Physical Memory Global Memory AddressesUp to 4 front-end computers talk to sequencers via 4x4 crossbar“Sequencers” issue SIMD instructions over a Broadcast NetworkBit procs communicate via 2D local HW grid connections (“NEWS”)Bit procs communicate via hypercube network using MSG passingLots of Twinkling Lights!!4
- 6. CM-1 and CM-2 ProgrammingISA supports:Bit-oriented operationsArbitrary precision multi-bit scalar Ops using bit-serial implementation on bit procsFull Multi-Dimensional Vector Ops“Virtual Processor” idea similar to CUDA threadsbut they are statically allocatedOS and Programming Tools run on front-ends*Lisp as the initial programming languageLater C* and CM-Fortran6
- 7. CM-2 Improvements1 Weitek IEEE FP coprocessor per 32 1-bit procsUp to 256K bits of memory per processorAdded ECC to MemoryImplemented the IO subsystemUp to 80 GByte RAID array called “Data Vault”uses 39 Striped Disks and ECC, plus spare disks on standbyHigh Speed Graphics OutputEn-route MSG combining in H-Cube routerNew implementation of Multi-DimensionalNEWS on top of H-Cube (special addressing mode)7
- 8. CM-1 Photo8
- 9. CM-5 vs CM-1 and CM-2Significant departure from CM-1 and CM-2Targeted at more scientific and business applications More Commercial Off-The-Shelf components (“COTS”)Large Array of SPARC Processing Nodes1-bit processors are abandonedAbandoned “NEWS” Grid and Hyper-Cube NetworksDelivered 1024 node machine, with claims 16K nodes possibleEven More Twinkling Lights!9
- 10. CM-5 Photo – Watch it Blink10
- 11. CM-5 Overall Architecture"Coordinated Homogeneous Array of RISC Processors“ or “CHARM”Asymmetric CoProcessors ModelLarge Array of Processor NodesSmall Collection of Control Nodes2 Separate scalable networksOne for dataOne for control and synchronizationStill uses striped RAID for high disk BandWidth11
- 12. Division of LaborProcessor Nodes can be assigned to a “Partition”One Control Node per PartitionControl Node runs scalar code, then broadcasts parallel work to Processor NodesProcessor Nodes receive a program, not an instruction stream, have own Program CounterProcessor nodes can access other node's memory by reading or writing a global memory addressProcessor Nodes also communicate via MSG passingProcessor Nodes cannot issue system calls12
- 13. Control NodesFull Sun WorkstationsRunning UNIXConnected to the “Outside World”Handles Partition Time SharingConnected to both data and control networksPerforms System Diagnostics13
- 14. Processor NodesNodes are a 5-chip microprocessorOff the Shelf SPARC processor @ 40 MHz32MBytes local node memoryMulti-port memory controller for added BW“Caching techniques do not perform as well on large parallel machines”Proprietary 4-FPU Vector coprocessorProprietary network controller14
- 15. CM-5 Processor Node Diagram15
- 16. Data Network ArchitecturePoint to Point Inter-node communication and I/OImplemented as a Fat TreeFat Trees invented by TMI employee Charles LeisersonClaim: Onsite BandWidth ExpandableDelivering 5GB/sec Bisection BW on 1024 node machineData router chip is a 8x8 crossbar switchFaulty nodes are mapped out of networkPrograms can not assume a network topologyNetwork can be flushed when Time Share swaps occurNetwork, not processors, guarantee end to end delivery16
- 18. Separate Control NetworkSynchronization & control networkComplete Binary Tree organizationProvides broadcast capabilityImplements barrier operationsImplements interrupts for timesharingPerforms reduction operators (Sum, Max, AND, OR, Count, etc)18
- 19. CM-5 ProgrammingSupports multiple Parallel High Level Languages and Programming StylesIncluding Data Parallel Model from CM-1 and CM-2Goal: Hide many decisions from programmersCM-1, CM-2 vs CM-5 ISA changesUse of Processor Node CPU vs Vector CoProcessorsPartition Wide Synchronizations generate by CompilerIs it MIMD, SPMD, SIMD? “Globally Synchronized MIMD”19
- 20. Sample CM AppsMachine LearningNeural Nets, concept clustering, genetic algorithmsVLSI DesignGeophysics (Oil Exploration), Plate TectonicsParticle SimulationFluid Flow SimulationComputer VisionComputer Graphics , AnimationProtein Sequence MatchingGlobal Climate Model Simulation20
- 21. ReferencesDanny Hillis PhD: The Connection MachineInc: The Rise and Fall of Thinking MachinesWiki: Connection MachineACM: The CM-5 Connection MachineACM: The Network Architecture of the CM-5IEEE: Architecture and Applications of the Connection MachineIEEE: Fat-trees: universal networks for hardware-efficient supercomputingEncyclopedia of Computer Science and Technology21