Csc4320 chapter 8 2

8.4 paging
 Paging is a memory-management scheme
that permits the physical address space of a
process to be non-contiguous.
 The basic method for implementation involves
breaking physical memory into fixed-sized
blocks called FRAMES and break logical
memory into blocks of the same size called
PAGES

Paging
 Every address generated by the CPU is
divided into two parts: Page number
(p) and Page offset (d)
 The page number is used as an index
into a Page Table

Paging
 The page size is defined by the hardware
 The size of a page is typically a power of 2,
varying between 512 bytes and 16MB per
page
 Reason: If the size of logical address is 2^m
and page size is 2^n, then the high-order
m-n bits of a logical address designate the
page number

Paging
 When we use a paging scheme, we have no
external fragmentation: ANY free frame can
be allocated to a process that needs it.
 However, we may have internal fragmentation
 For example: if a page size is 2048 bytes, a
process of 72766 bytes would need 35 pages
plus 1086 bytes

Paging
 If the process requires n pages, at least
n frames are required
 The first page of the process is loaded
into the first frame listed on free-frame
list, and the frame number is put into
page table

Hardware Support on Paging
 To implement paging, the simplest
method is to implement the page table
as a set of registers
 However, the size of register is limited
and the size of page table is usually
large
 Therefore, the page table is kept in
main memory

Hardware Support on Paging
 If we want to access location I, we must first
index into page table, this requires one
memory access
 With this scheme, TWO memory access are
needed to access a byte
 The standard solution is to use a special,
small, fast cache, called Translation look-aside
buffer (TLB) or associative
memory

TLB
 If the page number is not in the TLB (TLB
miss) a memory reference to the page table
must be made.
 In addition, we add the page number and
frame number into TLB
 If the TLB already full, the OS have to must
select one for replacement
 Some TLBs allow entries to be wire down,
meaning that they cannot be removed from
the TLB, for example kernel codes

TLB
 The percentage of times that a particular page
number is found in the TLN is called hit ratio
 If it takes 20 nanosecond to search the TLB and 100
nanosecond to access memory
 If our hit ratio is 80%, the effective memory access
time equal:
0.8*(100+20) + 0.2 *(100+100)=140
 If our hit ratio is 98%, the effective memory access
time equal:
0.98*(100+20) + 0.02 *(100+100)=122
(detail in CH9)

Memory Protection
 Memory protection implemented by associating
protection bit with each frame
 Valid-invalid bit attached to each entry in the page
table:
 “valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal
page
 “invalid” indicates that the page is not in the process
’logical address space

Memory Protection
 Suppose a system with a 14bit address
space (0 to 16383), we have a program
that should use only address 0 to
10468. Given a page size of 2KB, we
may have the following figure:

Memory Protection
 Any attempt to generate an address in
page 6 or 7 will be invalid
 Notice that this scheme allows the
program to access 10468 to 12287, this
problem is result of the 2KB page size
and reflects the internal fragmentation
of paging

Shared Pages
 An advantage of paging is the possible of
sharing common code, especially time-sharing
environment
 For example a server with 40 user using text
editor (with 150k reentrant code and 50k data
space)
 In next figure, we see three page editor with
50k each. Each process has its own data
page

Shared Pages
 In this case, we need only
150k + 40* 50k = 2150 KB
Instead of
(150k + 50K)*40 = 8000KB

8.5 Structure of Page Table
 Consider a system with 32-bit logical
address space.
 If the page size is 4 KB (2^12), then the
page table may consist of up to 1 million
entries (2^32/2^12=2^20)
 Clearly, we would not want to allocate
the page table contiguously in main
memory

Hierarchical paging
 One way is to
use a two-level
paging algorithm

Hierarchical paging
 Remember the example is a 32-bit
machine with a page size of 4 KB.
 A logical address is divided into a page
number consisting of 20 bits and a page
offset consisting of 12 bits
10 10 12

Hierarchical paging
 Address translation scheme:

Hierarchical paging
 For a system with 64-bit system, by the
same scheme with page size=4KB will
looks like:

Hierarchical paging
 One way to avoid such large table is to
further divide the outer table into
smaller pieces:

Hierarchical Paging
 The next step would be a four-level
paging scheme…
 However, for 64-bit architecture,
hierarchical page table are generally
considered inappropriate

Hash Page Table
 Hash Page table is commonly used in
systems with address spaces larger
than 32 bit
 So what is a hash table?

Hash Page Table
 Each element consists of three fields:
1. The virtual page number
2. The value of the mapped page frame
3. A pointer to the next element

8.6 Segmentation
 Since the user’s view of memory is not the
same as the actual physical memory,
segmentation helps user to view memory as a
collection of variable-size segment
 Segmentation is a memory management
scheme that supports user view of memory

Segmentation
A program is a collection of segments. A segment is a logical unit
such as:
 main program,
 procedure,
 function,
 method,
 object,
 local variables, global variables,
 common block,
 stack,
 symbol table, arrays

Segmentation
 The user specifies each address by two
quantities: a segment name and an offset
<segment-number, offset>
 Compare with page scheme, user specifies
only a single address, which is partitioned by
hardware into a page number and an offset,
all invisible to the programmer

Segmentation
 Although the user can refer to objects in the
program by a two-dimensional address, the
actual physical address is still a one-dimensional
sequence
 Thus, we need to map the segment number
 This mapping is effected by a segment
table
 In order to protect the memory space, each
entry in segment table has a segment base
and a segment limit

Example of Segmentation
 For example, segment 2
starts from 4300 with size
400, if we reference to byte
53 of segment 2, it mapped
to 4335
 A reference to segment 3,
byte 852?
 A reference to segment 0,
byte 1222?

8.7 Example: Intel Pentium
 In Pentium system, the CPU generates
logical address, which are given to the
segmentation unit
 The segmentation unit produces a linear
address for each logical address
 Then the linear address is then given to
paging unit, which in turn generates the
physical address in main memory.

Pentium paging
 The Pentium architecture allows a page
size of either 4KB or 4MB.
 For 4KB pages, the Pentium uses a two
level paging scheme in which division of
the 32 bit linear address as:

Linux on Pentium System
 Although the Pentium uses a two-level paging
model, Linux is designed to run on a variety
of hardware platform, many of which are 64-
bit platforms
 Therefore, two-level paging is not plausible
 Thus, Linux has adopted a three level paging
strategy that works well for both 32-bit and
64-bit architectures

Linux on Pentium System
 The linear address is Linux is broken into the
following four parts:
 The number of bits in each part varies
according to architecture
 How does Linux apply its three-level model
on the Pentium? The size of middle directory
is zero bits

Csc4320 chapter 8 2

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Csc4320 chapter 8 2