deep_dive_on_sic-based_10kw_grid_tie_inverter_design_challenges.pdf

Deep dive on SiC-based 10kW grid tie
inverter design challenges
Bart Basile
SEM – Grid Infrastructure – Renewable Energy
Asia FAE Summit - 2018

Why SiC?
[Source: “A survey of wide bandgap power semiconductor devices,” in IEEE Transactions on
Power Electronics, 2014, vol. 5]
[Source: PSMA Yole Power Market Roadmap 2014]
Intrinsic Material Properties Properties leading to System Benefits

SiC: system benefit examples
SiC Solution:
▪ 60% Smaller
▪ 20% Lower Cost
[Link]
SiC Solution:
▪ 5X Smaller
[Link] [Link]

SiC: application landscape
[Sources: PSMA Yole Reports, PCIM’2016]
1MW+
100kW
0.1kW
Application
Power
Device Voltage
600V 6.6kV+
1.7kV
1.2kV
900V 3.3kV
Ships & Vessels
2.5kV-3.3kV
200kW-20MW
Wind Turbines
3.3kV
1MW+
Grid T&D
4.5kV-6.6kV+
10MW-1GW+
PV: Buildings/Farms
(Inverter)
600V-1.7kV
100kW-1MW
Rail Traction
(Inverter)
750V-1.5kV
300kW-1MW
UPS: High-Power
(Inverter)
600V-1.2kV
50kW-1MW
Motor Drives
Medium-Power Inverter
900V-1.7kV
5kW-50kW
PV: Residential
(Inverter)
600V-1.2kV
5kW-50kW
UPS: Low-Power
(Inverter)
600V-1.2kV
500W-5kW
EV/HEV
(Inverter/Converter)
600V-1.2kV
3kW-350kW
Light Rail
(Inverter)
750V-1.5kV
5kW-80kW
PFC/Power Supplies:
High-Power
600V
10kW-100kW
10kW
1kW
Motor Drives
High-Power Inverter
1.2kV-3.3kV
50kW-200kW

SiC: MOSFET adoption has started …
Rail Traction PV: Multi-MW Inverters
EV/HEV Powertrain Inverter & DC-DC EV/HEV On-board & Off-board Chargers
Shinkansen Bullet Train
[Link]
[Link]
[Link]
All-SiC Rail Traction Inverter
[Link] [Link] [Link]
SiC Solution:
 5X Smaller
than IGBT
SiC Solution:
 2X Smaller
than IGBT
EV On-Board Charger EV/HEV
Off-Board Charger
[Link]

SiC: future challenges for mass adoption
System Cost, Size,
Weight Reduction
Fast Switch
Protection
EMI Reduction
System
Robustness
over Lifetime
 EV/HEV need 4X-10X smaller size & 40%-80% weight reduction
 SiC systems need to operate at 4X-10X higher switching frequencies compared to IGBTs
 Challenge: How to reduce switching losses at considerably higher frequencies?
 SiC MOSFETs have significantly reduced SC capability (<3µs) compared to IGBTs (10µs)
 Challenge: How to protect SiC MOSFETs in <2µs in a SC/OC event?
 Higher switching frequencies & slew rates (dV/dt) would create higher Ringing & EMI
 Challenge: How to reduce Ringing & EMI without increasing system cost/size/weight?
 Higher slew rates (dV/dt) would need higher component derating: Higher system cost
 Challenge: How to handle higher dV/dt while reducing system cost?
 Higher slew rates (dV/dt) would reduce MOSFET lifetime due to higher voltage excursions
 Challenge: How to reduce Ringing to guarantee increased lifetime of MOSFETs?
 SiC systems need to transition at higher slew rates (dV/dt) as compared to IGBTs
 Challenge: Need higher isolation & CMTI rated components at lower system cost

Traditional H-bridge inverter
Q1
Q2
DC+
DC-
R
Y
B
N
N

The T-type inverter
Q1
Q2
Q3
Q4
DC+
DC-
R
Y
B
N
N

Carried From H-Bridge
• Maintains Low Conduction Losses
• Small Part Count
• Simple Switching Operation
Upgrades to H-Bridge
• Lower Switching Losses
• Lower Output Harmonics
• Reduced Filter Size
T-type advantages

Efficiency comparison for grid tie inverter
Q1
Q2
DC+
DC-
R
Y
B
N
N
Q1
Q2
Q3
Q4
DC+
DC-
R
Y
B
N
N
2-Level Full Bridge
(6 x SiC Mosfet - SIC1MO120E0080)
3-Level (T-type) Full Bridge
(6 x IGBT – FGH60N60SMD)
3-Level (T-type) Full Bridge
(6 x Mosfet – IPW65R045C7)
SiC Mosfet Loss 9.4 SiC Mosfet Loss 5.2 SiC Mosfet Loss 5.2
IGBT Loss 7.887 Si Mosfet Loss 2.78
3 X Inductors – 833uH 3 X Inductors – 555uH 3 X Inductors – 555uH
Inductor Loss 8.9 Inductor Loss 6.4 Inductor Loss 6.4
Efficiency Efficiency Efficiency
Total Loss 83.1 Total Loss 100.242 Total Loss 69.6
Efficiency 99.16% Efficiency 98.99% Efficiency 99.3%
Specifications
AC Output:
3Ph 400V, 50Hz, UPF
10KW output power
DC Input:
800V
Inverter:
50KHz switching frequency
20% current ripple
2-Level Full Bridge 3-Level T-type Inverter

Loss details 2-level SiC
2-Level SiC, 10kW
SW Speed (kHz) 20 50 100
IND Val 2083uH 833uH 416uH
SiC Conduction 6.9 5.9 4.49
SiC SW 1.54 3.5 6.14
Ind 7.5 8.9 12.1
System Total 73.14 83.1 100.08
0
2
4
6
8
10
12
14
0 50 100
Loss
(w)
SW (kHz)
2-Level SiC, 10kW
SiC Conduction
SiC SW
Ind

Loss details 3-level SiC+MOSFET
3-Level SiC+SIFET, 10kW
SiC SW 0.637 1.53 2.6
FET Conduction 2.05 2.17 2.5
FET SW 0.59 0.61 1.56
Ind 5.8 6.4 7.77
System Total 66.462 69.6 80.67
0
1
2
3
4
5
6
7
8
9
0 50 100
Loss
(w)
SW (kHz)
3-Level SiC+MOSFET, 10kW
SiC Conduction
SiC SW
FET Conduction
FET SW
Ind

Loss details 3-level Sic+IGBT
3-Level SiC+IGBT, 10kW
SiC SW 0.637 1.53 2.6
IGBT Conduction 4.77 5.107 5.1
IGBT SW 1.11 2.78 5.58
Ind 5.8 6.4 7.77
System Total 85.902 100.242 120.39
0
1
2
3
4
5
6
7
8
9
0 50 100
Loss
(w)
SW (kHz)
3-Level SiC+IGBT, 10kW
SiC Conduction
SiC SW
IGBT Conduction
IGBT SW
Ind

IGBT over SiMOSFET
• Si MOSFET have a resistive feature which helps to reduce conduction loss at light
load conditions compared with IGBT, but the high reverse recovery of the body diode
will increase voltage and current overshoot. Since SiC MOSFET switches much
faster than i devices, the reverse recovery is much more severe.
• Si IGBT have higher conduction loss at light load, but the reverse recovery can be
lower if a fast recovery diode is used as the antiparallel diode. Moreover, since IGBT
is a unidirectional device, the current will always conduct through one anti-parallel
diode in T-Type topology, the light load efficiency will be reduced.

T-Type conduction
ON
OFF
A B
C
A B
C
Deadtime Deadtime

What is a Gate Driver
H
L
Voltage
Level
LI
LO
GND
~ VDD-GND
Low side driver
Voltage
Level
GND
HS
LI
LO
HI
HO
~ VDD-GND
~ HB-HS
(same as Low-side
Driver)
High side-Low side (Half-bridge) driver
Gate Driver is a power amplifier that turns a low-power
signal from a controller IC into the high-current gate drive
for a power MOSFET.
Input Signal: from controller, can be logic level Output signal: changes state based on input signal
• OUT High (ON state) ~ VDD (Souring current)
• OUT Low (OFF state) ~ GND (Sinking current)
Controller output
Fast charge/discharge of CGS, CGD reduces power loss in time intervals
Therefore reduce Power Dissipation during switching
Definition Benefits
Types
2 3
Power Loss (VDS*ID)
During 2,3
Power Loss (VDS*ID)
During 2,3
MOSFET Turn-On MOSFET Turn-Off
G
S
D
Gate Drive VGS > VTH, ON.
Gate Drive VGS < VTH, OFF.
Definition Benefits
Types

The MOST critical requirements for a SiC driver
• Isolation (Reinforced / Basic)
• High dVDS/dt Immunity (CMTI)
• Fast Over-current / Short-circuit Protection
• Low Propagation Delay & Variation
• High Output Drive Voltage > 25V

SiC driver: new key requirements
Requirement Reason
High output drive voltage: 25V-35V Higher Efficiency: Lower conduction loss
 Tight voltage control Gate-oxide protection
 Margin to accommodate noise Gate-oxide protection
 Negative supply voltage Miller turn-ON immunity (Low Vth)
25
High drive strength Higher Efficiency: Lower switching loss
Lower
Drive
Strength
Higher
Drive
Strength
Impact of drive strength on switching loss (Turn ON)
~100V/ns
High dVDS/dt immunity (CMTI) Robustness for higher efficiency
[NOTE: CMTI = Common-Mode Transient Immunity]
TI’s Industry-best Capacitive Isolation Technology
[Link to ti.com/isolation]
 Industry-leading Integrated Capacitive Isolation
 SiO2 is the most stable dielectric over temperature
& moisture
 Leverage advantages of TI’s customized CMOS
process:
 High precision
 Tight part-to-part skew
 No wear out mechanisms
 Low defect levels
 Highest lifetime in the industry: >1.5 kVRMS for
40 years
 Superior transient protection for harsh
environments: >12.8kV peak

Requirement Reason
13
Fast short-circuit protection Lower short-circuit capability
SiC: Need for Fast Short-Circuit Protection
[NOTE: Drawings not to scale.]
SiC
IGBT
 For same ON resistance, IGBT
die is larger than SiC MOSFET
die
 SiC MOSFET die has lower
thermal dissipation capability
than IGBT
 For same rated current & voltage, IGBT reaches active region for significantly
lower VCE (high β) as compared to SiC MOSFET
 IGBT self-limits the current increase
 In the case of SiC, ID continues to increase with increase in VDS, eventually
resulting in faster breakdown
IGBT SiC MOSFET

Requirement Reason
13
Fast short-circuit protection Lower short-circuit capability
Small propagation delay & variation Higher Efficiency + Faster System Control
Switch Temperature Sensing Advanced switch protection

Short-circuit protection: hardware validation
Goals Evaluation Hardware
S1
S2
D1
D2
VBUS
ISO5852S
Based
Driver
Module
ISO5852S
Based
Driver
Module
Rshunt
L
Isolated Power Supplies
DC Bus Caps
IGBT/SiC Half-bridge Module
Isolated Half-bridge Drive Stage
using ISO5852S-Q1 + 15A Buffer Driver
IGBT/SiC
Half-bridge Module
High-side
Isolated Driver
(Upto ±15A)
Low-side
Isolated Driver
(Upto ±15A)
Schematic for Double-Pulse Test Setup
 Evaluate short-circuit protection
capability through measurements using
IGBT/SiC half-bridge module
 Test feasibility of reliable short-circuit
protection based on ISO5852S driver
architecture
 Test reliable operation of isolated driver
in high drive current (up to ±15A)
condition
 Confirm reliable short-circuit protection
of IGBT/SiC modules
TOP
BOTTOM

Short-circuit protection: SiC: delayed load short
Without Soft Turn-OFF With Soft Turn-OFF
VGate: 10V/div
ID (1000A/div) [Inverted]
VDS: 100V/div
DESAT Pin (5V/div)
VGate: 10V/div
ID (1000A/div)
VDS: 100V/div
VDS Overshoot limited to <50V !!
VDS Overshoot +400V
+ Ringing !!
ID Over-Current +1000A !!
ID Over-Current +2000A !!
 Reliable short-circuit protection in <1µs
 VDS overshoot significantly improved with Soft Turn-OFF
 ISO5852S: Reliable Soft Turn-OFF for safe shutdown

Short-circuit protection: SiC: turn ON into short
Without Soft Turn-OFF With Soft Turn-OFF
VGate: 10V/div
ID (1000A/div)
VDS: 100V/div
DESAT Pin (5V/div)
VGate: 10V/div
ID (1000A/div)
VDS: 100V/div
VDS Overshoot limited to <50V !!
VDS Overshoot +400V
+ Ringing !!
ID Over-Current +1000A !! ID Over-Current +2000A !!
 Reliable short-circuit protection in <1µs
 VDS overshoot significantly improved with Soft Turn-OFF
 ISO5852S: Reliable Soft Turn-OFF for safe shutdown

Reference Design for Reinforced Isolation 3-Phase Inverter with
Current, Voltage and Temp Protection / TI Design : TIDA-00366
Tools & Resources
• TIDA-00366 and Tools Folder
• Design Guide
• Design Files: Schematics, BOM,
Gerbers, and more
• Device Datasheets:
‒ UCC21520 - AMC1301
‒ OPA320 - TLV1117-33
‒ TLC372 - TLV70433
‒ REF2033 - TL431B
Board Image
Target Applications
• Variable Speed AC Drives
• Three-Phase UPS
• Industrial Power Supplies
Features
• Reinforced isolated Inverter suited for 200 – 690V AC drives rated up to 10kW
• Simple yet effective gate driver with 4A source, 6A sink output current
capability
• 250kHz isolated amplifier for Inverter current, DC link voltage and IGBT
module temperature measurement
• Uncalibrated current measurement accuracy of ±0.5% across temperature
range from -25˚C to 85˚C
• Protection against DC bus Under-Voltage, Over-Voltage, Over-Current,
Ground Fault and Over-Temperature
Benefits
• Using AMC1301 enables use of internal ADC of MCU
• Bootstrap based power supply for high side gate driver reduces
overall cost for power supply requirements
• 19ns typical Propagation Delay optimizes dead band distortion
Back to
Outline
TI Confidential – NDA Restrictions FOR TI INTERNAL USE ONLY

ISO5852S
+2.5A/-5A, Isolated, High CMTI, Miller Clamp
Features Benefits
• Integrated SiO2 Dielectric Capacitor
• CMOS compatible logic input threshold
• Safety Features: Miller Clamp, Desat Detect, UVLO, Fault
feedback, Ready status feedback, auto soft-shutdown on short
• +2.5/-5A Peak Source/Sink Split Outputs
• 120 kV/μs CMTI (typ) / 100 kV/μs (min)
• 30ns Integrated Glitch Filter
• 110 ns (max) Prop Delay
• 4kV ESD on all pins
• Immunity and Certifications
• 12.8 kVpk Surge (8 kV VIOSM ) per VDE Reinforced Isolation
• 5.7 kVrms Isolation rating per UL1577
• 8000 Vpk VIOTM (transient) and 2121 Vpk VIORM (working
voltage) per VDE0884-10
• Enables IEC61800-5-1, IEC60664-1 & IEC62109-1
• Power and Package
• Wide VCC2 Range: 15V-30V
• 16-pin Wide SOIC Package (>8mm Creepage)
• Extended Temp: -40 to 125 oC
• Component-level Reinforced rating
• Improved system performance
• Enabling low power & efficient solutions
• High Immunity for Noisy Environments
• High Reliability in Harsh Environments
• Certified by all 3 World Wide agencies
PART # Split
outputs
Soft
Turnoff
UVLO+/
UVLO- (typ)
PKG
ISO5852S Yes Yes 11.6/10.3 16DW
: AEC-Q100

UCC5320ECD, UCC5320SCD, UCC5320SCDWV
2A/2A Single-Channel Isolated Gate Driver with Split Output (S) or for Bipolar Supply (E)
Features Benefits
• Integrated SiO2 Dielectric Capacitor
• 2A/2A Peak Source/Sink Drive
• >100 kV/us CMTI
• 100 ns Propagation Delay (max)
• Negative voltage handling on input pins (-5V)
• 4kV ESD on all pins
• Immunity and Certifications
• Basic and Reinforced Isolation
• Safety-related certifications:
• 7000-VPK Isolation (DWV) and 4242-VPK Isolation (D)
per DIN V VDE V 0884-11:2017- 01 (Planned)
• 5000-VRMS (DWV) and 3000-VRMS (D) Isolation Rating
for 1 minute per UL 1577
• CQC Certification per GB4943.1-2011 (Planned)
• Power and Package
• Wide VCC2 Range: 13.2 to 33V
• 8-pin Narrow Body SOIC (4 mm Creepage) or 8-pin Wide-
Body SOIC (8mm Creepage)
• 3V to 15V input supply range
• Family (UCC53x0) with different configuration options available
• UCC53x0SCD allows control of rise and fall time of driver.
UCC53x0ECD has UVLO2 referenced to GND2 which facilitates
bipolar supplies
• Enabling low power & efficient solutions
• Improved system performance

System grounding and isolation

Compliance standard for leakage currents
According to the German standard VDE 0126-1-1, there are
three different currents that have to be monitored:
• Ground Fault current, which happens in case of
insulation failure when the current flows through the
ground wire;
• Fault current, which represents the sum of the
instantaneous values of the main currents, that in
normal conditions leads to zero;
• Leakage Ground currents, which is the result of
potential variations of capacitive coupled parasitic
elements
The standard states that
disconnection from the grid is necessary within 0.3s in
case the leakage current is higher than 300mA

Option 1: System ground - Earth Option 2: System ground – DC-
System isolation

Optical Magnetic
Isolation technologies
Capacitive

Optical Isolation: Major Drawbacks:
• Low performance
– Long propagation times
– Higher quiescent current
• Low robustness and reliability
– Low noise immunity: Low common mode transient immunity
– LED Degradation associated with temperature and age
Optical & magnetic isolation: major drawbacks
Magnetic Isolation: Major Drawbacks
• Low robustness
– Lower working voltage  Translates to limited applications
– Low noise immunity: Low common mode transient immunity
– High EM emissions – noise issues
• Lower reliability
– Higher quiescent current
– Insulator degradation over time
 Capacitive isolation technology does not suffer from the above drawbacks

TI’s capacitive signal isolation technology
 Industry-leading Integrated Capacitive Isolation
 SiO2 is the most stable dielectric over temperature
& moisture
 Leverage advantages of TI’s customized CMOS
process:
 High precision
 Tight part-to-part skew
 No wear out mechanisms
 Low defect levels
 Highest lifetime in the industry: >1.5 kVRMS for 40 years
 Superior transient protection for harsh
environments: >12.8kV
UCC21520 CMTI Results

Specifications
AC Output
Power (KW/KVA) 10/10
PF rated/adjustable 1/0.7lag to 0.7lead
Grid Voltage (L-L) 400V ± 20%
No of Phases 3
Frequency 50/60Hz ± 5Hz
Current (Max)(A) 18
DC Input
Nominal Voltage (V) 800
Rated Min/Max Voltage (V) 600/1000
Performance
Efficiency (peak/European) 98.5%
Output current THD <2%
Other Specs
Off Grid operation No
Operating temperature -25˚C to +60˚C
Thermal management Forced air cooling
Target End Equipment's
String Inverters – Residential/Commercial

Topology & system architecture

System power topology
Main System Power Tree Gate Bias Power Tree

10 100 1 10
3
 1 10
4
 1 10
5
 1 10
6
 1 10
7

160
-
140
-
120
-
100
-
80
-
60
-
40
-
20
-
0
20
40
180
-
170
-
160
-
150
-
140
-
130
-
120
-
110
-
100
-
90
-
80
-
27.11
154.772
-
Gain F.lcl.rd s f
( ) L.x 0.5
( )
, L.g.x 0.5
( )
, C.f.x
, R.d.x 0.5
( )
,
( )
( )
Gain F.lcl.rd s f
( ) L.x 1
( )
, L.g.x 1
( )
, C.f.x
, R.d.x 1
( )
,
( )
( )
Gain F.lcl.rd s f
( ) L.x 2
( )
, L.g.x 2
( )
, C.f.x
, R.d.x 2
( )
,
( )
( )
Gain F.lt s f
( ) L.x 1
( )
, L.g.x 1
( )
,
( )
( )
80
-
179.713
-
Phase F.lcl.rd s f
( )
(
(
Phase F.lcl.rd s f
( )
(
(
Phase F.lcl.rd s f
( )
(
(
Phase F.lt s f
( ) L.x
,
(
(
1 10
7

10 f
Linv Lgrid
cf
Rd
Vinv VGrid
igrid
iinv
𝐿𝑖𝑛𝑣 =
𝑉𝑑𝑐
8 × 𝐹𝑠𝑤 × 𝐼𝑔𝑟𝑖𝑑𝑟𝑎𝑡𝑒𝑑 × %𝑟𝑖𝑝𝑝𝑙𝑒
𝐶𝑓 =
%𝑥 × 𝑄𝑟𝑎𝑡𝑒𝑑
2 × 𝜋 × 𝐹𝑔𝑟𝑖𝑑 × 𝑉𝑔𝑟𝑖𝑑
2
𝐿𝑔𝑟𝑖𝑑 = 𝑟 × 𝐿𝑖𝑛𝑣
𝑖𝑔𝑟𝑖𝑑
𝑖𝑖𝑛𝑣
=
1
𝑟 × 1 − 𝐿𝑖𝑛𝑣 × 𝐶𝑓 × 𝜔𝑠𝑤
2 + 1
LCL Filter
%ripple
10 20 40
Linv(µH) 1386 692 346
Cf(µF) 9.95 9.95 9.95
Lgrid(µH) 9.17 9.18 9.19
Filter Gain @ Fsw (dB) -65.7 -59.8 -53.9
Rd 0.319 0.318 0.316
Power loss in Rd(W) 0.22 0.387 1.043
THD(%) 0.36 0.722 1.443
10%
20%
40%
𝑅𝑑 =
1
2 × 𝜋 × 𝐹𝑟𝑒𝑠 × 𝐶𝑓 × 3
Choose Igrid to Iinv attenuation and calculate ‘r’, chosen 10% for
above calculations
L -20%
Output filter design

50kHz inductor design
Grid
• 340uH
• 61mm(d) x 38mm(h)
𝐿𝑖𝑛𝑣 =
𝑉𝐷𝐶
8 × 𝑓𝑠𝑤 × 𝐼𝑔𝑟𝑖𝑑 × %𝑟𝑖𝑝𝑝𝑙𝑒
𝐿𝑖𝑛𝑣 = 346𝑢𝐻
𝑅𝐴𝐶 = 0.087Ω
𝑅𝐷𝐶 = 0.024Ω
𝑃𝑖𝑛𝑑_𝑙𝑜𝑠𝑠 = 5.64𝑊
Rated RMS Current 15A
Peak Current 24A
Core Kool Mu 26
Windings 84 turns 12AWG Flat

SiC MOSFET loss estimation
Specs used for loss estimation
Grid
Switch
conduction loss 4.095
Switching Loss 1.536
Diode
Conduction loss 0
reverse recovery loss 3.21E-03
Total Loss/Switch (W) 5.63W
More details required
• Eon, Eoff vs Ids at high temperature
• Qrr of diode vs Isd

Total system losses
IGBT Loss SIC Loss Inductor Loss Total / Phase System Total
7.56W 5.63W 5.64W 32.02W 96.06W

Digital power control requirements
1. A high speed ADC which
can be synchronized with the
switching patterns
2. A high performance CPU for
low latency computation of the
control law
3. A flexible PWM pattern
generator
4. A high speed
comparator sub-system to trip
PWM outputs on current events
Trip
logic
CPU
ADC PWM
H1 DAC
Vfb
Ifb
PWMA
PWMB

Delfino™ TMS320F2837xD
TMS320F2837xD
Actuation
12x ePWM Modules (Type 4)
24x Outputs (16x High-Res)
Fault Trip Zones
3x 12-bit DAC
Connectivity
4x UART
2x I2C (w/ true PMBus)
3x SPI
2x McBSP
2x CAN 2.0
USB 2.0 OTG FS MAC & PHY
uPP
Sensing
ADC1: 16-bit, 1.1-MSPS
12-bit, 3.5 MSPS
12-bit, 3.5 MSPS
12-bit, 3.5 MSPS
12-bit, 3.5 MSPS
8x Windowed Comparators w/ Integrated
12-bit DAC
8x Sigma Delta Interface
Temperature Sensor
3x eQEP
6x eCAP
Power & Clocking
2x 10 MHz OSC
Ext OSC Input
System Modules
3x 32-bit CPU Timers
NMI Watchdog Timer
2x 192 Interrupt PIE Debug
Real-time JTAG
Temperatures 105C 125C Q100
Processing
C28x™ DSP
core
200 MHz
FPU
TMU
VCU-II
Tools
• 800MIPS real-time performance of dual C28x core with dual
CLA co-processors to run parallel control loops
• 4 differential 16-bit ADC, 1MSPS each and 3x 12-bit DAC
• Trigonometric Math Unit (TMU) - 1 to 3 cycle SIN, COS,
ARCTAN instructions
• Direct memory access through dual EMIFs (16bit/32bit)
• Protection with 8x Windowed Comparators and X-Bar
• 8 Sigma Delta Decimation Filters to enable sensing across
the isolation boundary
Features
Package Dimension
176-pin HLQFP 24x24mm2
337-pin NFBGA 16x16mm2
Packages
Processing
C28x™ DSP
core
200 MHz
FPU
TMU
VCU-II
CLA DSP
core
200 MHz
Floating-Point Math
CLA DSP
core
200 MHz
Floating-Point Math
6ch DMA 6ch DMA
Memory
Up to 512 KB Flash
Up to 102 KB SRAM
Memory
Up to 512 KB Flash
Up to 102 KB SRAM
2x 128-bit Security Zones
Boot ROM
2x EMIF
controlSUITE™
Software
Code Composer Studio
(CCS) IDE
Software
TMS320F28379D Experimenter’s Kit
Part Number: TMDXDOCK28379D
Digital Power SDK
& powerSUITE
SafeTI

Open loop control software
PWM1 A/B
PWM2 A/B
PWM3 A/B
a
c
b
PWMDAC
MACRO MFuncC1
MFuncC2
PWMxA
PWMxB
Low
Pass
Filter
Cct
DATALOG
Dlog1
Dlog2
Dlog3
Dlog4
Scope
Graph
Window
DQ0_ABC
Ds
sin(angle), cos(angle)
Qs
Freq
PWM
MACRO
PWM
HW
Sine/Cos
Angle
RG
MACRO
ISR_Period
c
b
a i
i
i ,
,
c
b
a v
v
v ,
,
ABC_DQ0
ABC_DQ0
PLL_3ph
Sine/Cos
c
b
a i
i
i ,
,
c
b
a v
v
v ,
,
d
v
q
v
Pll_theta
Pll_theta
Angle
ADC
HW
ADC
READ
d
i
q
i
IdRef
IqRef

Grid connected control software
PWM1 A/B
PWM2 A/B
PWM3 A/B
a
c
b
PWMDAC
MACRO
MFuncC1
MFuncC2
PWMxA
PWMxB
Low
Pass
Filter
Cct
DATALOG
Dlog1
Dlog2
Dlog3
Dlog4
Scope
Graph
Window
DQ0_ABC
Ds
Qs
Id_Ref
PWM
MACRO
PW
M
HW
c
b
a i
i
i ,
,
c
b
a v
v
v ,
,
ABC_DQ0
ABC_DQ0
PLL_3ph
Sine/Cos
c
b
a i
i
i ,
,
c
b
a v
v
v ,
,
d
v
q
v
Pll_theta
ADC
HW
ADC
READ
PI MACRO
Id Reg
Iq_Ref PI MACRO
Id Reg
d
i
q
i
d
i
q
i
sin(angle),
cos(angle)
Power_3Ph
d
i
q
i
d
v
q
v
P
Q

TI control loop features
Includes
• All filter blocks tested
• Feedback sensing validated
• Hardware control validation
• Basic grid connected current feedback
control loop
Left to the Customer
• P&Q Control
• DC Bus Regulation
• Unbalanced Load Control
• Anti-Islanding
• Additional Safety Features

• 10kW 3-Phase 3-Level inverter using SiC MOSFETs
• System Specifications:
• Input : 800V/1000V
• Output : 400VAC 50/60 Hz
• Power : 10KW/10KVA
• Efficiency : > 99% peak efficiency
• PWM frequency : 50kHz
• Uses ISO5852, UCC5320 gate driver & C2000 MCU controller
• Uses Littelfuse LSIC1MO120E0080 1200V 80mOhms SiC MOSFETS
• Reduces output filter size by switching inverter at 50KHz
• Isolated current sensing using AMC1306 for load current monitoring
• Differential voltage sensing using OPA4350 for load voltage monitoring
• Targets less than 2% output current THD at full load
• 3-Level T-type inverter topology for reduced ground current in transformer-less
grid-tie inverter applications
• Reduced size at higher efficiency using low Rdson SiC MosFET and higher
switching frequency (50kHz) at higher power (10kW)
• Platform for testing both 2-level and 3-level inverter by enabling or disabling middle
devices through digital control.
Design Features Design Benefits
• TIDA-01606 Tools Folder
• Test Data/Design Guide
• Design Files: Schematics, BOM and BOM Analysis, Design Files
• Key TI Devices: UCC5320, ISO5852, AMC1306, SN6505, TMS320F28379D,
OPA4350, OPA350, LM76003, PTH08080WAZT, UCC27211
TIDA-01606
10kW 3-Phase 3-Level Grid Tie inverter reference design for solar string inverter
Tools & Resources
[Preliminary View]
Size: 350mm X 200mm X 100mm

TI Part Number Device Description Why did we pick this device?
ISO5852S 5A/5A, 5.7Vrms Isolated Single
Channel Gate Driver
High current source/sink with bipolar
supply voltage best fit for driving SiC
Mosfet.
TMDSCNCD28379D Dual-Core Delfino Microcontroller Standard 180pin form factor control card
with C2000 controller provides enough
bandwidth for complete digital control of
3phase inverter.
AMC1306M05 Precision, ±50mV Input, 3µs Delay,
Reinforced Isolated Amplifier
Replaces bulky low frequency CT with
shunt for measuring 50/60Hz current.
OPA4350 High-Speed, Single-Supply, Rail-to-Rail
Operational Amplifiers
Low noise with high slew rate ideally
suited for high frequency input signal
conditioning.
Key TI parts

Total Size: 350mmx 200mm x 100mm
TIDA-01605 Driver TIDA-01605 Driver TIDA-01605 Driver
Key hardware

Measured Efficiency (vs) Load
99.07% Peak Efficiency
93
94
95
96
97
98
99
100
0% 20% 40% 60% 80% 100% 120%
Efficiency
(%)
Load (% of 10kW)
99.07%
Testing results

 99.07% Peak Efficiency at 8kW
 99.02% Efficiency at 10kW
 1.4kW/l
SYSTEM PARAMETER VALUE
Input Voltage 600-1000Vdc
Output Voltage 400VAC 50/60Hz
Maximum Power 10kW
PWM Frequency 50kHz
Efficiency (Peak) 99.07% @ 8kW
Efficiency (Full Load) 99.02% @ 10kW
Size 350mm x 200mm x 100mm
Measured Results Summary
Summary

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