Design and Implementation of Half Adder & Full Adder using Verilog HDL

Design and Implementation of
Half Adder & Full Adder using
Verilog HDL
Presented by:
Anirban Nath
M.Tech in Microelectronics & VLSI Design
NIT Silchar
Tools Used: Xilinx Vivado

Table of Contents
1. Introduction
2.Half Adder
3.Full Adder
4.Conclusion
5. References

Introduction
What is an Adder?
An adder is a combinational circuit that performs the arithmetic addition of binary numbers.
It is one of the fundamental building blocks in digital electronics and VLSI design.
Two main types:
Half Adder
Full Adder

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Half Adder
Adds two single-bit binary numbers.
Produces Sum (S) and Carry (C) outputs.
Truth Table:
It has two input & two output.

A B Sum(s) Carry(c)
0 0 0 0
0 1 1 0
0 0 1 0
0 1 0 1
A B 0 1
0 0 1
1 1 0
A B 0 1
0 0 0
0 0 1
Half Adder
Truth Table:
S=Σm(1,2)
C=Σm(3)
K-Map for Sum (S)
K-Map for Carry (C)
S=A′B+AB= A⊕B
C=AB

Half Adder
Logic Diagram:
S= A⊕B
C=AB

Half Adder
Verilog Code
module half_adder(
input A, B,
output reg Sum, Carry
);
always @(*) begin
Sum = A ^ B;
Carry = A & B;
end
endmodule
Test Bench
module tb_half_adder;
reg A, B;
wire Sum, Carry;
// Instantiate DUT
half_adder uut (.A(A), .B(B), .Sum(Sum), .Carry(Carry));
initial begin
$display("A B | Sum Carry");
$monitor("%b %b | %b %b", A, B, Sum, Carry);
A=0; B=0; #10;
A=0; B=1; #10;
A=1; B=0; #10;
A=1; B=1; #10;
$finish;
end
endmodule

Half Adder
Waveform
TCL console

Full Adder
Adds three inputs: A, B, and Cin (Carry-in).
Produces Sum (S) and Carry-out (Cout).

A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
A/BCin 0 1 11 10
0 0 1 0 1
1 1 0 1 0
A/BCin 0 1 11 10
0 0 0 1 0
1 0 1 1 1
S=A⊕B⊕C
Truth Table: K-Map for Sum (S)
K-Map for Carry (C)
Cout
=AB+ACin
+BCin
S=Σm(1,2,4,7)
Full Adder
Cout=Σm(3,5,6,7)
S=A′B′Cin
+A′BCin′
+AB′Cin′
+ABCin

Full Adder
Cout=Σm(3,5,6,7)
Cout
=A′BCin
+AB′Cin
+ABCin′
+ABCin
Cout
=(A′BCin
+AB′Cin
)+(ABCin′
+ABCin
)
Cout
=(A′B
+AB′)Cin+AB(Cin′
+Cin
)
Cout
=(A⊕B)Cin+AB
Cout
=AB+(A⊕B)Cin
Logic Diagram

Full Adder
Verilog Code
Test Bench
module full_adder(
input A, B, Cin,
output reg Sum, Cout
);
always @(*) begin
Sum = A ^ B ^ Cin; // XOR for Sum
Cout = (A & B) | (B & Cin) | (A & Cin); // function for Carry
end
endmodule
module tb_full_adder;
reg A, B, Cin; // Input signals
wire Sum, Cout; // Output signals
// Instantiate the DUT (Device Under Test)
full_adder uut (.A(A), .B(B), .Cin(Cin), .Sum(Sum), .Cout(Cout));
// Apply all test cases
initial begin
$display("A B Cin | Sum Cout");
$display("-----------------");
// $monitor automatically prints when any value changes
$monitor("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
// Stimulus
A=0; B=0; Cin=0; #10;
A=0; B=0; Cin=1; #10;
A=0; B=1; Cin=0; #10;
A=0; B=1; Cin=1; #10;
A=1; B=0; Cin=0; #10;
A=1; B=0; Cin=1; #10;
A=1; B=1; Cin=0; #10;
A=1; B=1; Cin=1; #10;
$finish;
end
endmodule

Full Adder
Waveform
TCL console

Conclusion
Successfully designed and implemented Half Adder and Full Adder circuits using
Verilog HDL.
Verified the functionality through simulation waveforms using Xilinx Vivado.
Derived and validated Boolean expressions using Truth Tables and K-Maps.

References
M. Morris Mano and Michael D. Ciletti, Digital Design, 6th Edition, Pearson.
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design,
McGraw-Hill.
Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Pearson.
Xilinx Vivado Design Suite User Guide (UG901 & UG937).
Online Verilog HDL resources and Xilinx documentation from https://hdlbits.01xz.net

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