Lecture verilog ii_c
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This document summarizes key topics covered in an ECE 287 lecture on Verilog HDL for sequential circuits. It discusses sequential circuits using "<=" assignments in always blocks, including circuit reset functionality. It provides examples of parameter usage and problems, such as building a circuit with multiple multipliers storing results in flip-flops with a reset and clock. Students are instructed to work on problems in groups, including building a RAM module from the previous class.
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Lecture verilog ii_c
- 1. ECE 287 –Lecture Verilog II Verilog HDL with Sequential Circuits
- 2. Announcements Next Wednesday Exam II– Nov 15th Last Day to Demo Labs – Nov 14th Project Oral Proposal - Nov 1st
- 5. What you shouldknow how to use in Verilog •The Golden Rule I •Combinational always blocks •If, Case •Modules instantiated in other modules •? Operator •Groupings •Constants •Conditionals •Logic Operators If you don’t talk to me…
- 6. Sequential Circuits …example What’s different?
- 7. Second Golden Rule!!! •Use “=“ in combinational always blocks • Use “<=“ in sequential always blocks
- 8. Circuit Reset This ishow you’ll write most sequential circuits… Include a reset !!!
- 9. Use fully definedif and case structures… For the following example, what is the value of c?
- 10.
- 11. Problem… Build a circuitthat has 2, 8 bit multipliers and 1 32 bit multiplier and stores the result in flip-flops. It needs a reset and clock.
- 12. Problem as agroup… Build the ram from last class…
- 13. Problem Set 1. BuildVerilog code for a counter that counts from 0 to 259 and then starts over. 2. Build Verilog code that multiplies by 5.