MICROCONTROLLER 8051- Architecture and registers

UNIT IV
MICROCONTROLLER
EC22503
Microprocessors & Microcontroller
Dr. C.Helen Sulochana
Professor/ECE

Architecture of 8051 – Special Function Registers(SFRs)
– I/O Pins Ports and Circuits – Instruction set –
Addressing modes – Assembly language programming.
CO4: Interpret the overview of the internal
architecture and various operating modes of a
typical microcontroller.

MICROCONTROLLER
• A smaller computer on a CHIP
• On-chip RAM, ROM, I/O Ports, Timer, Serial Controller
Microprocessor vs. Microcontroller
Microprocessor
• CPU is stand-alone, RAM, ROM,
I/O, timer are separate
• Designer can decide on the amount
of ROM, RAM and I/O ports.
• Expansive
• Versatility
• General-purpose
Microcontroller
• CPU, RAM, ROM, I/O and timer are
all on a single chip
• Fixed amount of on-chip ROM, RAM,
I/O ports
• Not Expansive
• Single-purpose
• Special Purpose.

MICROCONTROLLER- 8051
• The 8051 is an 8-bit processor
–The CPU can work on only 8 bits of data at a time
Features of 8051
8 bit Processor
16 bit Address bus
4KB Internal ROM
128 Bytes Internal RAM
Four 8 bit I/O PORTS
Two 16 bit Timers/Counters
On Chip Full Duplex UART for Serial Communication
5 Vector Interrupts ( 2 External, 3 Internal, Timer0,Timer1,Serial)
On Chip Clock Oscillator

Pin Diagram
8051 has 40 pins dedicated for functions
such as I/O, RD, WR, address, data, and
interrupts

1. On– chip oscillators
The 8051 has an on-chip oscillator but requires an external clock to run it
 A quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2
(pin18)
 The quartz crystal oscillator also needs two capacitors of 30 pF value
XTAL1 and XTAL2
If you use a frequency source other than a crystal oscillator, such as a TTL oscillator:
 It will be connected to XTAL1
 XTAL2 is left unconnected
 The speed of 8051 refers to the maximum oscillator frequency connected to XTAL.
 We can observe the frequency on the XTAL2 pin using the oscilloscope.
Upon applying a high pulse to this pin, the microcontroller will reset and terminate
all activities
2. RST- RESET pin
 Normally EA pin is connected to Vcc
 EA pin must be connected to GND(logic 0) to indicate that the code or data is
stored externally.
3. EA’ - external access

4. PSEN’ and ALE- program store enable & Address latch Enable
 PSEN, “program store enable’’, is an output pin
 This pin is connected to the OE pin of the external memory.
 For External Code Memory, PSEN’ = 0
 For External Data Memory, PSEN’ = 1
 ALE pin is used for demultiplexing the address and data.
When ALE=0, it provides data D0-D7
When ALE=1, it has address A0-A7
The four 8-bit I/O ports P0, P1, P2 and P3.
5. I/O Port Pins
 Bidirectional I/O port
 When connecting to an external memory(external program or data memory), port 0
also acts as multiplexed lower order address and data bus(provides both address
and data
1. Port 0 (P0.0-P0.7).
PROG - During Flash Programming, this pin acts as program pulse input (PROG).

In 8051-based systems with no external memory connection:
Both P1 and P2 are used as simple I/O.
In 8051-based systems with external memory connections:
Port 2 must be used along with P0 to provide the 16-bit address for the external
memory.
P0 provides the lower 8 bits address (A0 – A7).
P2 is used for the upper 8 bits of the 16-bit address, designated as A8 – A15,
and it cannot be used for I/O.
Port 1 and Port 2
Port 3
 Multifunctional port
 Programmed to act as I/O
port or as one of the
alternate function as
specified in the table

MICROCONTROLLER 8051- Architecture and registers

Architecture of 8051
Harvard architecture with separate program and data memory;

8051 architecture consists of
1. CPU
2. Memory- data memory(RAM) and Program memory(ROM)
3. Input/output port-I/O ports
4. Special function register
1. Central processing unit(CPU)
 CPU consists of 8-bit arithmetic and logic unit(ALU) with registers like A, B, PSW, SP,
16-bit program counter, Data pointer(DPTR) registers and special function registers
 ALU can manipulate 1-bit, 8-bit data types
The 8-bit accumulator register A (addresses OEOH ) is used to store temporary
values and the results of arithmetic operations.
Accumulator A and Reister B
Register B (addresses OFOH) – 8-bit register used for multiply/divide
operation.

Data pointer(DPTR) registers
 DTPR consists of a high byte(DPH- address 83H) and
a low byte((DPL-address 82H)
 It used as a16-bit register or two independent 8-bir
registers
 It serve as a base register
Program counter
16-bit program counter used to hold the address of memory location from which the next
instruction is to be fetched
Flag register
Flag register is a 8-bit register. Its bit pattern is indicated by Program status word
Program status word

 FO- Available for user for general purpose
Serve as borrow flag for subtraction
 RS1-RS0 – Register bank select- They selct the working register bank as follows
 OV-Over flow- This flag is set when the result of signed number causes the higher
order bit to overflow into sign bit
 P – Parity flag- parity is number of ones in the accumulator
p=0 even parity
p=1, odd parity
 CY- carry flag-This flag is set when carry during addition
Serve as borrow flag for subtraction
 AC-Auxiliary carry flag-This flag is set when there is a carry from lower nibble to higher
nibbles

2. Memory- data memory(RAM) and Program memory(ROM)
8051 can access up
to 64k program
memory and 64k
data memory
It has 4K bytes of
internal program
memory(ROM) and
128 bytes of
internal data
memory(RAM)

Internal RAM Organization
8051 has 128 bytes internal RAM
It is organized into three distinct areas
 Register bank
 Bit addressable RAM
 General purpose (scratch pad RAM)
Register banks
 Consist of 32 register from 00H to 1FH
 They are organized into four groups of eight
registers each
 Register bank 0 (00H -07H)
 Register bank 1 (08H -0FH)
 Register bank 2 (10H -17H)
 Register bank 3 (18H -1FH)
Each consists of 8 registers named R0- R7

 Only one register bank is in use at a
time.
 Bits RS0 and RS1 in the PSW
determine which bank of register is
currently in use.
 Bank 0 is default register bank
 Register bank when not selected used
as general purpose RAM
Bit Addressable RAM
 It is 16 bytes RAM from 20H to 2FH
 A total of 128(16x8) addressable bits
General purpose RAM
 General purpose RAM is the RAM area above bit addressable area from 30H to 7FH
 It is byte addressable
ROM in 8051
 8051 has 4Kbyte of internal ROM with address from 0000H to 0FFFH
 It is programmed by manufacturer when the chip is built

3. Input/output port-I/O ports
and data
1. Port 0 (P0.0-P0.7).
memory.
Port 1 and Port 2
Port 3
 Programmed to act as I/O port or as one of the alternate function as specified in the
table

 The 8051 is a flexible microcontroller with a relatively large number of modes of
operations.
 operating mode of the 8051 by manipulating the values of the 8051's Special Function
Registers (SFRs).
 SFRs are accessed as if they were normal Internal RAM.
 The only difference is that Internal RAM is from address 00H through 7FH whereas SFR
registers exist in the address range of 80H through FFH.
4. Special Function Register(SFR) (Asked as a separate question)
 The special function register(80H to F0H) are
located above the 128 bytes of RAM. Totally 21
registers.
 All special function registers access to the 4 I/O
ports, CPU registers, Timer/counter, UASRT
and power control

special function register
Explain all the registers in
the table by referring the
previous slides

The 8-bit accumulator register A (addresses OEOH ) is used to store temporary
values and the results of arithmetic operations.
Accumulator A and Reister B
Register B (addresses OFOH) – 8-bit register used for multiply/divide
operation.
Program status word
Flag register is a 8-bit register. Its bit pattern is indicated by Program status word
Program status word

 The stack is a section of RAM used by the CPU to store information temporarily.
 This information could be data or an address
 The register used to access the stack is called the SP (stack pointer) register
 The stack pointer in the 8051 is only 8 bit wide, which means that it can take value of
00 to FFH
PUSH and POP
 The storing of a CPU register in the stack is called a PUSH
 SP is pointing to the last used location of the stack
 As we push data onto the stack, the SP is incremented by one. This is different from
many microprocessors
 Loading the contents of the stack back into a CPU register is called a POP
 With every pop, the top byte of the stack is copied to the register specified by the
instruction and the stack pointer is decremented once
8051 Stack
 The Power Control SFR is used to control the 8051's power control modes.
 Certain operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode
which requires much less power.
 Additionally, one of the bits in PCON is used to double the effective baud rate of the
8051's serial port.
PCON (Power Control, Addresses 87H):

Data pointer(DPTR) registers
 DTPR consists of a high byte(DPH- address 83H) and
a low byte((DPL-address 82H)
 It used as a16-bit register or two independent 8-bir
registers
 It serve as a base register
 used to enable and disable specific interrupts.
 The lower 7 bits of the SFR are used to enable/disable the specific interrupts,
 the highest bit is used to enable or disable(IE is 0) ALL interrupts.
IE (Interrupt Enable)
 used to specify the relative priority of each interrupt.
 On the 8051, an interrupt may either be of low (0) priority or high (1) priority.
IP (Interrupat Priority, Bit-Addressable):

Input/output port-I/O ports
and data
1. Port 0 (P0.0-P0.7).
memory.
Port 1 and Port 2
Port 3
 Programmed to act as I/O port or as one of the alternate function as specified in the
table

 The Timer Control SFR is used to configure and modify the way in which the 8051's two
timers operate.
 Additionally, some non-timer related bits are located in the TCON SFR. These bits are
used to configure the way in which the external interrupts are activated
TCON (Timer Control, Addresses 88h, Bit-Addressable):
 This SFR is used to configure the mode of operation of each of the two timers.
 configure each timer to be a 16-bit timer, an 8-bit autoreload timer, a 13-bit timer, or two
separate timers.
 Additionally, configured to count "events" that are indicated on an external pin.
TMOD (Timer Mode, Addresses 89h):
TL0/TH0 (Timer 0 Low/High)
These two SFRs, taken together, represent timer 0.
,these timers always count up.
TL1/TH1 (Timer 1 Low/High):
These two SFRs, taken together, represent timer 1.
these timers always count up. What is configurable is how and when they increment in value.

SCON (Serial Control, Bit-Addressable):
 used to configure the behavior of the 8051's on-board serial port.
 controls the baud rate of the serial port, whether the serial port is activated to receive
data, and also contains flags that are set when a byte is successfully sent or received.
SBUF (Serial Buffer): - output port
 used to send and receive data via the on-board serial port.
 Any value written to SBUF will be sent out the serial port's TxD pin.
 Any value which the 8051 receives via the serial port's RxD pin will be delivered to the
user
The RCAP2 register in the 8051 microcontroller is a 16-bit register that holds the
reload/capture value for Timer 2:
RCAP2H is for higher order byte
RCAP2L is for higher order byte
RCAP2(reload or capture) register

I/O Pins Ports and Circuits of 8051 Microcontroller
Port 0 Structure
Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it
floats (tristated) when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'.
Port-0 Pin Structure
Port -0 has 8 pins (P0.0-P0.7).

Port-0 can be configured as a normal bidirectional I/O port or it can be used for
address/data interfacing for accessing external memory. When control is '1', the port
is used for address/data interfacing. When the control is '0', the port can be used as a
normal bidirectional I/O port.
Let us assume that control is '0'. When the port is used as an input port, '1' is written
to the latch. In this situation both the output MOSFETs are 'off'. Hence the output pin
floats. This high impedance pin can be pulled up or low by an external source. When
the port is used as an output port, a '1' written to the latch again turns 'off' both the
output MOSFETs and causes the output pin to float. An external pull-up is required to
output a '1'. But when '0' is written to the latch, the pin is pulled down by the lower
MOSFET. Hence the output becomes zero.
When the control is '1', address/data bus controls the output driver MOSFETs. If the
address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is
'on'. The output becomes '0'. If the address/data bus is '1', the upper transistor is 'on'
and the lower transistor is 'off'. Hence the output is '1'. Hence for normal address/data
interfacing (for external memory access) no pull-up resistors are required.
Port-0 latch is written to with 1's when used for external memory access.

Port-1 Pin Structure
Port-1 has 8 pins (P1.1-P1.7) .The structure of a port-1 pin is shown in fig below.
Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing.
When used as output port, the pin is pulled up or down through internal pull-up. To use
port-1 as input port, '1' has to be written to the latch. In this input mode when '1' is written
to the pin by the external device then it read fine. But when '0' is written to the pin by the
external device then the external source must sink current due to internal pull-up. If the
external device is not able to sink the current the pin voltage may rise, leading to a
possible wrong reading.
Port 1 Structure

PORT 2 Pin Structure
Port-2 has 8-pins (P2.0-P2.7) . The structure of a port-2 pin is shown in figure below:
Port-2 is used for higher external address byte or a normal input/output port. The I/O
operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for
external memory access. Here again due to internal pull-up there is limited current
driving capability.
Port 2 Structure

Port-3 has 8 pin (P3.0-P3.7). Port-3 pins have alternate functions. The structure of a port-3
pin is shown in figure
Port 3 Structure
Each pin of Port-3 can be individually programmed for I/O operation or for alternate
function. The alternate function can be activated only if the corresponding latch has been
written to '1'. To use the port as input port, '1' should be written to the latch. This port also
has internal pull-up and limited current driving capability.

Addressing Modes
1.Register Addressing Mode
2.Immediate Addressing Mode
3.Direct Addressing Mode
4.Register indirect Addressing Mode
5.External Addressing Mode
Addressing modes - the way in which an operand is specified and the way that the
processor can access the data
Instruction is divided into two groups of bits or fields
1.Operation code(op code) -specifies the operation to be performed.
2. operand - data or information needed to perform an operation.
The 8051 has 12 Addressing modes can be classified into five groups

1. Register Addressing Mode
• Use eight registers(R0 –R7). Three bit within the instruction selects one of
the eight registers from the selected bank..
• The source and destination registers must match in size.
MOV DPTR,A will give an error
• The movement of data between Rn registers is not allowed
MOV R4,R7 is invalid
• The register bank is decided by 2 bits of Processor Word (PSW).
The instruction will specify the name of the register which holds the data to be
operated

2. Immediate Addressing Mode
• The source operand is a constant.
• The immediate data must be preceded by the pound sign, “#”
• Can load information into any registers, including 16-bit DPTR register
– DPTR can also be accessed as two 8-bit registers, the high byte DPH
and low byte DPL
Data is immediately available in the instruction.

3. Direct Addressing Mode
• It is most often used the direct addressing mode to access RAM locations 30 – 7FH.
• The entire 128 bytes of RAM(MSB=0) or special function registers(MSB=1) can be
accessed .
• Contrast this with immediate addressing mode, there is no “#” sign in the operand.
• Looping is not possible.
The address of the data is available in the instruction.
Stack Addressing Mode
• Sub type of direct addressing mode
• Stack instruction PUSH and POP are used.
• PUSH A is invalid. Address of register A(0E0) is specified.
• PUSH 0E0H is valid. -Pushes the content of Accumulator on the stack

4. Register Indirect Addressing Mode
• Only register R0 and R1 of each register bank are used as pointer or index
register.
• R2 – R7 cannot be used to hold the address of an operand located in RAM.
• When R0 and R1 hold the addresses of RAM locations, they must be
preceded by the “@” sign.
• Increment or decrement the pointer register to access successive locations
The address of data is available in an index or pointer
register as specified in the instruction

either R0 or R1 used as Pointer
5. External Addressing (Index):
MOVX A, @R0; Moves content of 8-bit address pointed by R0 to A
MOVX A, @DPTR; Moves content of 16-bit address pointed by DPTR to A
Only program memory(External memory) or ROM is accessed in index addressing
MOVC A, @A+PC;
MOVC A, @A+DPTR
E.G: Code for 8-segment displays never changes, that code is fixed and we are not
interested in changing the code, so we store this data in ROM.
DTPR must be loaded with the address of External memory
either DPTR or PC can be used as index register
External program /ROM addressing (Index):
External Data/RAM addressing
Data memory(External memory) or RAM is accessed in this addressing

8051 Instructions
1.Data Transfer Instruction
2.Byte level logical Instruction
3.Bit level logical Instruction
4.Arithmetic Instruction
5.Branching Instruction
8051 has about 111 instructions. These can be grouped into
1.Data Transfer Instruction
1.MOV Instruction
2.Instruction to access external data/RAM memory
3.Instruction to access external program/ROM memory
4.Data transfer with stack
5.Data exchange instruction
involve two operands: Source operand and Destination operand of same size
 Source: is a Register or a memory location or an immediate data
 Destination: is a Register or a memory location.
used to transfer data/ address in to registers, memory locations and I/O ports.
Both Source and Destination cannot be memory location at the same time.

MOV Instruction
MOV destination, source ; copy source to destination.
 Immediate, direct, register, and indirect addressing mode can be used in MOV
instruction
MOV A,#55H ;load value 55H into reg. A
MOV R0,A ;copy contents of A into R0 ;(now A=R0=55H)
MOV R3,#95H ;load value 95H into R3 ;(now R3=95H)
Example
Instruction to access external data/RAM memory
All external data moves with external RAM involve the A register
R register can address 256 bytes, DPTR can address 64 bytes
Example
MOVX instruction is used to access external RAM or I/O addresses
• MOVX A, @Ri ; copy the content of external address in Ri to A MOVX
A,@DPTR ; copy the data from 16 bit address in DPTR to A

Instruction to access external program /ROM memory
•When PC is used to access external ROM, ii is incremented by 1 before it adds to A
to form the physical address of the ROM
•All the external data moves with external ROM involves A register.
Example
Data transfer with stack
• Stack instruction PUSH and POP are used.
PUSH B ; increment the SP by one and store the content of register B to the internal
RAM location.
POP B; copy the content of internal RAM location addressed by SP to the register B
and SP is decremented by one
Example

Data exchange instructions
–All exchange involve the A register
–Immediate addressing mode cannot be used.
Move the data from source to destination and vice versa
• XCH A, Rn ; Exchange data bytes between Rn and A
• XCHD A,Rn ; Exchange lower bytes nibbles
Example
2. Byte level logical Instruction
perform logical operation(AND, OR, Ex-OR) between two byte variables(destination,
source) and leaving the result in the destination
Destination : A / memory , Source: data/register/memory
No flags are affected. All 4 addressing modes are used.
ANL A, Rn ; logically AND the content of A and Rn and store result in A
ORL A, #32H; logically OR the content of A with 32H and store result in A
XRL A, @R2H; logically XOR the content of A and the memory location whose
address is given by R2 and stores result in A
Example

CLR A ; clear accumulator
CPL A; complement accumulator

3.Bit level logical Instruction
Similar to logical instructions, these instructions also perform logical operations.
The difference is that these operations are performed on single bits.
To set or reset a particular bit in the internal RAM or special function register(SFR)
CPL C ; complement carry flag
CLR A ; clear accumulator
SETB, bit ; set the indicated bit to 1
ANL C, bit ; Logical AND operation between Carry bit and directly addressed bit.
 ORL C, bit ; Logical OR operation between Carry bit and directly addressed bit.
MOV C, bit ; Move directly addressed bit to carry bit.
Example
4. Arithmetic Instruction
perform 8 bit addition, subtraction, multiplication, increment-decrement operations
Addition
ADD A, R2 ; Add the content of Accumulator A and Register R2 and store the result in A
- carry flag (CY) is set/reset appropriately.
ADDC A, 20H (add with carry) ; Add the contents of A , memory location whose
address is 20H and previous value of carry flag and stores result in A

Subtraction
SUBB A, R2 ;(Subtract with borrow) -subtract the content of R2 and carry together and
store the result in A
Multiply and divide
MUL AB ; Multiply the unsignned 8 bit
integer in A and register B
lower order byte of 16 bit product is in A and
Higher order byte in B
DIV AB ; Divides the unsignned 8
bit integer in A by register B
Quotient is in A and remainder in B
Decimal adjust Accumulator for Addition
DA A ; Decimal adjustment of accumulator (BCD addition)
INC A A = A + 1
INC Rn Rn = Rn + 1
Increment and decrement
 Increment or decrement the operand by 1
 Operand can be register, direct address,
indirect address or data pointer
Example

These instructions change the flow of the program by changing the contents of program
counter
 JUMP –permanently change the program flow
 CALL - temporarily change the program flow to allow another part of program to run
New address from the address of program counter is called range of the jump or call
5. Branching Instruction
Unconditional Jump Instructions
• All conditional jumps are short jumps
–Target address within -128 to +127 of PC
• LJMP (long jump): 3-byte instruction
–2-byte target address: 0000 to FFFFH
–Original 8051 has only 4KB on-chip ROM
• SJMP (short jump): 2-byte instruction
–1-byte relative address: -128 to +127

Call Instructions
• LCALL (long call): 3-byte instruction
–2-byte address
–Target address within 64K-byte range
• ACALL (absolute call): 2-byte instruction
–11-bit address
–Target address within 2K-byte range

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