Question Bank Microprocessor 8085

Microprocessor & Interfaces
Question Bank
Department of Electronics Engineering
Dr. Nilesh Bhaskarrao Bahadure
Page 1
SHORT ANSWER TYPE QUESTIONS
Marks: 2 each
1. List the components of a computer.
2. Explain the function of each component of a computer.
3. What is a Microprocessor? What is the difference between a Microprocessor & CPU?
4. Define bit, byte, word, double word, quad word and instruction
5. What determines that Microprocessor is an 8, 16 or 32 bit?
6. Explain the difference between the machine language and the assembly language of
the 8085 microprocessor.
7. What is an assembler?
8. What are low and high level languages?
9. What are the advantages of an assembly language in comparison with high level languages?
10. List the four operations commonly performed by the MPU.
11. Specify the four control signals commonly used by the 8085 MPU.
12. Specify the function of the address bus and the direction of the information flow on the address
bus.
13. Why is the data bus bidirectional?
14. What is a bus?
15. How many memory locations can be addressed by a microprocessor with 14 address lines?
16. How many address lines are necessary to address two megabytes (2048K) of memory?
17. Why is the data bus bidirectional?
18. Specify the control signal and the direction of the data flow on the data bus in a memory‐write
operation.
19. What is the function of the accumulator?
20. What is a flag?
21. Why are the program counter and the stack pointer 16‐bit registers?
Total Questions 544

Question Bank
Page 2
22. What is the function of the WR signal on the memory chip?
23. Specify the number of registers and memory cells in a 128 x 4 memory chip.
24. What is the memory word size required in an 8085 system?
25. While executing a program, when the 8085 MPU completes the fetching of the machine code
located at the memory address 2057H, what is the content of the program counter?
26. What is the role of clock in Microprocessor?
27. Which pins of 8085 carry only data?
28. Which pins of 8085 are bidirectional?
29. Differences between the 8155/8156 and 8355/8755 peripherals.

Mid Range Questions (4 to 6 Marks)

30. What is the difference between INR & INX instructions?
31. List all the interrupt signals of 8085 microprocessor.
32. Write short note on evolution of microprocessors.
33. Explain the functions of the ALE and IO/M signals of the 8085 microprocessor.
34. List the sequence of events that occurs when the 8085 MPU reads from memory.
35. If the 8085 adds 87H and 79H, specify the contents of the accumulator and the status of the S, Z,
and CY flags.
36. If the clock frequency is 5 MHz, how much time is required to execute an instruction of 18 T‐
states?
37. Discuss the programming model of 8085 µP with the help of suitable diagram.
38. Draw and explain the timing diagram for opcode fetch operation
39. Discuss various types of addressing modes of 8085.
40. Explain why the number of output ports in the peripheral‐mapped I/O is restricted to 256 ports.
41. In the peripheral‐mapped I/O, can an input port and an output port have the same port
address? Explain.

Question Bank
Page 3
42. What are the control signals necessary in the memory‐mapped I/O?
43. List the four categories of 8085 instructions that manipulate data.
44. Define opcode and operand, and specify the opcode and the operand in the instruction
MOV H, L.
45. Write logical steps to add the following two Hex numbers. Both the numbers should be saved
for future use. Save the sum in the accumulator. Numbers: A2H and 18H.
46. What is the need for ALE signal in microprocessor 8085?
47. How many machine cycles are needed to execute STA 1000h and MVI M, 30h
48. What is the need for interfacing?
49. Compare memory mapped I/O and Peripheral mapped I/O.
50. Differentiate between CALL/RET and PUSH/POP
51. Differentiate between SRAM and DRAM.
52. Differentiate between full decoding and absolute decoding technique.
53. What is memory, Classify the read/write and read only memory
54. State the disadvantages of memory mapped I/O scheme.
55. Differentiate between software and hardware interrupt?
56. What is interrupt? Name the vectored and non vectored interrupts of 8085?
57. What do you mean by timing diagram?
58. Define instruction cycle and machine cycle?
59. Define T – state and in which T cycle the ALE signal is activated?
60. What do you mean by masking the interrupt? How it is activated in 8085 system?
61. Show the different instruction formats used in 8085.
62. What is the type of stack used in 8085?
63. What are the different addressing modes of 8085?
64. Define addressing modes. How many addressing modes are available in 8085?
65. The last executable instruction in a procedure must be ………….. .
66. Explain the following instruction:

Question Bank
Page 4
i. LHLD 8020
ii. XTHL
67. What is the subroutine? How it is useful?
68. Explain the need of software timers.
69. If the CALL and RET instructions are not provided in the 8085, could it be possible to write
subroutines for this microprocessor? If so how will you call and return from the subroutine?
70. What is the significance of ‘XCHG’ and ‘SPHL’ instructions?
71. Write an initialization program to mask RST 6.5 and disable RST 5.5 and RST 7.5
72. Write an initialization program to disable RST 7.5 and enable RST 5.5 and RST 7.5
73. After the execution of RIM instruction, the contents of the accumulator is found to be 4Ch. Put
your comments on the result.

LONG ANSWER TYPE QUESTIONS
   Architecture and operation.

1. Give a general block diagram of a microprocessor based system. Explain briefly the various
blocks of the system. Give some examples of the types of devices used for each block.
2. What is a microprocessor? Sketch and explain the various pins of 8085.
3. Sketch and explain the signal diagram of 8085.
4. Explain the operation of 8085 signals: READY, S1 & S0, HOLD & HLDA and ALE.
5. Explain the architecture of 8085 with the help of its internal block schematic.
6. Write the flag register and explain each of the flags with an example.
7. Mention the list of registers of 8085 that are accessible to the programmer. Explain what each
of these registers is generally used for.

Question Bank
Page 5
8. What should be the starting address of ROM for an 8085 microcomputer? Substantiate your
answer.
9. Explain the purpose of the following signals of 8085: AD0‐AD7, /RESET IN, RESET OUT, and RST
7.5.
10. Explain with schematic diagram how separate address, data signals can be generated from 8085
common address‐data lines.
11. Explain the schematic which decodes IO//M, /RD, /WR into two active low signals /MERD,
/MEWR, /IORD and /IOWR.
12. List the status signals in 8085. Explain their functions.
13. List the control signals in 8085. Explain their functions.
14. Explain, how the microprocessor works?
15. Explain the operations of microprocessor.
16. What are RAM’s and ROM’s? Why should both of these be used in an 8085 system?
17. Explain the functions of following 8085 registers in Intel 8085: HL, STACK POINTER, and FLAG
REGISTER.
18. (a) Specify the contents of the registers and the flag status as the following instructions are
executed.
i. MVI A, 00H
ii. MVI B, F8H
iii. MOV C, A
iv. MOV D, B
v. HLT
(b) Write instructions to load the hexadecimal number 65H in register C and 92H in accumulator
A, Display the number 65H at PORT0 and 92H at PORT1.
19. Draw and explain the block diagram of a microprocessor 8085.
20. Why the lower order address bus is multiplexed with data bus? How they will be de‐
multiplexed?
21. Differentiate between maskable and non‐maskable interrupts.

Question Bank
Page 6
22. Write an 8085 assembly language program using minimum number of instructions to add the 16
bit no. in BC, DE & HL. Store the 16 bit result in DE pair.
23. Mention the features of 8085.
24. Describe the functions of the following registers of 8085: Instruction Register, PC, SP,
Incrementer / Decrementer Address latch.
25. How many temporary registers are there in8085? Mention their utilizations.
26. Discuss the scheme of multiplexing Address/Data bus in 8085.
27. Explain the structure of flag register of 8085.
28. With a neat diagram discuss the architecture of 8085.
29. Classify the registers of 8085 and mention their functions in brief.
30. Why Accumulator is said to be a special register?
31. What are program visible and program invisible registers?
32. Why it is said that HL pair is a special pair?
33. Write a brief note on ‘virtual register’.
34. Classify various pins of 8085.
35. Mention the functions of the following pins of 8085: ALE, CLK OUT, RESET OUT, RESET IN
36. Mention the functions of the clock related pins of 8085.
37. Briefly discuss the how clock signal is generated in 8085.
38. Mention the pins which carry both address as well as data. How they are demultiplexed?
39. Why the address bus is unidirectional whereas data bus is bidirectional?
40. How can you generate IOR, IOW, MEMR and MEMW signal?
41. (a) Explain in detail the following instructions:‐
(i) ADC (ii) LHLD (iii) RLC (iv) DI
(b) Define & explain the term addressing modes.

Question Bank
Page 7
Instructions and Programming of 8085.

42. Sketch the programming model and explain in detail.
43. What are the various addressing modes available in 8085? Explain with examples.
44. Explain the instruction format of 8085 microprocessor with an example.
45. How do you classify the instructions of 8085, based on a) Number of bytes b) Addressing
modes? Explain with examples.
46. Give two examples for each of the following types of instructions and indicate what each of
these instructions do:
a. Instructions with implied addressing.
b. ALU type of instructions.
c. Instructions addressing memory indirectly through any register pair.
d. Conditional branch instructions.
e. Interrupt related instructions.
47. Explain fully the action of the following 8085 instructions: ADC M, STAX D, RLC, LHLD 9898, and
TRAP.
48. Explain the following instructions and indicate the flags affected: DAA, DAD D, XCHG, HALT &
MOV M, A.
49. Define Instruction cycle, Machine cycle and T‐States with examples.
50. With suitable examples explain the addressing modes supported by 8085.
51. Classify the instructions of 8085 based on their operation.
52. Mention different ways to clear the accumulator and make a comparison between them.
53. Explain the meaning of the following instructions of 8085: LHLD, SHLD, XTHL, XCHG, SPHL, PCHL,
CMA, and DAD.
54. Differentiate between: CMP & SUB, RAL & RLC, RAR & RRC, JMP & CALL, PUSH & POP, XTHL &
SPHL.
55. Explain all stack related instructions.

Question Bank
Page 8
56. Explain all instructions related to HL pair.
57. Explain all sorts of conditional instructions.
58. Write a short note on DAA instruction.
59. Explain all exchange instructions supported by 8085.
60. Why INX and DCX instructions do not affect the flags?
61. Mention the instructions through which the user can have an access to flag register.
62. Mention an alternative instruction for JMP.
63. What are the various ways of initializing HL pair?
64. What are various ways of initializing DE pair?
65. What are the various ways of initializing Stack Pointer?
66. Write a short note on stack.
67. What are dummy operations? Give examples.
68. Mention various parts of an instruction.
69. What is label? How it is useful in writing a program?
70. Mention the meaning and addressing modes of the following instructions: MVI M, 03H, PUSH B,
RET
71. Can there be more than one HLT in an assembly language program? Justify your answer with a
suitable example.
72. Explain the following instructions indicating their addressing modes, flags affected, number and
names of machine cycles on the execution of each: XRA A, SUB M, & DCXSP.
73. Draw opcodes fetch machine cycle, memory write machine cycle and I/O read machine cycle
and explain.
74. Explain the various steps involved while executing CALL instruction with an example.
75. Explain DAA instruction with example.
76. Explain the functions and timing associated with STA and RST instructions.
77. Explain the working of CALL address and RET instructions, in terms of machine cycles.
78. Write an ALP for 8085 to multiply two 8‐bit numbers. Explain your program with only
comments.

Question Bank
Page 9
79. Write a program in 8085 to convert the binary number stored in location XX20h to BCD. Store
the possible three BCD digits in unpacked manner from location XX50h.
80. What is a stack? On what principle it works? Is it necessary to initialize stack pointer while
writing program? Explain with example.
81. Mention the uses of stack. Sketch the content of SP and stack memory after the execution of
each of the following instructions in the given order, if SP = 1000h, BC = 2030h and DE = 4050h
initially: PUSH B and PUSH D.
82. With suitable programming example clearly explain passing the parameter through registers,
through memory and through stack.
83. Explain stack operation in detail.
84. Sketch and explain briefly the timing diagram of the instruction MVI A, 32h, which is stored from
address 3000h.
85. Draw the timing diagram for the instruction STA 9000h.
86. Write an 8085 program to simulate a decimal upcounter to count 00 to 99. Use delay of 100
msec in between counts. Assume the operating frequency as 2 MHz.
87. What is the use of instruction ORA A? What is the status of CY and AC flags after the execution
of this instruction?
88. Write a recursive subroutine named FACT to find factorial of the number in 8085.
89. Using JMP, can you call a subroutine? Explain with an example and a corresponding ALP.
90. Write an ALP to count number of 1’s and 0’s present in a hex byte present at 9100h memory
location. Store number of 1’s at 9101h and number of 0’s at 9102h.
91. Write an ALP for 8085 processor to separate ODD and EVEN numbers from an array of 16
numbers stored from F100h. Store the EVEN numbers from F120h and ODD numbers from
F150h.
92. Write an ALP subroutine to produce a delay of 1 second. Consider the 8085 clocked at 5 MHz.
93. What is a subroutine? How it is useful? Explain the use of stack in CALL and RET instructions.
94. Explain any five logical instructions with their function, addressing modes and flags affected.

Question Bank
Page 10
95. Assume register B holds 94H and the accumulator holds 16H. Illustrate the results of the
instructions ORA B, XRA B, CMA, INX B separately alongwith the status flags.
96. Register E contains 01H. What will be the contents of the register E after DCR E has been
executed twice? Also mention the status of the flag register.
97. To write program on:
f. Addition of single byte numbers
g. Addition of multibyte numbers
h. Addition of BCD numbers
i. Subtraction of BCD numbers
j. Multiplication of unsigned binary number
k. Reversing an array
l. Sorting in ascending order
m. Sorting in descending order
n. Searching a block for a specific byte
o. Counting of the occurrence of a specified byte in a block
p. Conversion of BCD numbers into binary
q. Conversion of binary numbers into BCD
r. Counting the number of BCD number in an array
s. To add even and odd bytes separately from a block
t. Conversion of ASCII to binary
u. Conversion of binary to ASCII
v. Editing of an ACII string
98. Write two instructions to initialize stack pointer at FFFFh.
99. Compare the following pairs of instructions with their opcode operations instruction bytes,
addressing modes, affected flags and the results.
a. MVI A, 00 and   XRA A
b. SUB B and   CMP B
c. JMP 2700 and   PCHL

Question Bank
Page 11
d. XTHL and   SPHL
e. LDA 1000 and   LHLD 2000
f. RRC and RAR
100. How many times will the two JNZ instructions be executed in the following sequence? What
will be the contents of H and L when program control reaches to HLT instruction?
LXI H, 0503H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
HLT
101. The first four instructions of a typical subroutine are:
PUSH PSW
PUSH H
PUSH B
PUSH D
What will be the last five instructions of the subroutine? Explain clearly.
102. What is the roll of stack and stack pointer in processing interrupt service routine?
103. Explain the concept of subroutine in 8085 assembly language.
104. Draw timing diagram for execution of the instruction MVI A, 40h on 8085. Opcode for MVI A
is 3Eh.
105. Draw the timing diagram for the execution of RET instruction of 8085.
106. Draw the timing diagram for the execution of CALL instruction in 8085.
107. Explain the concept of machine cycle with the help of 8085 microprocessor.
108. Obtain logical OR of the data 0Fh and 02h.
109. Obtain EX‐OR of the data 22h and 13h.
110. Obtain logical AND of the data 0Fh and 02h.
111. Addition of two number of one byte each using registers only.

Question Bank
Page 12
112. Addition of two decimal numbers using registers only.
113. Addition of two decimal numbers referring memory locations.
114. Addition of two hexadecimal numbers stored in two consecutive locations and stores the
result at the third location.
115. Subtraction of two 8 bit numbers using registers only
116. Subtraction of two 8‐bit numbers with memory referencing.
117. Multiplication using ADD instruction
118. Write a program to obtain 1’s complement of the 16‐bit number stored at location 2115 and
2116h. Store the result at location 2117 and 2118h. MSB’s should be in location 2116 and
2118h.
119. Obtain 2’s complement of the number stored at location 2110 and store the result at 2111h.
120. Obtain 1’s complement of the data stored at memory location 2110 and place the result at
location 2111h.
121. Write a program to convert the binary number into gray code
122. Write a program to multiply the data 05 by 07d.
123. Obtain larger of the contents of memory locations 2140 and 2141h
124. Write a program to add two 16‐bit numbers from memory 2140 and 2141 with 2142 and
2143 store the result in next consecutive memory locations.
125. Write a program to multiply two 8‐bit numbers to result in 8 bit number only i.e. maximum
value could be FFh.
126. Write a program to multiply two 8‐bit numbers to result in 16 bit numbers.
127. Write a program to separate the hexadecimal number into two nibbles (MSB and LSB).
128. Write a program to form a byte from two nibbles.
129. Write a program to check the parity of data stored in the memory 2130h. Indication should
be 00 for odd parity and EE for the even parity. Stored the result in the next memory
location.
130. Write a program to multiply any number by 2 that is stored at location 2130h and stored the
result at 2131h.

Question Bank
Page 13
131. Write a program to multiply by 08h to a number stored at location 2130h and store the
result at location 2131h.
132. Multi byte addition when the result is more than data byte.
133. Multi byte addition for any number of bytes.
134. Subtraction of multi byte numbers when the value of the subtrahend is more than the
minuend.
135. Addition of series of numbers descending continuously to zero i.e.
20
I=1 I
136. Write a program to add and display the result automatically of s series of continuously
increasing number.
137. Multiplication of two 8‐bit numbers o result in the 16‐bit number by repetitive addition.
138. Multiplication of two 8‐bit numbers by registers shifting method.
139. Write a program to convert BCD to binary number. MSD and LSD numbers are stored at
location at 2140 and 2141 respectively.
140. Write a program to find out minimum value of data stored at 10 locations.
141. Write a program to find out maximum value of data stored at 10 locations.
142. Write a program to short out the maximum and minimum from a table data stored 04
locations.
143. Arrange a sequence of data in ascending order.
144. Arrange a sequence of data in descending order.
145. Evaluate E= (A+B) * (C+D)
146. Division of 8‐bit number. Write a program to divide 8‐bit number from 8‐bit number.
147. Division of 16 bit numbers.
148. A BCD number is stored in memory location 2040 in packed form. Write a program using
8085 ALP to unpack it and store in memory location 2041 and 2042. LSB should be store
first.
149. Write a program that input data from port 01 h and masks all bits except D0. Test the result
for 0. If the result is zero, then halt, if not, jump to input data from port 02.

Question Bank
Page 14

Timing Diagram and Memory Interface

150. Compare the memory mapped I/O with peripheral mapped I/O.
151. Explain data transfer techniques.
152. Explain assembler directives or pseudo instructions or dummy instruction in details.
153. Interface the following memory to 8085:
154. ROM : 2Kx 8‐bit, using 2716, starting address : 0000h
155. RAM : 2Kx 8‐bit, using 6116, starting address : 8000h.
Use absolute address decoding. Show all the control signals interfacing.
156. Design a microcomputer to obtain the following: 4K EPROM, 512 bytes static RAM, four 8‐
bit ports. using
a. Standard I/O and linear decoding.
b. Full decoding using 3 x 8 decoder.
c. Memory mapped I/O and full decoding.
157. Interface two input ports at addresses FFF0h and FFF1h and two output ports at addresses
9000h and 9001h using memory mapped I/O. Indicate the assumptions made if any.
158. Interface 8K bytes of EPROM & 4K bytes of RAM, 8 I/P devices, 8 O/P devices to a 8085
system in I/O mapped I/O. the memories are provided in 2K bytes ICs. Give the schematic
diagram with address data bus demultiplexing; indicate the decoding logic & the address
space for each.
159. Differentiate between partial decoding and absolute decoding in case of device (memory
I/O) selection. Give an example.
160. Interface 8K byte RAM and 4K byte EPROM to 8085, by absolute decoding using 74LS138
decoder. Give the memory map starting at address 0000h for EPROM.
161. Explain: i) memory mapped I/O, ii) I/O mapped or standard I/O, iii) serial I/O.
162. Draw the timing diagram of an 8085 instruction MVI M, 34h

Question Bank
Page 15
163. Draw the timing diagram for the instruction STA 1000h. Opcode of STA is 32h
7000 32
7001 00
7002 10
164. Draw the timing diagram of an 8085 Instruction LHLD 1234h
2000 2A (Opcode of LHLD)
2001 34
2002 12
165. Draw the timing diagram of an 8085 instruction XTHL.
166. Define T‐state, Machine cycle, Opcode fetch Cycle, Execute Cycle, Instruction Cycle.
167. Differentiate between Opcode Fetch cycle and Memory read cycle.
168. Mention various Machine cycle encountered by 8085 and the status of various signals
thereof.
169. Why the Address data bus goes into tristate while the CPU is reading from the memory?
170. List the instruction takes 6 T‐states in their Opcode Fetch?
171. Which is the longest instruction of 8085? Draw its timing diagram.
172. Mention the instructions those consume all five machine cycles of 8085.
173. Draw the timing diagram of MVI B, 32H and mention its difference with MVI M, 32H as far as
the timing diagram is concerned.
174. What is a timing diagram? Why it is so important?
175. Write a short note on FEO.
176. Write a delay program using single register. Calculate the delay being introduced by the
program.
177. Write a delay program using register pair. Calculate the delay being introduced by the
program.
178. Write a delay program that can introduce a delay of 1 msec. assume suitable frequency of
the clock supported by 8085.
179. Draw the timing diagram of an instruction which is in the indirect addressing mode.

Question Bank
Page 16
180. Draw the timing diagram of an instruction which is equivalent to JMP instruction.
181. Draw the timing diagram of an instruction that stores the contents of the accumulator at a
location pointed by BC pair.
182. Draw the timing diagram of an instruction that adds a specified byte to the contents of the
accumulator.
183. Draw the timing diagram of an instruction that increments the contents of the memory
location pointed by HL pair.
184. Answer the following questions with respect to the timing diagram of the following
instructions:
a. How many machine cycles are there in the instruction?
b. Mention the sequence of the machine cycles
c. How many T‐states are there in the Opcode fetch of the instruction?
d. How many machine cycles are there in the execute cycle of the instruction?
e. How many times the CPU reads the memory?
f. How many T‐states are there in the instruction?
g. If the clock frequency is 1MHz, what will be the time of execution of the instruction?
JMP, JNZ, CALL, STA, CC, RET, INX, SHLD, LHLD, HLT, MOV M,R
185. Explain with neat diagram the opcode fetch and memory read and memory write machine
cycles.
186. Define WAIT state. How it is internally generated by the CPU? What is its duration?
187. Suggest a circuit that can introduce one WAIT state in every machine cycle.
188. Suggest a circuit that can introduce two WAIT state in every machine cycle.
189. Draw the state transition diagram of 8085 with respect to WAIT state.
190. Draw the timing diagram of JPO when the condition is not satisfied.
191. Differentiate absolute and partial address decoding.
192. A circuit containing 32KB of RAM is to be an interfaced with 8085 based system, so that the
first address of RAM is at 4800h. What is the entire range of RAM address? How the address
bus is used to enable the RAMs? What address lines should be used?

Question Bank
Page 17
193. Design the interfacing system of 16K x 8 with microprocessor 8085. The available chip is 16K
x 1
194. Connect following memory IC with 8085
16 K * 8  EPROM         4 IC’s
    4 K * 8    RAM              4 IC’s
i. Perform memory mapping using partial decoding
ii. Perform memory mapping without fold back
195. Connect 2114 IC with 8085. Use suitable address.
196. Design the interfacing system of 64K x 8 with microprocessor 8085 based system. The
available chip is 64K x 1
197. Interface 2K word memory using 2142 SRAM chip. 2142 is 1024 x 4 bit SRAM, with output
enable. Select starting address 4000h. Use decoder circuit to select memory chips.
198. Interface 8K bytes of EPROM and 8K bytes of RAM to 8085.
199. Interface 6K X 8 memory to 8085 using 2K X 8 memory chips. Give the address range of each
chip used.
200. Interface 2KX8 memory chip to 8085. Show all necessary connections. Use minimum
hardware for the same. Specify the addresses under use.
201. What do you folding back of Memory? How this can be avoided?
202. What are shadows of memory? Why they are generated? How they can be removed?
203. What do you mean by ‘Hardwired Decoding chip select and Decoder decoding chip select?
Give examples of each.
204. Describe the Minimum System with neat diagram.
205. What is ‘Bus Contention’? How it can be avoided?
206. Differentiate between linear select decoding and absolute decoding. Mention their relative
merits and demerits.
207. A particular microprocessor has 10 bit address bus. (i) How many memory locations it can
access? (ii) Write down the highest address, (iii) Using 256 byte memory blocks design a
decoder logic for above memory requirement.

Question Bank
Page 18
208. Explain the basic concept of memory interfacing and draw the memory write cycle.
209. What parameters are to be considered while selecting a memory chip for interfacing?
210. Given a memory with a 14 bit address and 8 bit word size. (i) How many bytes can be stored
in this memory? (ii) If this memory were constructed from 1KX1 bit RAMs, how many such
memory chips would be required? (iii) How many bits will be required for chip select?
211. Define Memory Map.
212. Interface 1K X 8 memory chips. Give the address range of each chip used.
213. The following memory devices are to be interfaced to 8085: (i) 2 K EPROM, (ii) 2K RAM. The
EPROM location address should start from location 0000H and RAM from location 4000 H.
Draw the complete interfacing diagram. Use minimum hardware.
214. Interface 16K X 8 EPROM memory to 8085. The available memory chip is 4K X 4. The address
should start from 0000H onwards. Give detailed interfacing diagram and address range for
each chip used.
215. It is required to connect following memory devices to 8085 CPU system bus:
4K of EPROM (2732) starting address 0000H   : 1 No.
Followed by this 2K of SRAM (6116) : 2 Nos.
256 bytes of RWM starting address 2000H : 1 No.
2K of SRAM (6116) starting address 2800H   : 1 No.

Use a decoder fro chip select logic and you may use additional gates if required. Use
exhaustive decoding. Draw the memory map and logic diagram of the system.
216. Interface an 8085 CPU with a 2K X 8 ROM chip and two 1K X 8 RAM chips such that the
following address map is realized:
ROM Chip : Starting address – 0800H
1st
RAM chip : Starting address – 1000H
2nd
217. Design an 8085 based minimum chip configuration system for the following specifications

Question Bank
Page 19
256 x 8 bit RAM ‐ 2000H onwards
2K x 8 bit EPROM ‐ 0000h onwards
218. Design an interface arrangement to map a
a. 1024 x 8 ROM in address space 0000h to 03FFh
b. 2048 x 8 RAM in 0800H to 0FFFH
c. Output port in address space 1000H to 2000H
d. Input port in 3000H to 4000H

Interrupts

219. Explain in detail the interrupt system of 8085.
220. Design and explain a scheme to interrupt on INTR of 8085.
221. Indicate all the pins of 8085 through which the processor can be interrupted. In respect of
each of these pins describe how the processor obtains the starting address of the interrupt
service routine.
222. What is meant by priority interrupts? Explain the operation of different interrupts available
in 8085, with the help of circuit diagram.
223. How is the device priority determined in hardware polling? Explain.
224. Discuss the instructions related to interrupts of 8085.
225. Mention the functions of RIM and SIM.
226. Explain various I/O techniques supported by 8085.
227. Mention the desirable features of PID
228. Differentiate between Memory mapped I/O and I/O mapped I/O.
229. Using Status check program controlled I/O input 256 bytes of data and store them at
locations starting from 9000H. Draw the interfacing diagram and write necessary program
for the same.

Question Bank
Page 20
230. Using Status check program controlled I/O output 256 bytes of data stored at locations
starting from 9000H. Draw the interfacing diagram and write necessary program for the
same.
231. Repeat problem No. 24 with a delay of at least 1 msec in between two consecutive bytes.
232. Explain timing diagram for inputting and outputting of data using handshake.
233. What are the various techniques of addressing the I/O ports. Make a comparison between
them.
234. Distinguish between: i) Vectored and non vectored interrupt, ii) Maskable and non maskable
interrupt, iii) Internal and external interrupt, iv) Software and hardware interrupt.
235. Explain interrupt driven I/O technique. How 8085 responds to INTR interrupt?
236. What is an interrupt? Why it is required?
237. Discuss the interrupt structure of 8085.
238. Differentiate between hardware and Software interrupt
239. Differentiate between Maskable and Non‐Maskable interrupt.
240. Draw and explain the basic timings characteristics of hardware interrupt of 8085.
241. Write an initialization program to disable RST 7.5 and enable RST 5.5 and RST 7.5
242. After the execution of RIM instruction, the contents of the Accumulator is found to be 4CH.
your comments on the result.
243. Write an ALP to count the number of times RST 6.5 interrupt has occurred and display the
count in BCD at 8‐LEDs connected at memory location 3000H.
244. Write an ALP to reverse a block of 16 bytes residing at locations starting from 0900H
whenever an RST 6.5 interrupt occur.
245. Write an ALP to output a train of square waves having a frequency of 1 KHz through SOD
pin.
246. Write an ALP to output a train of rectangular pulses having a frequency of 1 KHz and Duty
Cycle 70%, through SOD pin.
247. Write an ALP to output a train of 256 rectangular pulses having a frequency of 1 KHz and
Duty Cycle 70%, through SOD pin.

Question Bank
Page 21
248. Write an ALP to output a byte residing at 9000H serially through SOD pin. Allow a delay of 1
msec as the bit interval.
249. Write an ALP to input a byte serially through SID pin. Assume a delay of 1 msec as the bit
interval. Convert the serial bit pattern into a parallel byte and store the byte at 9000H.
250. Assume the microprocessor is completing an RST 7.5 interrupt request, check to see if RST
6.5 is pending, enable RST 6.5 without affecting any other interrupts; otherwise, return to
the min program.
251. Design a 1‐hour real time clock using 50Hz power line as an interrupt source. The displays
are to be mad at the ports and must be in BCD.
252. Design a 24‐hour real time clock using 50Hz power line as an interrupt source. The displays
are to be mad at the ports and must be in BCD.
253. Implement a breakpoint facility at RST 5 for user. When the user writes RST 5 in the
program, the program should be interrupted at the instruction RST 5, display the content of
the accumulator and the flags when Hex key A is pressed and exit the break point routine
and continue execution when Hex key ‘0’ (zero) is pressed
254. Discuss the instructions related to interrupts of 8085.
255. Mention the functions of RIM and SIM.
256. Explain various I/O techniques supported by 8085.
257. Mention the desirable features of PID
258. Differentiate between Memory mapped I/O and I/O mapped I/O.
259. Using Status check program controlled I/O input 256 bytes of data and store them at
locations starting from 9000H. Draw the interfacing diagram and write necessary program
for the same.
260. Using Status check program controlled I/O output 256 bytes of data stored at locations
starting from 9000H. Draw the interfacing diagram and write necessary program for the
same.
261. Explain timing diagram for inputting and outputting of data using handshake.
262. What are the various techniques of addressing the I/O ports. Make a comparison between

Question Bank
Page 22
them.
263. Write an ALP to reverse a block of 16 bytes residing at locations starting from 0900H
whenever an RST 6.5 interrupt occur.
264. Write an ALP to count the number of times RST 6.5 interrupt has occurred and display the
count in BCD at 8‐LEDs connected at memory location 3000H.
265. Write an ALP to output a train of square waves having a frequency of 1 KHz through SOD pin
266. Write an ALP to output a byte residing at 9000H serially through SOD pin. Allow a delay of 1
msec as the bit interval.
267. Write an ALP to input a byte serially through SID pin. Assume a delay of 1 msec as the bit
interval. Convert the serial bit pattern into a parallel byte and store the byte at 9000H.

Interfacing of peripherals and applications.

268. Initialize port A as input port and port B as output port in such a way that port a should in
the handshake mode and port B as simple I/O mode for the 8155.
269. Write a program to read the status of 8 switches connected to port A and display the status
of switches at the LED’s connected to port B.
270. Mention the important features of 8155 / 8156.
271. What is the difference between 8155 & 8156?
272. With neat diagram explain the architecture of 8155 / 8156.
273. Discuss the utility of Port C in 8155 / 8156.
274. Discuss, with example, the generation of addresses of the various ports and registers of
8155 / 8156.
275. Explain the timer operation of 8155 / 8156.
276. Mention the function of the bit ‘INTR TIMER’ in the status registers of 8155.
277. Discuss the start and stop operation of timer I 8155 / 8156.

Question Bank
Page 23
278. Discuss various modes of operation of the ports of 8155 / 8156.
279. Discuss various modes of operation of the timer 8155 / 8156 with necessary signal.
280. Draw the detail decoding diagram to achieve the address of Port A of 8155 / 8156 as 91H.
Under this situation, mention the addresses of other ports and registers in 8155 / 8156.
281. Mention the utility of Port C in 8155 / 8156.
282. Design a square wave generator of frequency 2 KHz using 8155 timer.
283. Write initialization instructions to program Port A as output port and Port B as input Port for
the 8755
284. Write initialization instructions to program Port B as output port and Port A as input Port for
the 8755
285. Write initialization instructions to program Port B in such a way that the upper nibble (PB7 –
PB4) be declared as input and upper nibble (PB3 – PB0) be declared as output for the 8755
286. Write initialization instructions to program Port A in such a way that the alternate bits be
declared as i/p and o/p alternately starting from MSB for the 8755.
287. 4 switches are connected across PA7 – PA4 and 4 LEDs are connected across PA3 – PA0. Write
a program to read the status of the switches and to display the status at the LEDs. For the
8755.
288. Explain the operation of 8255 PPI chip with its internal block schematic. Explain its mode 0,
mode 1 and BSR modes.
289. Explain the features of Programmable Peripheral Interface 8255.
290. Draw and explain the block diagram of the Programmable Peripheral Interface 8255.
Or explain the architecture of the Programmable Peripheral Interface 8255.
291. Explain the modes of operation supported by the Programmable Peripheral Interface 8255.
292. Explain the Bit Set Reset mode of Programmable Peripheral Interface 8255.
293. Explain in details the parallel Input – Output mode of 8255 PPI.
294. What is the mode and Input – Output configuration for ports A, B and C of an 8255 PPI after
its control word register is loaded with 54H.
295. Describe the mode 0, mode 1 and mode 2 input – output operation of the 8255 PPI.

Question Bank
Page 24
296. If Ports A, B and C of an 8255 PPI are to be configured for mode 1 operation, where the
ports A and B are Inputs and Port C as an output, what is the control word.
297. Explain how Programmable Peripheral Interface 8255 is interfaced with Microprocessor
8085.
298. Give the interfcing of 16 – bit 8255 ports are to be interfaced with Microprocessor 8086.
Assume that the address of port A is E0h.
299. A 4 x 4 matrix keyboard is to be interfaced with Microprocessor 8086. Write an ALP to
detect key closure and return the key code in register AL. The debouncing period for a key is
10ms. Use software key debouncing technique.
300. Write  a control word format and assembly instruction when the ports of 8255 are defined
as follows:
Port A as an Input port in mode 0.
Port B as an Output port in mode 0
Port CUP as an Input port and Port CLow as an Output port.
301. Write  a control word format and assembly instruction when the ports of 8255 are defined
as follows:
Port A as an Output port in mode 0.
Port B as an Output port in mode 0
Port CUP as an Output port and Port CLow  as an Input port.
302. Interface an 8255 PPI with 8086 Microprocessor at address from 60h. Interface 5 seven
segment display with 8255 PPI and write a sequence of instruction to display 1,2,3,4 and 5
over the five displays continuously. The seven segment codes for the number is available in
the look up table at address 30000h.
303. Write an assembly language program to generate 256 pulses at the rate of 50Hz. Pulse ON
time is 5msec used PC3 pin of 8255 PPI.
304. Write an ALP to generate a square wave of frequency 1 Hz on PC2 pin of 8255 having control
word register address is 93h.
305. Write an ALP to generate 256 pulses at the rate of 50 Hz. Pulse ON time is 5 msec. used PC3

Question Bank
Page 25
pin of 8255.
306. Write a short note on 8279 keyboard/display interface.
307. Explain with block diagram the 8253 timer chip and its operation.
308. Explain with block diagram the USART 8251 chip and its operation.
309. Explain how data can be transferred using 8251 USART at different baud rates. Also discuss
the features available in 8251.
310. Explain the features of 8253. Briefly explain its different modes of operation.
311. With the help of functional block diagram, explain the different features available in 8279.
312. What are the maximum and minimum frequencies that can be generated using 8155 timer
section when 8085 clock is 3 MHz?
313. Explain with diagram serial synchronous and asynchronous data formats of 8251.
314. Write a program to transmit 8 bit data through SOD pin starting with MSB. The data is
stored at address 1A00h.
315. Write an ALP to generate square wave using 8255.
316. Write & explain the mode word format, command word format & status word format of
8251.
317. Write ALP to initialize 8251 USART and receive data on polled basis given the parameters:
Baud rate factor = 64, Character length = 8 bits, No parity check and 1 stop bit. Assume port
address 50h for data and 51h for control/status.
318. Show how you would interface a keyboard to an 8085 processor using 8255. Write an ALP to
generate a key code for the key pressed.

Question Bank
Page 26
Fill in the blanks:
1. Microprocessor 8085 is a ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ bit processor.
2. Microprocessor has ‐‐‐‐‐‐‐‐‐‐‐‐ number of pins.
3. Address bus of 8085 microprocessor is of ‐‐‐‐‐‐‐‐ bits.
4. Data bus of 8085 microprocessor is of ‐‐‐‐‐‐‐‐ bits.
5. Address bus of 8086 microprocessor is of ‐‐‐‐‐‐‐‐ bits.
6. Data bus of 8086 microprocessor is of ‐‐‐‐‐‐‐‐ bits.
7. Examples of 1‐byte instruction ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
10. STA 2500H takes ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ machine cycles.
11. LDA 2500H takes ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ machine cycles.
12. MOV A, B takes ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ machine cycles.
13. LXI H 2600H takes ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ machine cycles.
14. ADI 09 takes ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ machine cycles.
15. IN 02 takes ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ machine cycles.
16. Opcode fetch cycle takes ‐‐‐‐‐‐‐‐‐‐‐‐ T‐ states.
17. Memory read cycle takes ‐‐‐‐‐‐‐‐‐‐‐‐ T‐ states.
18. Memory write cycle takes ‐‐‐‐‐‐‐‐‐‐‐‐ T‐ states.
19. There are ‐‐‐‐‐‐‐‐‐‐‐‐‐ addressing modes.
20. Differentiate between microprocessors and microcontroller in one line.
21. PUSH PSW means ‐‐‐‐‐‐‐‐‐‐‐‐‐‐
22. POP PSW means ‐‐‐‐‐‐‐‐‐‐‐‐‐
23. The function of ALE is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
24. Values of S1 and S2 in case of opcode fetch cycle is ‐‐‐‐‐‐‐‐‐‐ and ‐‐‐‐‐‐‐‐‐‐‐‐‐.
25. Values of S1 and S2 in case of memory read cycle is ‐‐‐‐‐‐‐‐‐‐ and ‐‐‐‐‐‐‐‐‐‐‐‐‐.
26. Values of S1 and S2 in case of memory write cycle is ‐‐‐‐‐‐‐‐‐‐ and ‐‐‐‐‐‐‐‐‐‐‐‐‐.

Question Bank
Page 27
27. RAM of 1K* 8 means ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
28. There are ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ opcodes in 8085.
29. An example of direct addressing mode is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
30. An example of indirect addressing mode is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
31. Examples of register addressing mode is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
32. An example of implicit addressing mode is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
33. Examples of control signals of 8085 ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
34. Give the priority order of interrupts in 8085.
35. Data transfer instructions change the status of flags. State true or false.
36. CPM M  means ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
37. The CPU of a computer comprises of ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
38. Opcode is a term used to refer ‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
39. An 8‐bit microprocessor signifies that it has ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
40. The address bus width of 64 KB of memory is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
41. DCR register can be used to decrement the contents of ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
42. A  3‐byte instruction requires ‐‐‐‐‐‐‐‐‐‐‐‐‐ fetch cycles for its execution.
43. A  2‐ byte instruction requires ‐‐‐‐‐‐‐‐‐‐‐‐‐ fetch cycles for its execution.
44. A  1‐byte instruction requires ‐‐‐‐‐‐‐‐‐‐‐‐‐ fetch cycles for its execution.
45. The term cycle stealing is used for ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
46. The instruction MOV A, B belongs to ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ addressing mode.
47. The instruction MVI A, B belongs to ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ addressing mode.
48. The instruction LXI H, 2000H belongs to ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ addressing mode.
49. The instruction LDAX D belongs to ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ addressing mode.
50. The instruction CMA belongs to ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ addressing mode.
51. Move the contents of register A to register B.
52. Move the contents of memory location 2000H to the accumulator directly.
53. In digital computers byte denotes ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
54. Load the HL pair with the address 2500H.

Question Bank
Page 28
55. Move the data 09H to the B register.
56. Complement the contents of the accumulator.
57. Complement the contents of the carry flag.
58. Rotate the contents of the accumulator by one bit to the left through carry.
59. Rotate the contents of the accumulator by one bit to the left.
60. Rotate the contents of the accumulator by one bit to the right through carry.
61. Rotate the contents of the accumulator by one bit to the right.
62. In a microprocessor based system, the address signals are sent by ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
63. In a microprocessor based system, the address bus is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
64. In a microprocessor based system, the data bus is ‐‐‐‐‐‐‐‐‐‐.
65. The basic purpose of timing and control unit is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
66. The arithmetic and logical unit is meant for ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
67. TRAP is a maskable interrupt. State true or false.
68. Subroutine is defined as ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
69. 8253 works in ‐‐‐‐‐‐‐‐‐‐‐‐‐ modes.
70. The format for BSR mode is ‐‐‐‐‐‐‐‐‐‐‐.
71. The register pair WZ can only access by a microprocessor. State true or false.
72. The address bus width of 8 KB of memory is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
73. The term operand specifies ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.
74. The clock frequency required for 8085 is ‐‐‐‐‐‐‐‐‐‐‐.
75. Store the contents of accumulator in the memory location 2500H.
76. Increment the contents of memory location 2400H by 1.
77. Increment the contents of the register B by 2.
78. Decrement the contents of memory location 2400H by 1.
79. Decrement the contents of the register C by 2.
80. The instruction XTHL signifies ‐‐‐‐‐‐‐‐‐‐‐.
81. The instruction SPHL signifies ‐‐‐‐‐‐‐‐‐‐‐.
82. The instruction HLT signifies ‐‐‐‐‐‐‐‐‐‐‐‐.

Question Bank
Page 29
83. The fist microprocessor was introduced in the year ‐‐‐‐‐‐‐‐‐‐‐‐.
84. The major difference between INTEL 8080 and INTEL 8085 is ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐.

State true or false:

1. RST 7.5 IS LATCHED IN 8085.
2. After HOLD is activated, the bus control is relinquished by 8085 after the instruction is executed.
3. INTA pulses are required because INTR is having the lowest priority.
4. With encoded scan keyboard mode, the total number of keys are connected to 8279 is 128.
5. Asynchronous mode of 8251 is used for very high rate of data transfer.
6. POP D is data transfer of instruction.
7. ALE signal is required because higher order bus is multiplexed with data in 8085.
8. 'Opcode Fetch ’machine cycle is of 4t states for all instructions.
9. RST 4.5 pin causes microprocessor 8085 to go in to ‘WAIT’ state.
10. If register H=OOH, L=OIH, then by using DCX h instruction will set zero flag.
11. RST5 is a direct addressing mode type instruction.

Question Bank

Page 30

Page
30
Additional Questions
Microprocessor 8085

01. Draw and explain architecture of microprocessor 8085.
02. Explain flag register of microprocessor 8085, explain with suitable example.
03. Draw and explain register model of microprocessor 8085.
04. What is addressing modes, explain addressing modes with suitable examples.
05. Explain following instruction with their number of bytes, addressing modes and flags
(a) ANA M
(b) CPI 67h
(c) STA 2000h
(d) CALL Addr
(e) RC Addr
(f) XTHL
(g) PCHL
(h) IN 56h
(i) DCX H
(j) LDAX D
(k) SIM
(l) SHLD 1000
06. Write an ALP to add 16 bit data 1234 and 5678 using ADD and DAD Opcode.
07. Write an ALP to exchange contents of memory location 2000h and 2001h using Direct
addressing mode and Indirect addressing mode.
08. Write an ALP to add series of 10 bytes present in the memory location from 1000h
09. Write an ALP to transfer 100 bytes from the memory location 1000h to 2000h.
10. Write an ALP to get 100 bytes from the memory location 1000h and arrange them in the
reverse order from 2000h.
11. Write an ALP to find larges t byte from the 10 bytes present in the memory location 1000h and
put the largest byte in the memory location at 2000h.
12. Write an ALP to find smallest byte from the 10 bytes present in the memory location 1000h
and put the smallest byte in the memory location at 2000h.
13. Write an ALP to convert BCD number present in the register B to the Two ASCII numbers and
put the result in the memory location at 2000h and 2001h.
14. Write an ALP to clear 100 memory locations from 7000h.
15. Write an ALP to enter 00, 01, 02, 03, ….98, 99 in the memory location from 7000h.
16. Write an ALP to enter 00, 01, 02, 03, ….FE, FF in the memory location from 7000h.

Question Bank

Page 31

Page
31
17. Write an ALP to enter 00, 11, 22, 33, ….EE, FF in the memory location from 7000h.
18. Write an ALP to add positive numbers only from the 10 bytes present in the memory location
8000h.
19. Write an ALP to count even and odd numbers from the 10 bytes present in the memory
location from 8000h. Put the even count in register H and odd count in register L.
20. Write an ALP to add negative numbers only from the 10 bytes present in the memory location
from 2000h
21. Write an ALP to count positive and negative number from the 10 bytes present in the memory
location from 2000h. Put the positive and negative count in 2001 and 2002 respectively.
22. Write a subroutine to find squares of BCD numbers 0 to 9 and put the result in the memory
location from 3000h
23. Write a subroutine to find average of two numbers present in the memory location at 4000h
and 4001h and put the result in the memory location at 4002h.
24. Write an ALP to multiply two 8 bit numbers 10 and 67h and put the result in the memory
location at 4500h and 4501h.
25. Write an ALP to find two’s complement of 8 bit data 12h and put the result in the register D.
26. Write an ALP to convert 8 bit decimal number/ BCD number to the binary and put te result in
the register D.
27. Write an ALP to convert binary number present in the memory location at 2000h into
decimal/BCD and put the result in register D.
28. Give an instruction reset 3 MSB’s and two LSB’s of register B without affecting other bits.
29. Give an instruction to set 3 MSB’s and two LSB’s of register B without affecting other bits.
30. Give an instruction to complement 3 MSB’s and two LSB’s of register B without affecting other
bits.
31. Give an instruction to check bit D3 of register D.
32. Write an ALP to add series of 10 BCD numbers present in the memory location from 6500h and
put the result at the end of the block.
33. Explain following registers of microprocessor 8085 with their importance.

Question Bank

Page 32

Page
32
(a) Stack Pointer (SP)
(b) Program Counter (PC)
(c) Accumulator (A)
(d) Flag Register.
(e) Temporary register W and Z.
(f) Increment / decrement latch
34. Explain what is subroutine? Also explain nested subroutine with example.
35. Give an instruction to enable interrupt RST 5.5 and mask other interrupt.
36. Write instruction to disable all interrupts and send logic 1 on SOD pin.
37. After execution of instruction RIM accumulator contains 4Bh explain the accumulator
contents.
38. Write a program to load number 35h in register B and then 39 in register C. subtract 39h from
35h and display the result at output port 1.
39. Write an ALP to load 9Bh and A7 in register D and E respectively, and add the numbers. If the
sum is greater than FFh, display 01 at output port 0, otherwise display the sum.
40. Write a program to output contents of register B LSB to MSB on the SOD pin.
41. Write an ALP to output square wave of 1 KHz frequency on the SOD pin of 8085 for 5 second,
operating frequency of 8085 is 2 MHz.
42. Write an ALP to count number of 1’s in the contents of register D and store the count value in
register B.
43. What do you folding back of Memory? How this can be avoided?
44. What are shadows of memory? Why they are generated? How they can be removed?
45. What do you mean by ‘Hardwired Decoding chip select and Decoder decoding chip select?
Give examples of each.
46. Describe the Minimum System with neat diagram.
47. What is ‘Bus Contention’? How it can be avoided?
48. Differentiate between Linear select decoding and Absolute decoding. Mention their relative
merits and demerits.
49. A particular microprocessor has 10 bit address bus. (i) How many memory locations it can
access? (ii) Write down the highest address, (iii) Using 256 byte memory blocks design a
decoder logic for above memory requirement.

Question Bank

Page 33

Page
33
50. Explain the basic concept of memory interfacing and draw the memory write cycle.
51. What parameters are to be considered while selecting a memory chip for interfacing?
52. Given a memory with a 14 bit address and 8 bit word size. (i) How many bytes can be stored in
this memory? (ii) If this memory were constructed from 1KX1 bit RAMs, how many such
memory chips would be required? (iii) How many bits will be required for chip select?
53. Define Memory Map.
54. Interface 1K X 8 memory chips. Give the address range of each chip used.
55. The following memory devices are to be interfaced to 8085: (i) 2 K EPROM, (ii) 2K RAM. The
EPROM location address should start from location 0000H and RAM from location 4000 H.
Draw the complete interfacing diagram. Use minimum hardware.
56. Interface 16K X 8 EPROM memory to 8085. The available memory chip is 4K X 4. The address
should start from 0000H onwards. Give detailed interfacing diagram and address range for
each chip used.
57. Interface an 8085 CPU with a 2K X 8 ROM chip and two 1K X 8 RAM chips such that the
following address map is realized:
ROM Chip : Starting address – 0800H
1st
2nd
58. It is required to connect following memory devices to 8085 CPU system bus:
Followed by this 2K of SRAM (6116) : 2 Nos.
256 bytes of RWM starting address 2000H : 1 No.
2K of SRAM (6116) starting address 2800H   : 1 No.
Use a decoder fro chip select logic and you may use additional gates if required. Use
exhaustive decoding. Draw the memory map and logic diagram of the system.

Question Bank Microprocessor 8085

More Related Content

What's hot

Similar to Question Bank Microprocessor 8085

More from Nilesh Bhaskarrao Bahadure

Recently uploaded

Question Bank Microprocessor 8085