USPTO Linear Bit Counting Implementations
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The document is a patent application publication for linear bit counting implementations. It describes methods, systems and computer programs for counting set and unset bits in data words or streams. The operations are bounded by the number of bits counted and can be used to determine if further processing is required on the data stream. Pseudocode is provided in Figures 2 and 3 describing algorithms for counting set and unset bits respectively in a data value in a linear fashion.
![US 2011/0238717 Al Sep. 29, 2011
1
LINEAR BIT COUNTING Pat. No. 5,682,405 "Ones Density Monitor" to Smith: 175+
IMPLEMENTATIONS 1-75 consecutive zeroes in the definition ofcarrier loss as well
as circuitry for detecting when at least four of thirty-two bits
TECHNICAL FIELD AND INDUSTRIAL are set to indicate carrier on line status or the lost carrier reset
APPLICABILITY OF THE INVENTION flag).
[0001] This invention relates generally to methods, com-
SUMMARY OF THE INVENTION
puterprogram products and apparata for counting the number
of set or unset bits in words within data processing systems. [0009] As a consequence of the preceding considerations,
the motivation for the present invention is to provide alterna-
BACKGROUND OF THE INVENTION tives for achieving linear or better performance in counting
the number of set and unset bits without costing additional or
[0002] Repeatedly counting the number of set bits is
complicated hardware while minimizing the repetitions nec-
required in graphics and cryptography operations. Known
essary in a variety of applications. Each of the three imple-
methods for counting these bits include
mentations of the present invention described in more detail
[0003] checking each bit in turn, keeping a running total
later model the following pseudocode:
of the number of set bits found by incrementing a
[0010] a) initializing a return value bit counter variable to
counter when the checked bit is a 'I',
the maximum number of bits to be counted or zero; and
[0004] clearing the least significant set bit of the word
[0011] b) while all bits in the value being counted are not
using x=x & (x-I) where' &' signifies the logical AND
lor 0, repeating the following operations bl-b2:
operation while keeping a count of the number of times
that a set bit has been cleared until the word is all zeros [0012] b I) setting the value being counted to the result
after which the count is returned, of ORing or ANDing it with itself and one greater or
less than itself; and
[0005] using a lookup table to count bits in part of the
word, summing the results from the individual parts and [0013] b2) decrementing or incrementing by I the
return value bit counter variable, whereby the result-
[0006] generating intermediate words by masking and
ing return value bit counter variable represents the
shifting, summing the intermediate words into deriva-
number of set/lor unset/O bits in the data word.
tive word fields representing the sum ofa group ofbits in
the word and summing the fields of the derivative word [0014] The advantages of the present invention are even
with shift, add and mask operations whereby the result- more evident in three types of environments:
ing sum value represents the number of set bits in the [0015] limited code space
data word [0016] limited data space and
with the best performing of the above methods using shift [0017] limited compute time.
operations (see colunm I, line 10 through column 2, line 35 of Code space advantages are clear when the disclosed methods,
U.S. Pat. No. 6,516,330 BI "Counting Set Bits in Data systems, apparata and computer program products are com-
Words" to Hicks et aI, hereinafter referred to as Hicks). Shift- pared to routines/implementations using if-then-else or
ing is also taught in U.S. Pat. No. 4,486,848 "Microprocessor switch-case statement(s) for counting the number of set/l or
Parallel Additive Execution of a Computer Count Ones unset/O bits in any 32 bit number, for example. Since it is very
Instruction" to Kaminski (see colunm I, lines 40-55). common for routines to use more than one local variable for
[0007] In addition to Hicks, U.S. Pat. No. 5,717,616 "Com- computation and returning the results of its computation, the
puter Hardware Instruction and Method for Computing Popu- use of only one local variable in each disclosed routine rep-
1ation Counts" to Morris and U.S. Pat. No. 5,734,599 "Per- resents the advantage in data space. The advantage of the
forming a Population Count Using Multiplication" to Lee et disclosed implementations in compute time can be deter-
al (hereinafter Lee) also identify counting the number ofIs as mined by examining the maximum number of comparison
useful for many types of algorithms especially cryptographic operations (normally performed by one computer instruction)
analysis (see Morris colunm I, line 10 through colunm 3, line between the disclosed approaches and an if-then-else or
5 and Lee column I, line 5 through column 2, line 40). Morris switch-case statement approach, 32 versus 4294967296. In
further presents the need in the industry for a new apparatus short, the inventions are most significant in environments
and method that can be implemented conveniently resulting where time and space efficiencies are critical and/or resource
in greater CPU design flexibility and faster computation than usage must be minimized.
prior art methods while Lee suggests the desirability of alter-
nate ways to efficiently perform such calculations with a BRIEF DESCRIPTION OF THE
minimum ofhardware. A circuit with a substantially reduced DRAWINGS/FIGURES
size is also taught as an improvement in U.S. Pat. No. 4,607,
176 "Tally Cell Circuit" to Burrows et al (see column I, line [0018] Preferred embodiments ofthe invention will now be
50 through colunm 2, line 10). described, by way of example, with reference to the accom-
[0008] Though the above approaches identify set bit count- panying drawings in which:
ing hardware and performance requirements, the expense and [0019] FIG. 1 is a block diagram of a data processing sys-
complexity ofthe shifters, multipliers and parallel circuitry in tem.
the prior art may provide little if any benefits in transmission [0020] FIG. 2 is a flowchart describing the operation ofthe
or other applications that count the number of unset or zero first preferred embodiment.
bits in data characterized by a significantly smaller number of [0021] FIG. 3 is a flowchart describing the operation ofthe
differing values (e.g. either heavily or sparsely populated as in second preferred embodiment.
the discussion of the ones density requirement of Tl digital [0022] FIG. 4 is a flowchart describing the operation ofthe
signals in column I, line 45 through column 2, line 45 of U.S. third preferred embodiment.](https://image.slidesharecdn.com/us20110238717ocrd-120217090621-phpapp02/85/USPTO-Linear-Bit-Counting-Implementations-7-320.jpg)
![US 2011/0238717 Al Sep. 29, 2011
2
[0023] FIG. 5 is a flowchart describing the operation of all instructions read from signal-bearing media storage 300 and/
three third preferred embodiments. or network are then implemented to process the input word
according to a method, system, computer program product or
DETAILED DESCRIPTION OF THE PREFERRED apparatus embodying the invention whereby the resulting
EMBODIMENTS sum value indicating the number of set or unset bits is output.
Though the present invention may be used to count the num-
[0024] The present invention can be implemented as a
ber of ones and zeros in various applications, the better than
method, computer program product and/or apparatus by soft-
linear performance of three embodiments is preferred:
ware configured to run in a generally available data process-
[0032] I. counting the ones in a heavily populated value,
ing system as illustrated in FIG. 1. Data processing system 10
such as 011,
includes processor 100 attached via system bus 600 to storage
[0033] 2. counting the zeros in a sparsely populated
300, input devices 200, output devices 400 and I/O devices
value, such as 001 and
500.
[0034] 3. counting the zeros in a heavily populated value,
[0025] Processor 100 executes a program (113) of instruc-
such as 011.
tions from memory 110 such as random access memory
(RAM) 112 and/or read only memory (ROM) 111. Registers The series ofoperations performed by the processor in imple-
120, arithmetic logic unit (ALU) 130 and instruction/pro- menting these three embodiments is defined by Java and
gram counter/decoder 140 are also commonly used to imple- C/C++ program listings comparable to the flowchart of FIG.
ment any appropriate processor available from a number of 5. It will be appreciated, however, that the actual instruction
vendors (PowerPC, 80x86, Pentium, etc.). Processor logic set stored may be other lower or higher level code where the
100 enables the determination of the number of set and/or value being counted has different values or is larger or smaller
unset bits in a data word through software embodiments ofthe than three bits.
invention that may be supplied separately, as an element of
the program code for a specific application in a processing Preferred Embodiment I
system or otherwise, for loading in the processor in a known [0035] Counting the ones in a heavily populated value, such
manner. The processor may also be supplied preconfigured as 011:
with software performing invention functions. Invention
functions can also be implemented by control circuitry
through the use oflogic gates, programmable logic devices or
other hardware components in lieu of a processor-based sys- Java CIC++
tem. public int Ibc1_(int val) unsigned int Ibc1_uint(unsigned int
[0026] Storage 300 could comprise a number of individual val)
volatile or non-volatile memory modules (hard disk 310, {
floppy drive 320, FLASH drive 330, PCMCIA 340, CD 350, int be = 3; lUlsigned int bc=3;
while (val!~ Oxll1) II loop while (val !~ Ox111) II loop
DVD 360, Blu-ray 370, SD/MMC 380) that store segments of begin begin
operating system and application software (i.e. programs and { {
data) that will be swapped into and ran on processor 100 in vall~ (val + 1); val I~ (val + 1);
whole or in part through bus 600. bc--; bc--;
} }
[0027] Output devices 400 could be a device for presenting return be; return be:
data to the user, such as monitor 410, speaker 420 and/or
printer 430.
[0028] Input devices 200 could be a device for presenting
data to processing system 10 including, but not limited to FIG. 2 offers a flow chart oflbcl_/lbcl_uint. After Start 700,
mouse 210, keyboard 220, microphone 230 and camera 240. the return value bit counter (bc) is initialized to the maximum
[0029] I/O devices 500 allows for locally or remotely number of bits to be counted at box 710. Control flow then
exchanging information with data processing system 10 passes to decision diamond 720, where the program continues
through universal serial bus (USB) 560, Bluetooth 570, Eth- to box 730 if any bit in the value being counted is zero;
ernet 510, RS-232 520 and RJ-II 550 as well as IEEE 802.11 otherwise, the function/routine stops at 750 with the result in
530 and IEEE 1394 540. the return value bit counter. When control flow passes to box
730, the value being counted is set to the result of ORing it
[0030] While a specific hardware configuration is given,
with itselfand one greater than itself. Progressing to box 740,
the inventions described could in general be practiced using
the return value bit counter is decremented by one before
any hardware configuration that allows counting the number
directing control flow to the beginning ofthe loop at decision
of set and unset bits in data words. As will be explained,
diamond 720. Starting with val=OII, a table ofvalues for each
aspects ofthe preferred embodiments pertain to specific steps
iteration through the loop further demonstrates the perfor-
implementable on computer systems such as through a com-
mance of this preferred embodiment:
puter program product/function delivered via a variety of
signal-bearing media including storage 300 as well as
through a wired and/or wireless network (e.g. Ethernet 510,
telephone 550, Wi-Fi 530, etc.). Such signal-bearing, when loop # val at loop begin be at loop begin
carrying computer-readable instructions that direct the func-
tions of the present invention, represent alternative embodi- 1 all ~ 3 3
2 111 ~ 7 2
ments of the present invention.
[0031] When the number of set or unset bits in a word are to
be counted, the word is supplied to a register 120 by the That the loop is entered only once to count the two set bits
instruction/program counter/decoder 140. Successive makes its efficiency clear, especially when other inventions](https://image.slidesharecdn.com/us20110238717ocrd-120217090621-phpapp02/85/USPTO-Linear-Bit-Counting-Implementations-8-320.jpg)
![US 2011/0238717 Al Sep. 29, 2011
3
may enter a loop for each bit or at least each unset bit (i.e.
three or two times, respectively, instead of once). -continued
Java CIC++
Preferred Embodiment 2
vall~ (val + 1); val I~ (val + 1);
bc++; bc++;
[0036] Counting the zeros in a sparsely populated value, } }
such as 001: return be; return be;
FIG. 4 offers a flow chart oflbcO and IbcOuint.After Start 900,
Java CIC++
the return value bit counter (be) is initialized to zero at box
public int IbcO_(int val) unsigned int IbcO_uint(unsigned int 910. Control flow then passes to decision diamond 920, where
val) the program continues to box 930 if any bit in the value being
{
int be = 3; lUlsigned int be = 3;
counted is zero; otherwise, the function/routine stops at 950
while (val> 0) II loop begin while (val> 0) II loop begin with the result in the return value bit counter. When control
{ { flow passes to box 930, the value being counted is set to the
val &~ (val- 1); val &~ (val- 1); result of ORing it with itself and one greater than itself.
bc--; bc--;
} }
Progressing to box 940, the return value bit counter is incre-
return be; return be; mented by one before directing control flow to the beginning
ofthe loop at decision diamond 920. Starting with val=OII, a
table of values for each iteration through the loop further
demonstrates the performance ofthis preferred embodiment:
FIG. 3 offers a flow chart oflbcO_ and IbcO_unit. After Start
800, the return value bit counter (bc) is initialized to the
maximum number of bits to be counted at box 810. Control
flow then passes to decision diamond 820, where the program loop # val at loop begin be at loop begin
continues to box 830 ifany bits in the value being counted are 1 all ~ 3 a
one; otherwise, the function/routine stops at 850 with the 2 111 ~ 7 1
result in the return value bit counter. When control flow passes
to box 830, the value being counted is set to the result of
ANDing it with itself and one less than itself. Progressing to That the loop is entered once to count the only unset bit makes
box 840, the return value bit counter is decremented by one its efficiency clear, especially when other inventions may
before directing control flow to the beginning of the loop at enter a loop for each bit or at least each set bit (i.e. three or two
decision diamond 820. Starting with val=OOI, a table of val- times, respectively, instead of once).
ues for each iteration through the loop further demonstrates [0038] While three specific preferred embodiments of the
the performance of this preferred embodiment: present linear bit counting invention have been described in
detail as associated with logical components and controlled
sequences for exerting sequential information manipulation
and control within such elements, the disclosure of the
loop # val at loop begin be at loop begin present invention is intended to be illustrative and not limit-
ing. Though implementable by microprogrammable control
1 001 ~ 1 3
2 a 2
or derived from timing chains and discrete control logics, it
will be understood by those skilled in the art that the basic
principles of the invention may be altered in form and detail
That the loop is entered only once to count the two unset bits without departing from the spirit and scope of the appended
makes its efficiency clear, especially when other inventions claims.
may enter a loop for each bit or at least each unset bit (i.e. The embodiments of the invention in which an exclusive
three or two times, respectively, instead of once). property or privilege is claimed are defined as follows:
1. A method ofcounting the number of set! I bits in an n-bit
Preferred Embodiment 3 data word in a data processing system comprising:
a) initializing a return value bit counter variable to the
[0037] Counting the zeros in a heavily populated value, maximum number of bits to be counted; and
such as 011: b) while all bits in the value being counted are not I,
repeating the following operations bl-b2:
b I) setting the value being counted to the result ofORing
it with itself and one greater than itself; and
Java CIC++ b2) decrementing by I the return value bit counter vari-
public int IbcO(int val) unsigned int IbcOuint(unsigned int able, whereby the resulting return value bit counter
val) variable represents the number of set! I bits in the data
{ word.
int be = 0; lUlsigned int be = 0;
while (val!~ Ox111) II loop while (val !~ Oxll1) II loop
2. A method of counting the number ofunset!O bits in an
begin begin n-bit data word in a data processing system comprising:
{ { c) initializing a return value bit counter variable to the
maximum number of bits to be counted; and](https://image.slidesharecdn.com/us20110238717ocrd-120217090621-phpapp02/85/USPTO-Linear-Bit-Counting-Implementations-9-320.jpg)
USPTO Linear Bit Counting Implementations
- 1. 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 us 20110238717Al (19) United States (12) Patent Application Publication (10) Pub. No.: US 201110238717 Al Bell (43) Pub. Date: Sep. 29, 2011 (54) LINEAR BIT COUNTING (52) U.S. Cl. 7081210 IMPLEMENTATIONS (57) ABSTRACT (75) Inventor: Meltin Bell, Alexandria, VA (US) Counting the number of set and unset bits in an n-bit data word or stream of data is most efficient in applications where the data can be characterized as sparsely populated (bits (73) Assignee: Meltin Bell, Alexandria, VA (US) mostly or all unset/O) and/or heavily populated (bits mostly or all set/I). In these populations, processing can be linearly (21) Appl. No.: 121749,154 proportional to the smaller number of differing bit values resulting in compute time and resource savings. In any popu- (22) Filed: Mar. 29, 2010 lation, the operations of the bit counting methods, systems, apparata and computer program products described are bounded by the number of bits counted in the data word/ Publication Classification stream. The described operations can be used for determining (51) Int. Cl. whether further processing of the data stream is required as G06F 7/00 (2006.01) well as the extent of that processing. Data Processing System 10 Processor 100 Storage 300 Memory 110 Hard Disk 31.0 ROM 111 Floppy Drive 320 RAM 112 FLAS.H Drive 330 Program 113 PCMCI.A340 Bus 600 Registers 120 CD 350 DVD360 ALU 130 Blu-ray 370 Instruction!Prograrn SDjMMC 380 Counter/Decoder 140 Output Devices 400 Monitor 410 S.peaker 420 Printer 430 Input Devices 200 I/O Devices 500 Mouse 210 Ethernet 510 Keyboard 220 RS232520 Microph0l1e 230 IEEE 802.11530 Cameral 240 IEEE 1394540 RJ11550 USB 560 Bluetooth 570
- 2. Patent Application Publication Sep. 29, 2011 Sheet 1 of 5 US 2011/0238717 Al Data Processing System 10 Processor 100 Storage 300 Memory 110 Hard Disk 310 ROM 111 Floppy Drive 320 RAM 112 flASH Drive 330 Program 113 PCMCIA340 Bus 600 Registers 120 CD 350 DVD360 A.lU 130 Blu-rav 370 lnstruction/Prograrn SD/MMC 380 Counter/Decoder 140 Output Devices 400 Monitor 410 Speaker 420 Printer 430 Input Devices 200 I/O Devices 500 Mouse 210 Ethernet SlO Keyboard 220 RS232520 Microphone 230 IEEE 802.11530 Cameral 240 IEEE 1394540 RJ11550 USB 560 Bluetooth 570 Fig. 1
- 3. Patent Application Publication Sep. 29, 2011 Sheet 2 of 5 US 2011/0238717 Al 710 Initialize a return value bit counter to the maximum number of bits to be counted 750 Yes Set the value being 730 counted to the result of ORing it with itself and one greater than~tself 740 Decrement the return value bit cou nter by one Fig. 2 Ibel >1'
- 4. Patent Application Publication Sep. 29, 2011 Sheet 3 of 5 US 2011/0238717 Al 810 Initialize a return value bit counter to the maximum number of bits to be counted 850 Yes Set the value being 830 counted to the result of ANDing It with itself and one less than itself 840 Decrement the return value bit counter by one Fig. 3 IbeO :;<
- 5. Patent Application Publication Sep. 29, 2011 Sheet 4 of 5 US 2011/0238717 Al 900 St~ 910 Initialize a return value bit counter to zero 950 Yes Set the value being 930 counted to the result of ORing it with itself and one greater than itself 940 lncrernent the return value bit counter by one Fig. 4 IbeO, IbcOuint
- 6. Patent Application Publication Sep. 29, 2011 Sheet 5 of 5 US 2011/0238717 Al 1010 Initialize a return value bit counter variable Yes Set the value being 1030 counted to the result of ORing Of ANDing it '.,'vith lt$e·lf and (itself +/~ one) 1040 .~-_.L-_-""i !ncrerYlent or decrement the return value bit counter by one Fig, 5 Unear Bit (ounting Flowchart Template
- 7. US 2011/0238717 Al Sep. 29, 2011 1 LINEAR BIT COUNTING Pat. No. 5,682,405 "Ones Density Monitor" to Smith: 175+ IMPLEMENTATIONS 1-75 consecutive zeroes in the definition ofcarrier loss as well as circuitry for detecting when at least four of thirty-two bits TECHNICAL FIELD AND INDUSTRIAL are set to indicate carrier on line status or the lost carrier reset APPLICABILITY OF THE INVENTION flag). [0001] This invention relates generally to methods, com- SUMMARY OF THE INVENTION puterprogram products and apparata for counting the number of set or unset bits in words within data processing systems. [0009] As a consequence of the preceding considerations, the motivation for the present invention is to provide alterna- BACKGROUND OF THE INVENTION tives for achieving linear or better performance in counting the number of set and unset bits without costing additional or [0002] Repeatedly counting the number of set bits is complicated hardware while minimizing the repetitions nec- required in graphics and cryptography operations. Known essary in a variety of applications. Each of the three imple- methods for counting these bits include mentations of the present invention described in more detail [0003] checking each bit in turn, keeping a running total later model the following pseudocode: of the number of set bits found by incrementing a [0010] a) initializing a return value bit counter variable to counter when the checked bit is a 'I', the maximum number of bits to be counted or zero; and [0004] clearing the least significant set bit of the word [0011] b) while all bits in the value being counted are not using x=x & (x-I) where' &' signifies the logical AND lor 0, repeating the following operations bl-b2: operation while keeping a count of the number of times that a set bit has been cleared until the word is all zeros [0012] b I) setting the value being counted to the result after which the count is returned, of ORing or ANDing it with itself and one greater or less than itself; and [0005] using a lookup table to count bits in part of the word, summing the results from the individual parts and [0013] b2) decrementing or incrementing by I the return value bit counter variable, whereby the result- [0006] generating intermediate words by masking and ing return value bit counter variable represents the shifting, summing the intermediate words into deriva- number of set/lor unset/O bits in the data word. tive word fields representing the sum ofa group ofbits in the word and summing the fields of the derivative word [0014] The advantages of the present invention are even with shift, add and mask operations whereby the result- more evident in three types of environments: ing sum value represents the number of set bits in the [0015] limited code space data word [0016] limited data space and with the best performing of the above methods using shift [0017] limited compute time. operations (see colunm I, line 10 through column 2, line 35 of Code space advantages are clear when the disclosed methods, U.S. Pat. No. 6,516,330 BI "Counting Set Bits in Data systems, apparata and computer program products are com- Words" to Hicks et aI, hereinafter referred to as Hicks). Shift- pared to routines/implementations using if-then-else or ing is also taught in U.S. Pat. No. 4,486,848 "Microprocessor switch-case statement(s) for counting the number of set/l or Parallel Additive Execution of a Computer Count Ones unset/O bits in any 32 bit number, for example. Since it is very Instruction" to Kaminski (see colunm I, lines 40-55). common for routines to use more than one local variable for [0007] In addition to Hicks, U.S. Pat. No. 5,717,616 "Com- computation and returning the results of its computation, the puter Hardware Instruction and Method for Computing Popu- use of only one local variable in each disclosed routine rep- 1ation Counts" to Morris and U.S. Pat. No. 5,734,599 "Per- resents the advantage in data space. The advantage of the forming a Population Count Using Multiplication" to Lee et disclosed implementations in compute time can be deter- al (hereinafter Lee) also identify counting the number ofIs as mined by examining the maximum number of comparison useful for many types of algorithms especially cryptographic operations (normally performed by one computer instruction) analysis (see Morris colunm I, line 10 through colunm 3, line between the disclosed approaches and an if-then-else or 5 and Lee column I, line 5 through column 2, line 40). Morris switch-case statement approach, 32 versus 4294967296. In further presents the need in the industry for a new apparatus short, the inventions are most significant in environments and method that can be implemented conveniently resulting where time and space efficiencies are critical and/or resource in greater CPU design flexibility and faster computation than usage must be minimized. prior art methods while Lee suggests the desirability of alter- nate ways to efficiently perform such calculations with a BRIEF DESCRIPTION OF THE minimum ofhardware. A circuit with a substantially reduced DRAWINGS/FIGURES size is also taught as an improvement in U.S. Pat. No. 4,607, 176 "Tally Cell Circuit" to Burrows et al (see column I, line [0018] Preferred embodiments ofthe invention will now be 50 through colunm 2, line 10). described, by way of example, with reference to the accom- [0008] Though the above approaches identify set bit count- panying drawings in which: ing hardware and performance requirements, the expense and [0019] FIG. 1 is a block diagram of a data processing sys- complexity ofthe shifters, multipliers and parallel circuitry in tem. the prior art may provide little if any benefits in transmission [0020] FIG. 2 is a flowchart describing the operation ofthe or other applications that count the number of unset or zero first preferred embodiment. bits in data characterized by a significantly smaller number of [0021] FIG. 3 is a flowchart describing the operation ofthe differing values (e.g. either heavily or sparsely populated as in second preferred embodiment. the discussion of the ones density requirement of Tl digital [0022] FIG. 4 is a flowchart describing the operation ofthe signals in column I, line 45 through column 2, line 45 of U.S. third preferred embodiment.
- 8. US 2011/0238717 Al Sep. 29, 2011 2 [0023] FIG. 5 is a flowchart describing the operation of all instructions read from signal-bearing media storage 300 and/ three third preferred embodiments. or network are then implemented to process the input word according to a method, system, computer program product or DETAILED DESCRIPTION OF THE PREFERRED apparatus embodying the invention whereby the resulting EMBODIMENTS sum value indicating the number of set or unset bits is output. Though the present invention may be used to count the num- [0024] The present invention can be implemented as a ber of ones and zeros in various applications, the better than method, computer program product and/or apparatus by soft- linear performance of three embodiments is preferred: ware configured to run in a generally available data process- [0032] I. counting the ones in a heavily populated value, ing system as illustrated in FIG. 1. Data processing system 10 such as 011, includes processor 100 attached via system bus 600 to storage [0033] 2. counting the zeros in a sparsely populated 300, input devices 200, output devices 400 and I/O devices value, such as 001 and 500. [0034] 3. counting the zeros in a heavily populated value, [0025] Processor 100 executes a program (113) of instruc- such as 011. tions from memory 110 such as random access memory (RAM) 112 and/or read only memory (ROM) 111. Registers The series ofoperations performed by the processor in imple- 120, arithmetic logic unit (ALU) 130 and instruction/pro- menting these three embodiments is defined by Java and gram counter/decoder 140 are also commonly used to imple- C/C++ program listings comparable to the flowchart of FIG. ment any appropriate processor available from a number of 5. It will be appreciated, however, that the actual instruction vendors (PowerPC, 80x86, Pentium, etc.). Processor logic set stored may be other lower or higher level code where the 100 enables the determination of the number of set and/or value being counted has different values or is larger or smaller unset bits in a data word through software embodiments ofthe than three bits. invention that may be supplied separately, as an element of the program code for a specific application in a processing Preferred Embodiment I system or otherwise, for loading in the processor in a known [0035] Counting the ones in a heavily populated value, such manner. The processor may also be supplied preconfigured as 011: with software performing invention functions. Invention functions can also be implemented by control circuitry through the use oflogic gates, programmable logic devices or other hardware components in lieu of a processor-based sys- Java CIC++ tem. public int Ibc1_(int val) unsigned int Ibc1_uint(unsigned int [0026] Storage 300 could comprise a number of individual val) volatile or non-volatile memory modules (hard disk 310, { floppy drive 320, FLASH drive 330, PCMCIA 340, CD 350, int be = 3; lUlsigned int bc=3; while (val!~ Oxll1) II loop while (val !~ Ox111) II loop DVD 360, Blu-ray 370, SD/MMC 380) that store segments of begin begin operating system and application software (i.e. programs and { { data) that will be swapped into and ran on processor 100 in vall~ (val + 1); val I~ (val + 1); whole or in part through bus 600. bc--; bc--; } } [0027] Output devices 400 could be a device for presenting return be; return be: data to the user, such as monitor 410, speaker 420 and/or printer 430. [0028] Input devices 200 could be a device for presenting data to processing system 10 including, but not limited to FIG. 2 offers a flow chart oflbcl_/lbcl_uint. After Start 700, mouse 210, keyboard 220, microphone 230 and camera 240. the return value bit counter (bc) is initialized to the maximum [0029] I/O devices 500 allows for locally or remotely number of bits to be counted at box 710. Control flow then exchanging information with data processing system 10 passes to decision diamond 720, where the program continues through universal serial bus (USB) 560, Bluetooth 570, Eth- to box 730 if any bit in the value being counted is zero; ernet 510, RS-232 520 and RJ-II 550 as well as IEEE 802.11 otherwise, the function/routine stops at 750 with the result in 530 and IEEE 1394 540. the return value bit counter. When control flow passes to box 730, the value being counted is set to the result of ORing it [0030] While a specific hardware configuration is given, with itselfand one greater than itself. Progressing to box 740, the inventions described could in general be practiced using the return value bit counter is decremented by one before any hardware configuration that allows counting the number directing control flow to the beginning ofthe loop at decision of set and unset bits in data words. As will be explained, diamond 720. Starting with val=OII, a table ofvalues for each aspects ofthe preferred embodiments pertain to specific steps iteration through the loop further demonstrates the perfor- implementable on computer systems such as through a com- mance of this preferred embodiment: puter program product/function delivered via a variety of signal-bearing media including storage 300 as well as through a wired and/or wireless network (e.g. Ethernet 510, telephone 550, Wi-Fi 530, etc.). Such signal-bearing, when loop # val at loop begin be at loop begin carrying computer-readable instructions that direct the func- tions of the present invention, represent alternative embodi- 1 all ~ 3 3 2 111 ~ 7 2 ments of the present invention. [0031] When the number of set or unset bits in a word are to be counted, the word is supplied to a register 120 by the That the loop is entered only once to count the two set bits instruction/program counter/decoder 140. Successive makes its efficiency clear, especially when other inventions
- 9. US 2011/0238717 Al Sep. 29, 2011 3 may enter a loop for each bit or at least each unset bit (i.e. three or two times, respectively, instead of once). -continued Java CIC++ Preferred Embodiment 2 vall~ (val + 1); val I~ (val + 1); bc++; bc++; [0036] Counting the zeros in a sparsely populated value, } } such as 001: return be; return be; FIG. 4 offers a flow chart oflbcO and IbcOuint.After Start 900, Java CIC++ the return value bit counter (be) is initialized to zero at box public int IbcO_(int val) unsigned int IbcO_uint(unsigned int 910. Control flow then passes to decision diamond 920, where val) the program continues to box 930 if any bit in the value being { int be = 3; lUlsigned int be = 3; counted is zero; otherwise, the function/routine stops at 950 while (val> 0) II loop begin while (val> 0) II loop begin with the result in the return value bit counter. When control { { flow passes to box 930, the value being counted is set to the val &~ (val- 1); val &~ (val- 1); result of ORing it with itself and one greater than itself. bc--; bc--; } } Progressing to box 940, the return value bit counter is incre- return be; return be; mented by one before directing control flow to the beginning ofthe loop at decision diamond 920. Starting with val=OII, a table of values for each iteration through the loop further demonstrates the performance ofthis preferred embodiment: FIG. 3 offers a flow chart oflbcO_ and IbcO_unit. After Start 800, the return value bit counter (bc) is initialized to the maximum number of bits to be counted at box 810. Control flow then passes to decision diamond 820, where the program loop # val at loop begin be at loop begin continues to box 830 ifany bits in the value being counted are 1 all ~ 3 a one; otherwise, the function/routine stops at 850 with the 2 111 ~ 7 1 result in the return value bit counter. When control flow passes to box 830, the value being counted is set to the result of ANDing it with itself and one less than itself. Progressing to That the loop is entered once to count the only unset bit makes box 840, the return value bit counter is decremented by one its efficiency clear, especially when other inventions may before directing control flow to the beginning of the loop at enter a loop for each bit or at least each set bit (i.e. three or two decision diamond 820. Starting with val=OOI, a table of val- times, respectively, instead of once). ues for each iteration through the loop further demonstrates [0038] While three specific preferred embodiments of the the performance of this preferred embodiment: present linear bit counting invention have been described in detail as associated with logical components and controlled sequences for exerting sequential information manipulation and control within such elements, the disclosure of the loop # val at loop begin be at loop begin present invention is intended to be illustrative and not limit- ing. Though implementable by microprogrammable control 1 001 ~ 1 3 2 a 2 or derived from timing chains and discrete control logics, it will be understood by those skilled in the art that the basic principles of the invention may be altered in form and detail That the loop is entered only once to count the two unset bits without departing from the spirit and scope of the appended makes its efficiency clear, especially when other inventions claims. may enter a loop for each bit or at least each unset bit (i.e. The embodiments of the invention in which an exclusive three or two times, respectively, instead of once). property or privilege is claimed are defined as follows: 1. A method ofcounting the number of set! I bits in an n-bit Preferred Embodiment 3 data word in a data processing system comprising: a) initializing a return value bit counter variable to the [0037] Counting the zeros in a heavily populated value, maximum number of bits to be counted; and such as 011: b) while all bits in the value being counted are not I, repeating the following operations bl-b2: b I) setting the value being counted to the result ofORing it with itself and one greater than itself; and Java CIC++ b2) decrementing by I the return value bit counter vari- public int IbcO(int val) unsigned int IbcOuint(unsigned int able, whereby the resulting return value bit counter val) variable represents the number of set! I bits in the data { word. int be = 0; lUlsigned int be = 0; while (val!~ Ox111) II loop while (val !~ Oxll1) II loop 2. A method of counting the number ofunset!O bits in an begin begin n-bit data word in a data processing system comprising: { { c) initializing a return value bit counter variable to the maximum number of bits to be counted; and
- 10. US 2011/0238717 Al Sep. 29, 2011 4 d) while the value being counted is nonzero, repeating the 6. A data processing system, comprising: following operations b l-b2: a processor; b I) setting the value being counted to the result ofAND- storage coupled to the processor; and ing it with itself and one less than itself; and program code residing in the storage and executing on the b2) decrementing by I the return value bit counter vari- processor, able, wherein the program code configures the processor to per- form the method of claim 3. whereby the resulting return value bit counter variable repre- 7. A computer program product comprising computer pro- sents the number ofunset/O bits in the data word. gram code which, when loaded in a processor of a data pro- 3. A method of counting the number of unset/O bits in an cessing system, configures the processor to perform the steps n-bit data word in a data processing system comprising: of claim 1. e) initializing a return value bit counter variable to zero; 8. A computer program product comprising computer pro- and gram code which, when loaded in a processor of a data pro- f) while all bits in the value being counted are not I, cessing system, configures the processor to perform the steps repeating the following operations bl-b2: of claim 2. b I) setting the value being counted to the result of 0 Ring 9. A computer program product comprising computer pro- it with itself and one greater than itself; and gram code which, when loaded in a processor of a data pro- b2) incrementing by I the return value bit counter vari- cessing system, configures the processor to perform the steps able, of claim 3. whereby the resulting return value bit counter variable repre- 10. An apparatus for counting the number of set/l bits in an sents the number ofunset/O bits in the data word. n-bit data word in a data processing system comprising: means for performing the functions of claim 1. 4. A data processing system, comprising: 11. An apparatus for counting the number of unset/O bits in a processor; an n-bit data word in a data processing system comprising: storage coupled to the processor; and means for performing the functions of claim 2. program code residing in the storage and executing on the 12. An apparatus for counting the number of unset/O bits in processor, an n-bit data word in a data processing system comprising: wherein the program code configures the processor to per- means for performing the functions of claim 3. form the method of claim 1. 13. The method of claim 1, wherein n=64. 5. A data processing system, comprising: 14. The method of claim 2, wherein n=64. a processor; 15. The method of claim 3, wherein n=64. storage coupled to the processor; and 16. The method of claim 1, wherein n=128. program code residing in the storage and executing on the 17. The method of claim 2, whereinn=128. processor, 18. The method of claim 3, whereinn=128. wherein the program code configures the processor to per- form the method of claim 2. * * * * *