Vlsi 2015 2016 ieee project list-(v)_with abstract
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S3 Infotech provides summaries of 10 VLSI projects related to low-power logic circuits, level shifters, adder architectures, optical counters, modular multiplication, transaction IDs, modulo adders, DACs, median filters, and quantum-dot SRAM. The projects explore techniques like spin-based devices, dynamic voltage scaling, pipelining, and cellular automata to improve efficiency, throughput, power consumption, and process variability tolerance in VLSI design.
![S3 INFOTECH +91 988 48 48 198
# 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198.
www.s3computers.com E-Mail: info@s3computers.com
ID assignment mechanism that guarantees the issued transactions to be deadlock-free and results in
significant reduction in the number of transaction stalls issued by masters. Our experimental results
showencouragingperformance improvementscomparedwithprevious works with little hardware and
power overheads.
S3VLSI07 - ( 4+2 log n ) Delta-G Modulo-(2^ Parallel Prefix n-3) Adder via Double
Representation of Residues in [0,2]
The most popular modulus in residue number systems (RNS), next to power-of-two modulus,
are those of the form ( ). However, in RNS applications that require larger dynamic range, without
increasingthe parameter,modulusof the form( ) are gainingpopularity.Nevertheless,latencybalanced
computational channels in RNS arithmetic systems are desirable. Ripple-carry modulo-( ) adders are
realizedsimplyasone’scomplement adders, where serves as a second representation for 0. However,
the same single -bit adder realization is not possible for modulo ( ). Given that efficient parallel prefix
realizationof modulo-( ) addersexistwhose latency is compatible with similar modulo- adders, we are
motivatedtodesignlatencycompatible parallel prefix modulo-( ) adders. In this paper, we propose the
fastest of such adders, where residues in ,, can be represented also as excess-( ) encoding (i.e., , , ,
respectively).The delay and area overhead of the proposed adder with respect to the base modulo-( )
adder, is only one extra gate in the critical delay path, and at most 20% more area. In very rare cases
that bothoperandsare excess-( ),augmentingthe proposedadderwithfew extra gates leads to correct
sum. The analytical results are confirmed by synthesis via Synopsys Design Compiler.
S3VLSI08 - A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038
mm²
A 6-bitfull-binarycompactandlow-powercurrent-steering digital-to-analog converter (DAC) designed
for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit
components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-
frequencydynamiclinearity. The proposed binary structure realizes a compact DAC by eliminating the
need for additional circuits, such as thermometer decoders, and thus reduces power consumption. A
prototype 6-bit 3.1-GS/s full-binary DAC was fabricated in a 90-nm CMOS process. The DAC exhibits a
spurious-free dynamicrange of >37.2 dB up to 3.1 GS/s over the Nyquist input. The chip consumes 17.7
mW of power and occupies 0.038 mm² of core size.
S3VLSI09 - Median Filter Architecture by Accumulative Parallel Counters
The time to processeachof W/B processingblocksof a mediancalculationmethodona set of N
W-bitintegersisimprovedherebyafactor of three comparedtothe literature.Parallelismuncoveredin
blockscontainingB-bit slices are exploited by independent accumulative parallel counters so that the
medianiscalculatedfasterthananyknownpreviousmethodforanyN,W values.The improvements to
the method are discussed in the context of calculating the median for a moving set of N integers for](https://image.slidesharecdn.com/vlsi2015-2016ieeeprojectlistvwithabstract-150705073040-lva1-app6892/85/Vlsi-2015-2016-ieee-project-list-v-_with-abstract-3-320.jpg)
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Vlsi 2015 2016 ieee project list-(v)_with abstract
- 1. S3 INFOTECH +91 988 48 48 198 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: [email protected] IEEE 2015 – VLSI PROJECTS S3VLSI01 - A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits Advancedcomputingsystemsembedspintronicdevicesto improve the leakage performance of conventional CMOSsystems.Highspeed,low power,andinfiniteendurance are importantpropertiesof magnetictunnel junction(MTJ),aspintronicdevice,whichassuresitsuse inmemoriesandlogic circuits. Thispaperpresentsa PentaMTJ-basedlogicgate, which provides easy cascading, self-referencing, less voltage headroom problem in precharge sense amplifier and low area overhead contrary to existing MTJ-basedgates. PentaMTJ is used here because it provides guaranteed disturbance free reading and increasedtolerance toprocessvariationsalongwith compatibility with CMOS process. The logic gate is validated by simulation at the 45-nm technology node using a VerilogA model of the PentaMTJ. S3VLSI02 - Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits Since the minimum feature size has shrunk beyond the sub-30-nm node, power density has become the major factor in modern microprocessors. Techniques such as dynamic voltage scaling operatingdowntonear thresholdvoltagelevelsandsupportingmultiple voltage domains have become necessary to reduce dynamic as well as static power. A key component of these techniques is a level shifterthatservesdifferentvoltage domains.Thislevelshiftermust be high speed and power efficient. The proposed level shifter translates voltages ranging from 250 to 790 mV, and exhibits 42% shorter delay, 45% lower energy consumption, and 48% lower static power dissipation. In addition, the proposed level shifter exhibits symmetric rise and fall transition times with up to 12% skew at the extreme conditions over the maximum range of voltages. S3VLSI03 - Ultralow-Energy Variation-Aware Design: Adder Architecture Study Power consumption of digital systems is an important issue in nanoscale technologies and growth of process variation makes the problem more challenging. In this brief, we have analyzed the latency,energyconsumption,andeffectsof processvariationondifferentstructureswithrespectto the design structure and logic depth to propose architectures with higher throughput, lower energy consumption, and smaller performance loss caused by process variation in application-specific integratedcircuitdesign.We have exploited adders as different implementations of a processing unit, and propose architectural guidelinesforfinertechnologies in subthreshold which are applicable to any other architecture. The results show that smaller computing building blocks have better energy efficiencyandlessperformancedegradationbecause of variationeffects.Incontrast,their computation throughputwill be midorlessunlesspropersolutions,suchaspipelinedorparallel structures, are used. Therefore,ourproposedsolutionto improve the throughput loss while reducing sensitivity to process variations is using simpler elements in deep pipelined designs or massively parallel structures.
- 2. S3 INFOTECH +91 988 48 48 198 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: [email protected] S3VLSI04 - All Optical Implementationof Mach-Zehnder Interferometer Based Reversible Sequential Counters This work presents all optical reversible implementation of sequential counters using semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) switches. All the designs are implemented using minimum number of MZI switches and garbage outputs. This design ensuresimprovedoptical costsinreversible realizationof all the countercircuits.The theoretical model is simulated to verify the functionality of the circuits. Design complexity of all the proposed memory elements has been analyzed. S3VLSI05 - Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Thissystemproposesasimple andefficientMontgomerymultiplication algorithm such that the low-costandhigh-performance Montgomerymodularmultiplier can be implemented accordingly. The proposedmultiplierreceives and outputs the data with binary representation and uses only one-level carry-save adder(CSA) to avoid the carry propagation at each addition operation. This CSA is also used to perform operand precomputation and format conversion from the carry-save format to the binary representation,leadingtoa lowhardware cost andshort critical pathdelayat the expense of extraclock cycles for completing one modular multiplication. To overcome the weakness, a configurable CSA (CCSA), which could be one full-adder or two serial half-adders, is proposed to reduce the extra clock cycles for operand precomputation and format conversion by half. In addition, a mechanism that can detectandskipthe unnecessarycarry-save additionoperationsin the one-levelCCSA architecture while maintaining the short critical path delay is developed. As a result, the extra clock cycles for operand precomputation and format conversion can be hidden and high throughput can be obtained. Experimental results show that the proposed Montgomery modular multiplier can achieve higher performance andsignificant area--time product improvement when compared with previous designs. S3VLSI06 - High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols In a modern system-on-chip design, hundreds of cores and intellectual properties can be integratedintoasingle chip.Tobe suitable forhigh-performance interconnects, designers increasingly adoptadvancedinterconnectprotocolsthatsupport novel mechanisms of parallel accessing, including outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a master tags an ID to each transaction to decide in-order or out-of-order properties. However, these advanced protocols may lead to transaction deadlocks that do not occur in traditional protocols. To prevent the deadlock problem, current solutions stall suspicious transactions and in certaincases,manysuch stallscan incurseriousperformance penalty. In this brief, we propose a novel
- 3. S3 INFOTECH +91 988 48 48 198 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: [email protected] ID assignment mechanism that guarantees the issued transactions to be deadlock-free and results in significant reduction in the number of transaction stalls issued by masters. Our experimental results showencouragingperformance improvementscomparedwithprevious works with little hardware and power overheads. S3VLSI07 - ( 4+2 log n ) Delta-G Modulo-(2^ Parallel Prefix n-3) Adder via Double Representation of Residues in [0,2] The most popular modulus in residue number systems (RNS), next to power-of-two modulus, are those of the form ( ). However, in RNS applications that require larger dynamic range, without increasingthe parameter,modulusof the form( ) are gainingpopularity.Nevertheless,latencybalanced computational channels in RNS arithmetic systems are desirable. Ripple-carry modulo-( ) adders are realizedsimplyasone’scomplement adders, where serves as a second representation for 0. However, the same single -bit adder realization is not possible for modulo ( ). Given that efficient parallel prefix realizationof modulo-( ) addersexistwhose latency is compatible with similar modulo- adders, we are motivatedtodesignlatencycompatible parallel prefix modulo-( ) adders. In this paper, we propose the fastest of such adders, where residues in ,, can be represented also as excess-( ) encoding (i.e., , , , respectively).The delay and area overhead of the proposed adder with respect to the base modulo-( ) adder, is only one extra gate in the critical delay path, and at most 20% more area. In very rare cases that bothoperandsare excess-( ),augmentingthe proposedadderwithfew extra gates leads to correct sum. The analytical results are confirmed by synthesis via Synopsys Design Compiler. S3VLSI08 - A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm² A 6-bitfull-binarycompactandlow-powercurrent-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high- frequencydynamiclinearity. The proposed binary structure realizes a compact DAC by eliminating the need for additional circuits, such as thermometer decoders, and thus reduces power consumption. A prototype 6-bit 3.1-GS/s full-binary DAC was fabricated in a 90-nm CMOS process. The DAC exhibits a spurious-free dynamicrange of >37.2 dB up to 3.1 GS/s over the Nyquist input. The chip consumes 17.7 mW of power and occupies 0.038 mm² of core size. S3VLSI09 - Median Filter Architecture by Accumulative Parallel Counters The time to processeachof W/B processingblocksof a mediancalculationmethodona set of N W-bitintegersisimprovedherebyafactor of three comparedtothe literature.Parallelismuncoveredin blockscontainingB-bit slices are exploited by independent accumulative parallel counters so that the medianiscalculatedfasterthananyknownpreviousmethodforanyN,W values.The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for
- 4. S3 INFOTECH +91 988 48 48 198 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: [email protected] whicha pipelinedarchitecture isdeveloped.Anextrabenefitof smaller area for the architecture is also reported. S3VLSI10 - A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM).Thispaperpresentsthe designandsimulationof a16-bit x 32-bit SRAMwith a new structure in QCA.Since QCA is a pipeline,thisSRAMhasa highoperating speed. The 16-bit x 32-bit SRAMhas a new structure witha 32-bit widthdesignedandimplementedinQCA.Ithasthe abilityof a conventional logic SRAMthat can provide read/writeoperationsfrequentlywithminimumdelay. The 16-bit x 32-bit SRAM is generalized and an n x 16-bit x 32-bit SRAM is implemented in QCA. Novel 16-bit decoders and multiplexers(MUXs) inQCA are presentedthathave beendesignedwithaminimumnumberof majority gatesand cells.The newSRAM,decoders,andMUXs are designed,implemented, and simulated in QCA using a signal distribution network to avoid the coplanar problem of crossing wires. The QCA-based SRAMcell was compared with the SRAMcell based on CMOS. Results show that the proposed SRAMis more efficient in terms of area, complexity, clock frequency, latency, throughput, and power consumption.