diff options
| author | Kevin Newton <[email protected]> | 2022-08-23 13:41:22 -0400 |
|---|---|---|
| committer | Takashi Kokubun <[email protected]> | 2022-08-29 09:09:41 -0700 |
| commit | 54c7bc67a2d54311b77aca9233b23a9e7a1ca581 (patch) | |
| tree | 26e2da017378285c18edecd671fbeea896178768 /yjit/src/asm/arm64 | |
| parent | d433eb957bf3826e7aea97c12f0cdc9fcb9a1b43 (diff) | |
Various AArch64 optimizations (https://github.com/Shopify/ruby/pull/433)
* When we're storing an immediate 0 value at a memory address, we
can use STUR XZR, Xd instead of loading 0 into a register and
then storing that register.
* When we're moving 0 into an argument register, we can use
MOV Xd, XZR instead of loading the value into a register first.
* In the newarray instruction, we can skip looking at the stack at
all if the number of values we're using is 0.
Notes
Notes:
Merged: https://github.com/ruby/ruby/pull/6289
Diffstat (limited to 'yjit/src/asm/arm64')
| -rw-r--r-- | yjit/src/asm/arm64/mod.rs | 3 | ||||
| -rw-r--r-- | yjit/src/asm/arm64/opnd.rs | 5 |
2 files changed, 7 insertions, 1 deletions
diff --git a/yjit/src/asm/arm64/mod.rs b/yjit/src/asm/arm64/mod.rs index e5ba2f81ea..fb07498ce2 100644 --- a/yjit/src/asm/arm64/mod.rs +++ b/yjit/src/asm/arm64/mod.rs @@ -542,6 +542,9 @@ pub fn mov(cb: &mut CodeBlock, rd: A64Opnd, rm: A64Opnd) { LogicalReg::mov(rd.reg_no, rm.reg_no, rd.num_bits).into() }, + (A64Opnd::Reg(rd), A64Opnd::UImm(0)) => { + LogicalReg::mov(rd.reg_no, XZR_REG.reg_no, rd.num_bits).into() + }, (A64Opnd::Reg(rd), A64Opnd::UImm(imm)) => { LogicalImm::mov(rd.reg_no, imm.try_into().unwrap(), rd.num_bits).into() }, diff --git a/yjit/src/asm/arm64/opnd.rs b/yjit/src/asm/arm64/opnd.rs index a10e289455..c89481fb03 100644 --- a/yjit/src/asm/arm64/opnd.rs +++ b/yjit/src/asm/arm64/opnd.rs @@ -111,6 +111,9 @@ pub const X20_REG: A64Reg = A64Reg { num_bits: 64, reg_no: 20 }; pub const X21_REG: A64Reg = A64Reg { num_bits: 64, reg_no: 21 }; pub const X22_REG: A64Reg = A64Reg { num_bits: 64, reg_no: 22 }; +// zero register +pub const XZR_REG: A64Reg = A64Reg { num_bits: 64, reg_no: 31 }; + // 64-bit registers pub const X0: A64Opnd = A64Opnd::Reg(X0_REG); pub const X1: A64Opnd = A64Opnd::Reg(X1_REG); @@ -143,7 +146,7 @@ pub const X27: A64Opnd = A64Opnd::Reg(A64Reg { num_bits: 64, reg_no: 27 }); pub const X28: A64Opnd = A64Opnd::Reg(A64Reg { num_bits: 64, reg_no: 28 }); pub const X29: A64Opnd = A64Opnd::Reg(A64Reg { num_bits: 64, reg_no: 29 }); pub const X30: A64Opnd = A64Opnd::Reg(A64Reg { num_bits: 64, reg_no: 30 }); -pub const X31: A64Opnd = A64Opnd::Reg(A64Reg { num_bits: 64, reg_no: 31 }); +pub const X31: A64Opnd = A64Opnd::Reg(XZR_REG); // 32-bit registers pub const W0: A64Opnd = A64Opnd::Reg(A64Reg { num_bits: 32, reg_no: 0 }); |