📄 Easily create your resume with Markdown on VSCode / Typora / Obsidian

Verilog/SystemVerilog Syntax and Omni-completion

pathogen.vim: manage your runtimepath

Must-have verilog systemverilog modules

lib, demo, model, data

Vdoing主题博客模板

🚀一款简洁高效的VuePress知识管理&博客(blog)主题

RISC-V Tools (ISA Simulator and Tests)

Rocket Chip Generator

Giter8 template for a simple hello world app in Scala.

个人博客

Spike, a RISC-V ISA Simulator

AutoGPT is the vision of accessible AI for everyone, to use and to build on. Our mission is to provide the tools, so that you can focus on what matters.

automatic-verilog based on vimscript

UESTC Thesis Latex Template 2023. It fully supports the latest format specification in 2023, supports independent symbol table, abbreviation table, and complete and fully customizable Academic/Prof…

《如何使用 LaTeX 排版论文》讲稿

一步一步写MIPS CPU

Verilog library for ASIC and FPGA designers