[RISCV][Lifting] Implement the atomic extension

[moste00]

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• I've read the guidelines for contributing to this repository.
• I made sure to follow the project's coding style.
• I've documented every RZ_API function and struct this PR changes.
• I've added tests that prove my changes are effective (required for changes to RZ_API).
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Detailed description

Continues #6364. Implements the A extension of RISC-V "trivially", by ignoring all concurrency guards and gurantees in the spec since RzIL is a strictly sequential VM, all instructions defined by the extension therefore reduce to a simplified implementation.

Claude Code CLI was used to write some code under review and testing by me, I take responsiblity for all the code and bugs here, I use CCC as only a text editing multiplier.

Test plan

Testing this extension specifically could be challenging, since spawning threads is itself a syscall (which we don't model in RzIL), I'm not sure how can we execute multiple threads (if even sequentially) in RzIL VM.

Theoretically, executing threads one-after-the-other is a valid sequentially-consistent way to execute threads, but I'm not sure we can get to this point. It's also prone to deadlocks if threads share variables and wait on them.

So all-in-all, this extension will be a bit under-tested compared to the others, but I will still add regression testing in the asm test files.

Closing issues

PR Stack Structure

This PR is the third of a 4-PR stack that lifts the IMAFD RISC-V archiecture plus some privileged instructions.

The following is a table for ease of navigation from any PR to any other, please filter by the commit(s) mentioned in the table when reviewing the diff in the "Files Changed" tab to avoid the noise of the base branches.

Extension	PR	Commits To Select in "Files Changed"	State (Open, Merged, Draft, Closed)
I	#6287	No filtering necessary	O
M	#6364	"implement the rest of the multiplication extension"	D
A	#6373 < (THIS PR)	"implement the atomic extension trivially by ignoring concurrency guards"	D
F/D	#6374	"add floating and double instructions, and add privlieged ISA instructions like reading CSRs to implement fflags reading and writing"	D

Because it's painful to maintain this stack manually with no Github or other tooling support, I won't grow it any further until one of those 4 PRs gets merged.

Depends-on: #6364