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Merged
merged 7 commits into from
Jun 27, 2025
Merged

[rte] cleanups and optimizations #1299

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a8cc817
⚠️ [rte] rework RTE trap configuration
stnolting Jun 27, 2025
f1d2ff0
[sw/example] update RTE trap codes
stnolting Jun 27, 2025
e77d5e9
[sw/lib] add RTE TRAP_CODE backwards compatibility layer
stnolting Jun 27, 2025
fdc08b5
[rte] minor rte core optimizations and cleanups
stnolting Jun 27, 2025
004938d
[sim] tb: minor edit
stnolting Jun 27, 2025
0bd10fc
[cpu]double-trap exception has highest priority
stnolting Jun 27, 2025
dc1b669
[changelog] add v1.11.7.3
stnolting Jun 27, 2025
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⚠️ [rte] rework RTE trap configuration 
use the actual trap code from mcause instead of an explicit trap enumeration list
  • Loading branch information
@stnolting
stnolting committed Jun 27, 2025
commit a8cc8172ba066ded48c9ece3eef52389efb940d2
24 changes: 10 additions & 14 deletions sw/lib/include/neorv32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,14 @@ extern "C" {
#include <inttypes.h>
#include <stdlib.h>

// required for semihosting
#if defined(STDIO_SEMIHOSTING)
#include <stdio.h>
#include <string.h>
#include <fcntl.h> // for open
#include <unistd.h> // for close
#endif

/**********************************************************************//**
* @name IO Address Space Map - Peripheral/IO Devices
**************************************************************************/
Expand Down Expand Up @@ -71,98 +79,84 @@ extern "C" {
/**@{*/
#define TWD_FIRQ_ENABLE CSR_MIE_FIRQ0E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define TWD_FIRQ_PENDING CSR_MIP_FIRQ0P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define TWD_RTE_ID RTE_TRAP_FIRQ_0 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define TWD_TRAP_CODE TRAP_CODE_FIRQ_0 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Custom Functions Subsystem (CFS) */
/**@{*/
#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define CFS_RTE_ID RTE_TRAP_FIRQ_1 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Primary Universal Asynchronous Receiver/Transmitter (UART0) */
/**@{*/
#define UART0_FIRQ_ENABLE CSR_MIE_FIRQ2E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define UART0_FIRQ_PENDING CSR_MIP_FIRQ2P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define UART0_RTE_ID RTE_TRAP_FIRQ_2 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define UART0_TRAP_CODE TRAP_CODE_FIRQ_2 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Secondary Universal Asynchronous Receiver/Transmitter (UART1) */
/**@{*/
#define UART1_FIRQ_ENABLE CSR_MIE_FIRQ3E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define UART1_FIRQ_PENDING CSR_MIP_FIRQ3P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define UART1_RTE_ID RTE_TRAP_FIRQ_3 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define UART1_TRAP_CODE TRAP_CODE_FIRQ_3 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Serial Peripheral Interface (SPI) */
/**@{*/
#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define SPI_RTE_ID RTE_TRAP_FIRQ_6 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Two-Wire Interface (TWI) */
/**@{*/
#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define TWI_RTE_ID RTE_TRAP_FIRQ_7 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name General Purpose Input/Output Controller (GPIO) */
/**@{*/
#define GPIO_FIRQ_ENABLE CSR_MIE_FIRQ8E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define GPIO_FIRQ_PENDING CSR_MIP_FIRQ8P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define GPIO_RTE_ID RTE_TRAP_FIRQ_8 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define GPIO_TRAP_CODE TRAP_CODE_FIRQ_8 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Smart LED Controller (NEOLED) */
/**@{*/
#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Direct Memory Access Controller (DMA) */
/**@{*/
#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define DMA_RTE_ID RTE_TRAP_FIRQ_10 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Serial Data Interface (SDI) */
/**@{*/
#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define SDI_RTE_ID RTE_TRAP_FIRQ_11 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name General Purpose Timer (GPTMR) */
/**@{*/
#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name 1-Wire Interface Controller (ONEWIRE) */
/**@{*/
#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Stream Link Interface (SLINK) */
/**@{*/
#define SLINK_FIRQ_ENABLE CSR_MIE_FIRQ14E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define SLINK_FIRQ_PENDING CSR_MIP_FIRQ14P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define SLINK_RTE_ID RTE_TRAP_FIRQ_14 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define SLINK_TRAP_CODE TRAP_CODE_FIRQ_14 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name True-Random Number Generator (TRNG) */
/**@{*/
#define TRNG_FIRQ_ENABLE CSR_MIE_FIRQ15E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define TRNG_FIRQ_PENDING CSR_MIP_FIRQ15P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define TRNG_RTE_ID RTE_TRAP_FIRQ_15 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define TRNG_TRAP_CODE TRAP_CODE_FIRQ_15 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/**@}*/
Expand Down Expand Up @@ -264,6 +258,8 @@ typedef union {
#include "neorv32_uart.h"
#include "neorv32_wdt.h"

// Legacy wrappers
#include "neorv32_legacy.h"

#ifdef __cplusplus
}
Expand Down
41 changes: 0 additions & 41 deletions sw/lib/include/neorv32_rte.h
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Original file line number Diff line number Diff line change
Expand Up @@ -16,47 +16,6 @@

#include <stdint.h>

/**********************************************************************//**
* NEORV32 runtime environment trap IDs.
**************************************************************************/
/**@{*/

/**< Synchronous exceptions */
#define RTE_TRAP_I_ACCESS TRAP_CODE_I_MISALIGNED /**< Instruction access fault */
#define RTE_TRAP_I_ILLEGAL TRAP_CODE_I_ACCESS /**< Illegal instruction */
#define RTE_TRAP_I_MISALIGNED TRAP_CODE_I_ILLEGAL /**< Instruction address misaligned */
#define RTE_TRAP_BREAKPOINT TRAP_CODE_BREAKPOINT /**< Breakpoint (EBREAK instruction) */
#define RTE_TRAP_L_MISALIGNED TRAP_CODE_L_MISALIGNED /**< Load address misaligned */
#define RTE_TRAP_L_ACCESS TRAP_CODE_L_ACCESS /**< Load access fault */
#define RTE_TRAP_S_MISALIGNED TRAP_CODE_S_MISALIGNED /**< Store address misaligned */
#define RTE_TRAP_S_ACCESS TRAP_CODE_S_ACCESS /**< Store access fault */
#define RTE_TRAP_UENV_CALL TRAP_CODE_UENV_CALL /**< Environment call from user mode (ECALL instruction) */
#define RTE_TRAP_MENV_CALL TRAP_CODE_MENV_CALL /**< Environment call from machine mode (ECALL instruction) */
#define RTE_TRAP_DOUBLE_TRAP TRAP_CODE_DOUBLE_TRAP /**< Double-trap */
/**< Asynchronous exceptions */
#define RTE_TRAP_MSI TRAP_CODE_MSI /**< Machine software interrupt */
#define RTE_TRAP_MTI TRAP_CODE_MTI /**< Machine timer interrupt */
#define RTE_TRAP_MEI TRAP_CODE_MEI /**< Machine external interrupt */
#define RTE_TRAP_FIRQ_0 TRAP_CODE_FIRQ_0 /**< Fast interrupt channel 0 */
#define RTE_TRAP_FIRQ_1 TRAP_CODE_FIRQ_1 /**< Fast interrupt channel 1 */
#define RTE_TRAP_FIRQ_2 TRAP_CODE_FIRQ_2 /**< Fast interrupt channel 2 */
#define RTE_TRAP_FIRQ_3 TRAP_CODE_FIRQ_3 /**< Fast interrupt channel 3 */
#define RTE_TRAP_FIRQ_4 TRAP_CODE_FIRQ_4 /**< Fast interrupt channel 4 */
#define RTE_TRAP_FIRQ_5 TRAP_CODE_FIRQ_5 /**< Fast interrupt channel 5 */
#define RTE_TRAP_FIRQ_6 TRAP_CODE_FIRQ_6 /**< Fast interrupt channel 6 */
#define RTE_TRAP_FIRQ_7 TRAP_CODE_FIRQ_7 /**< Fast interrupt channel 7 */
#define RTE_TRAP_FIRQ_8 TRAP_CODE_FIRQ_8 /**< Fast interrupt channel 8 */
#define RTE_TRAP_FIRQ_9 TRAP_CODE_FIRQ_9 /**< Fast interrupt channel 9 */
#define RTE_TRAP_FIRQ_10 TRAP_CODE_FIRQ_10 /**< Fast interrupt channel 10 */
#define RTE_TRAP_FIRQ_11 TRAP_CODE_FIRQ_11 /**< Fast interrupt channel 11 */
#define RTE_TRAP_FIRQ_12 TRAP_CODE_FIRQ_12 /**< Fast interrupt channel 12 */
#define RTE_TRAP_FIRQ_13 TRAP_CODE_FIRQ_13 /**< Fast interrupt channel 13 */
#define RTE_TRAP_FIRQ_14 TRAP_CODE_FIRQ_14 /**< Fast interrupt channel 14 */
#define RTE_TRAP_FIRQ_15 TRAP_CODE_FIRQ_15 /**< Fast interrupt channel 15 */
/**< Total number of trap codes */
#define NEORV32_RTE_NUM_TRAPS (2*32)
/**@}*/

/**********************************************************************//**
* @name Prototypes
**************************************************************************/
Expand Down