Open-source implementation of AlphaEvolve

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

程序员在家做饭方法指南。Programmer's guide about how to cook at home (Simplified Chinese only).

An advanced circuit-based sat solver

A high-efficiency hybrid solving CEC algorithm

Management of Benchmark Instances and Instance Attributes

LLMs as Copilots for Theorem Proving in Lean

SATZilla SAT feature extraction tool

A SAT Solver based on CDCL (Conflict Driven Clause Learning) implemented in python

A Simple CDCL Solver

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

AcadHomepage: A Modern and Responsive Academic Personal Homepage

This is a Pytorch implementation of the paper: Self-Supervised Graph Transformer on Large-Scale Molecular Data

Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

Cryptocurrency historical price data library in Python. Data from https://coinmarketcap.com.

非小号数据

A Pretrained BERT Model for Financial Communications. https://arxiv.org/abs/2006.08097

AIGEN is an open source tool for the generation of transition systems in a symbolic representation. To ensure diversity, it employs a uniform random sampling over the space of all Boolean functions…

Awesome machine learning for logic synthesis

G2SAT: Learning to Generate SAT Formulas

Making large AI models cheaper, faster and more accessible

Hacked together program to convert btor2 files to Verilog.

my circuitSolver

Problems and Results of IWLS 2022 Programming Contest

C++ logic network library