Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

From: Salvatore Dipietro <dipietro(dot)salvatore(at)gmail(dot)com>
To: Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us>
Cc: Nathan Bossart <nathandbossart(at)gmail(dot)com>, Robert Haas <robertmhaas(at)gmail(dot)com>, pgsql-hackers(at)postgresql(dot)org, Salvatore Dipietro <dipiets(at)amazon(dot)com>, blakgeof(at)amazon(dot)com
Subject: Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture
Date: 2025-05-01 22:16:17
Message-ID: CAGnuAhXNQXCcS1nCeD6E0Dyfi4Ms-b0sjcm79Y9iMi5WxUqM4g@mail.gmail.com
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On Thu, 1 May 2025 at 13:08, Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us> wrote:
> Oh! That's an excellent point. The OP didn't mention if their tests
> were done before or after 3d0b4b1, but that might well matter.

The benchmarks we conducted are based on REL_17_2 branch which do not
include the TAS_SPIN(lock) change for ARM yet.

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