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VHDL Code for 8:1 Multiplexer

8:1 Multiplexer The multiplexer is a combinational circuit which accepts several data inputs and allows only one of them at a time to get through to the output.

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Rishikesh Jatekar
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26K views5 pages

VHDL Code for 8:1 Multiplexer

8:1 Multiplexer The multiplexer is a combinational circuit which accepts several data inputs and allows only one of them at a time to get through to the output.

Uploaded by

Rishikesh Jatekar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

EXPERIMENT NO: 07

AIM: Write VHDL code for 8:1 Multiplexer.


APPARATUS: MODELSIM
THEORY: 8:1 Multiplexer The multiplexer is a combinational circuit which accepts
several data inputs and allows only one of them at a time to get through to the output.

Fig.1

EN

CONTROL INPUTS

OUTPUT(Y)
(Selected
Inputs)

SEL(3)

SEL(3)

SEL(3)

D0

D1

D2

D3

D4

D5

D6

D7

VHDL Code For 8:1 Multiplexer


------------------------------------------------------------------------------- File
:
mux8_1.vhd
-- Entity
:
mux8_1
-------------------------------------------------------------------------------- College
:
Rizvi College Of Engineering
-- Simulators
:
Mentor Graphics Modelsim
-------------------------------------------------------------------------------- Description
:
8 TO 1 MULTIPLEXOR
--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
---------------------------------- Entity Declarations ------------------------entity mux8_1 is
port (
D: in STD_LOGIC_VECTOR (7 downto 0);
EN: in STD_LOGIC;
SEL: in STD_LOGIC_VECTOR (2 downto 0);
Y: out STD_LOGIC );
end mux8_1;
architecture mux8_1_arch of mux8_1 is
begin
process(EN,SEL,D)
begin
if(EN='1')then
y<='0';
else
case SEL is
when "000" => y <= D(0);
when "001" => y <= D(1);
when "010" => y <= D(2);
when "011" => y <= D(3);
when "100" => y <= D(4);
when "101" => y <= D(5);
when "110" => y <= D(6);
when others=> y <= D(7);
end case
end if;
end process;
end mux8_1_arch;

Waveforms for 8:1 Multiplexer:


1000

2000

3000

4000

5000

6000

7000

8000

9000

D
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
EN
SEL
Y

ns

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