DMA CONTROLLER 8257

The Direct Memory Access (DMA) mode of data transfer is the fastest amongst all the mode
of data transfer. In this mode, the device may transfer data directly to/from memory without
any interference from the CPU.
Intel’s 8257 is a four channel DMA controller. The 8257, on behalf of the devices, requests
the CPU for bus access using local bus request input i.e. HOLD in minimum mode. In
maximum mode of the microprocessor RQ/GT pin is used as bus request input. On receiving
the HLDA signal or RQ/GT signal from the CPU, the requesting device gets the access the
bus, and it completes the required number of DMA cycles for the data transfer and then hands
over the control of the bus back to the CPU.
8257 INTERNAL ARCHITECTURE

The control logic controls the sequences of operations and generates the
required control signals. The priority resolver resolves the priority of the four
DMA channels depending upon whether normal priority or rotating priority is
programmed.

A byte transfer using 8257 may be requested by an I/O device using any
one of the 8257 DRQ inputs. In response to this, the 8257 sends HRQ signal to
the CPU at its HLD input and waits for acknowledgement at the HLDA input. If
the HLDA signal is received by the DMA controller, it indicates that the bus is
available for the transfer. The DACK line of the selected channel is pulled down
by the DMA controller to indicate the I/O device that its request for the DMA
transfer has been honoured by the CPU.
IOR: It is an active-low bidirectional input line. In the slave mode, the CPU
access the internal registers of the 8257. In the master mode this pin is used to
read data from peripheral devices during a memory write cycle
IOW: It is an active low bidirectional line. In the slave mode, it is used to load
the data bus contents into the 8-bit mode register or upper/lower byte of a 16-bit
DMA address register or terminal count register. In the master mode, it loads the
data to a peripheral during DMA memory read cycle.
CLK: The internal operation of the 8257 requires a clock frequency signal.
RESET: This signal RESETS the DMA controller by turning off all DMA
channels.
A0-A3: These are the four least significant address lines. In slave mode, they act
as input which select one of the registers to be read or written. In the master
mode, they are the four least significant memory address output lines generated
by 8257.
CS: It is a select chip line. It permits read/write operations to and from 8257 in
Slave mode. It prevents read/write operations to/from 8257 while in master
mode.
A4 - A7: In the master mode, this is the upper nibble of the lower byte address
created via DMA.
READY
It is an active-high asynchronous input signal that inserts wait states to make
DMA ready.
HRQ: This signal is used to receive the output device's hold request signal. In
slave mode, it is linked to DRQ input line 8257. In Master mode, it is coupled to
the CPU's HOLD input.
HLDA: When set to 1, the hold acknowledgment signal informs the DMA
controller that the CPU has granted the bus to the requesting peripheral.
MEMR
During DMA read cycles, the low memory read signal is utilized to read data
from the designated memory locations
MEMW
During a DMA write operation, the active-low three-state signal is utilized to
write data to the specified memory region.
AEN
This signal is used to disable the system data bus and the control the bus driven
by the CPU.
TC
It is an abbreviation for 'Terminal Count’. The TC pin is activated when 14-bit
content of the terminal count register of the selected channel becomes equal to
zero.
MARK
The mark will be triggered every 128 cycles or integral multiples of 128 from
the start. It denotes that the current DMA cycle is the 128th since the last
MARK output to the specified peripheral device.
Vcc
It is the power signal that is necessary for the circuit to function.
DREQ0 − DREQ3
Peripheral devices utilize these four individual channel DMA request inputs to
access DMA services. When the fixed priority mode is selected, DRQ0 is given
the highest priority, and DRQ3 is given the lowest.

DACK0 - DACK3
These DMA acknowledge outputs informs the requesting peripheral that the
request has been accepted and the bus is released by the CPU.

Register organisation of 8257

The 8257 performs DMA operation over four independent DMA channels with
the following Registers.
[Link] Address Register
Each DMA channel has one DMA address register. The function of this register
is to store the address of the starting memory location, which will be accessed
by the DMA channel. The device that wants to transfer data over a DMA
channel, will access the block of the memory with the starting address stored in
the DMA Address Register.
[Link] Count Registers
Each of the four DMA channels of 8257 has one terminal count register (TC).
This 16-bit register is used for ascertaining that the data transfer through a DMA
channel ceases or stops after the required number of DMA cycles. After each
DMA cycle, the terminal count register content will be decremented by one and
finally it becomes zero after the required number of DMA cycles are over. The
bits 14 and 15 of this register indicate the type of the DMA operation (transfer).
[Link] Set Register
The mode set register is used for programming the 8257 as per the requirements
of the system. The function of the mode set register is to enable the DMA
channels individually and also to set the various modes of operation as shown in
Figure.

Fig. Mode set register

The bits Do-D3 enable one of the four DMA channels of [Link] the TC STOP
bit is set, the selected channel is disabled after the terminal count condition is
reached, and it further prevents any DMA cycle on the channel. If the TC STOP
bit is programmed to be zero, the channel is not disabled, even after the count
reaches zero and further request are allowed on the same channel. The auto load
bit, if set, enables channel 2 for the repeat block chaining operations, without
immediate software intervention between the two successive blocks. The
extended write bit, if set to ‘1’, extends the duration of MEMW and IOW
signals by activating them earlier, which is useful in interfacing the peripherals
with different access times.
[Link] register
The lower order 4-bits of this register contain the terminal count status for the
four individual channels. If any of these bits is set, it indicates that the specific
channel has reached the terminal count condition. The update flag is not
affected by the read operation. This flag can only be cleared by resetting 8257.
The update flag is set every time, the channel 2 registers are loaded with
contents of the channel 3 registers. It is cleared by the completion of the first
DMA cycle of the new block. This register can only read.

Fig. Status register

Priority allotment
The 8257 can be programmed to select any of the two priority schemes using the command
register. The first one is fixed priority scheme, while the second is the rotating priority
scheme. In the fixed priority scheme, each device connected to a channel is assigned a fixed
priority. In the rotating priority scheme, suppose DRQ0 has highest priority and DRQ3 the
lowest, then after the device at channel 0 gets the service, its priority goes down and the
channel 0 becomes the lowest priority channel. channel 1 now becomes the highest priority
channel and remains the highest priority channel till it gets the service. Rotating priority
scheme is explained in the following figure.

Interfacing 8257 with 8086

To initiate the data transfer between peripheral and memory, peripheral needs system bus.
The system bus is under the control of CPU. The peripheral will send DMA request through
DRQ (DMA Request) to the DMA controller. The DMA controller sends a HOLD request to
the CPU and waits for the CPU to assert the HLDA signal. The CPU releases the control of
the bus before asserting the HLDA signal. Once the HLDA signal goes high, DMA controller
activates the DACK (DMA Acknowledgement) to the requesting peripheral and gains the
control of system bus. The DMA controller is the sole master of the bus, till the DMA
operation is over.

Fig. Interfacing of DMA controller (8257) with 8086

PROGRAMMABLE INTERRUPT PRIORITY CONTROLLER (8259A)

Features of Intel 8259 PIC are as follows:
1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading
further 8259 PICs.
5. Clock cycle is not required.

ARCHITECTURE OF 8259A
Data bus buffer
This buffer interfaces internal bus of 8259A to microprocessor system data bus.
Control words, status and vector information pass through data buffer during read or
write operations.

Read/write control logic

This circuit accepts and decodes commands from the CPU.
CS (chip select) signal enables the read and write operations of 8259A.
WR: Low signal on this pin enables it to accept command words from CPU.
RD: A low on this pin enables 8259A to release status on to the data bus of CPU.
Cascade Buffer/Comparator
This block stores and compare the IDs of all the 8259As used in the system. CAS0-2
are acts as outputs when the 8259A is used as master. In this mode it sends the ID of
the Interrupting Slave device on these lines. CAS0-2 are acts as inputs when 8259A is
in the slave mode. In this mode, it will send its pre-programmed vector address on the
data bus during the next INTA pulse.
CAS0 – CAS2 cascade lines: A single 8259A provides eight vectored interrupts. If
more interrupts are required, the 8259A is used in the cascade mode. In this mode
 8259A along with eight slaves can provide 64 vectored interrupt lines. These CAS0-
CAS2 lines acts as select lines for addressing the slaves 8259A.
SP/EN: When the chip is used in buffered mode, it can be used as a buffer enable to
control buffer transceivers. When the chip is not used in buffered mode, the pin is
used as input to designate whether the chip is used as master (SP=1) or a slave ( EN
=0).
IRR (Interrupt Request register) :
The interrupts at IRQ input lines are handled by IRR. This register stores all the
interrupts requests in it in order to serve them one by one on the priority basis.
Priority Resolver
This unit determines the priorities of the interrupt request appearing simultaneously.
The highest Priority is selected and stored in to the corresponding bit of ISR. IR0
having highest Priority while IR7 has lowest Priority in fixed Priority mode. The
Priorities may be changed by a program in rotating Priority mode.
ISR (In Service Register): This stores all the interrupt requests those are being
served. i.e. it keeps a track of the requests being served.
Interrupt control logic:
This block manages interrupt and interrupt acknowledge signals to be sent to the CPU
for Serving one of the eight interrupt requests. It also accepts the interrupt
acknowledge signal from CPU that causes the 8259A to release vector address on to
the data bus. When INT high, a valid interrupt is asserted. It is used to interrupt the
CPU.
Interrupt Mask Register (IMR): This register stores the bits required to mask the
Interrupt inputs. IMR operates on IRR at the direction of Priority Resolver.

Operating modes of 8259A

Fully nested mode:
• It is the default mode of operation of 8259.
• Here, IR0 has the highest priority and IR7 has the lowest priority.
• When any interrupt requests occurs then the highest priority interrupt request is
serviced first and its vector address is placed on data bus and its corresponding bit in
ISR register is set
Special fully nested mode (SFNM) :
This mode is used by master 8259 in a cascaded mode. Its priority structure is fixed and is
the same as fully nested mode (i.e. IR0 has the highest priority and IR7 has the lowest
priority).
Rotating priority modes:
There are two rotating priority modes –
1. Automatic rotation mode
• In this mode, after a device is serviced, it gets the lowest priority. All other priorities
rotate according to it.
• Example: If IR4 has just been serviced, it will get the lowest priority.
2. Specific Rotation Mode
• Here, the programmer can alter priorities by programming the lowest priority and thus
fixing all other priorities.
• For example: If IR6 is programmed as the lowest priority, then IR7 will have the
highest priority.
Special mask mode (SMM) :
• In SMM, 8259 enables interrupts of all levels (lower or higher) except the one that is
currently in service.
• Because we are especially masking the request of the priority level of interrupt, which
is the same as the current interrupt priority level, therefore it is called special mask
mode.
Poll mode :
Here the INT pin of 8259 is not used, so, 8259 cannot interrupt the microprocessor.
Instead, the microprocessor will provide a poll command to 8259. In response, 8259
provides a poll word to the microprocessor. The poll word indicates the highest priority
interrupt which needs service from microprocessor. Thereafter, the microprocessor
services the interrupt.