Logic Families

Introduction, Overview,
Comparison & Interfacing
 Logic Family Definition
 A circuit configuration or approach used to
produce a type of digital integrated circuit.
 Consequence:
Different logic functions, when fabricated in the
form of an IC with the same approach, or in
other words belonging to the same logic family,
will have identical electrical characteristics.
 The set of digital ICs belonging to the same logic
family are electrically compatible with each other

2
Logic Families
Logic Family : A collection of different IC’s that
have similar circuit characteristics
The circuit design of the basic gate of each logic
family is the same
The most important parameters for evaluating and
comparing logic families include :
Logic Levels
Power Dissipation
Propagation delay
Noise margin
Fan-out ( loading )

3
 Common Characteristics of the
Same Logic Family
 Supply voltage range, speed of response, power
dissipation, input and output logic levels, current
sourcing and sinking capability, fan-out, noise
margin, etc.
 Consequence:
Choosing digital ICs from the same logic
family guarantees that these ICs are
compatible with respect to each other and
that the system as a whole performs the
intended logic function.

4
Implementing Logic Circuits
There are several varieties of transistors – the
building blocks of logic gates – the most important
are:
BJT (bipolar junction transistors)
One of the first to be invented
FET (field effect transistors)
Especially Metal-Oxide Semiconductor types (MOSFET’s)
MOSFET’s are of two types: NMOS and PMOS

5
 Transistor Size Scaling
Performance improves as size is decreased: shorter switching time, lower power consumption.

2 orders of magnitude reduction in transistor size in 30 years.

6
Moore’s Law
In 1965, Gordon Moore predicted that the number of
transistors that can be integrated on a die would
double every 18 to 14 months
i.e., grow exponentially with time
Considered a visionary – million transistor/chip
barrier was crossed in the 1980’s
2300 transistors, 1 MHz clock (Intel 4004/4040) - 1971
42 Million transistors, 2 GHz clock (Intel P4) - 2001
140 Million transistors, (HP PA-8500)

7
Moore’s Law and Intel

From Intel’s 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond

8
9
TTL and CMOS
Connecting BJT’s together gives rise to a family of logic gates
known as TTL
Connecting NMOS and PMOS transistors together gives rise
to the CMOS family of logic gates

Transistor MOSFET
BJT types (NMOS, PMOS)

TTL Logic gate families CMOS

10
 Logic Families Vocabulary
TTL (Transistor-Transistor-Logic) Integrated-circuit technology that
uses the BJT as the principal circuit element.

CMOS (Complimentary Metal Oxide Semiconductor) Integrated-circuit

technology that uses the FET as the principal circuit element.

ECL (Emitter Coupled Logic) Integrated-circuit technology that uses the BJT
configured as a differential amplifier. This eliminates saturation and improves
speed but uses more power than other families.
Digital Logic Families

12
Example Logic Families
 General comparison or three commonly available logic
families.

the most important to understand

 Types of Logic Families
 The entire range of digital ICs is fabricated
using either bipolar devices or MOS devices
or a combination of the two.
 BJT families:
◦ Diode Logic (DL). (obsolete)
◦ Resistor Transistor Logic (RTL). (obsolete)
◦ Diode Transistor Logic (DTL). (obsolete)
◦ Transistor Transistor Logic (TTL).
◦ Emitter Coupled Logic (ECL), aka Current Mode
Logic(CML).
◦ Integrated Injection Logic (I2L). (obsolete)
14
 Types of Logic Families
 MOS families:
◦ PMOS family (using P-channel MOSFETs)
◦ The NMOS family (using N-channel
MOSFETs)
◦ The CMOS family (using both N- and P-
channel devices).
◦ The Bi-MOS logic family uses both bipolar
and MOS devices.

15
 Types of Logic Families
 The entire range of digital ICs is fabricated
using either bipolar devices or MOS devices
or a combination of the two.
 BJT families:
◦ Diode Logic (DL). (obsolete)
◦ Resistor Transistor Logic (RTL). (obsolete)
◦ Diode Transistor Logic (DTL). (obsolete)
◦ Transistor Transistor Logic (TTL).
◦ Emitter Coupled Logic (ECL), aka Current Mode
Logic(CML).
◦ Integrated Injection Logic (I2L). (obsolete)
16
Types of Logic Families

17
Types of Logic Families

18
Types of Logic Families

19
Types of Logic Families

20
Pull-up and Pull-down Resistors

21
Pull-up and Pull-down Resistors

22
Pull-up and Pull-down Resistors

? 23
Pull-up and Pull-down Resistors

24
Pull-up and Pull-down Resistors

25
Pull-up and Pull-down Resistors
Single IC

26
Pull-up and Pull-down Resistors
Single IC

Multiple ICs

27
 Pull-up and Pull-down Resistors

Pull-up Input
 Pull-up and Pull-down Resistors

Pull-down Input
 Pull-up and Pull-down Resistors

Floating Input
Pull-up and Pull-down Resistors

31
Pull-up and Pull-down Resistors

32
Pull-up and Pull-down Resistors

33
Diode Logic
(DL)

34
DL Example

35
DL Example

36
DL Example

37
DL Example

38
DL Example

39
DL Example

40
Resistor Transistor Logic
(RTL)

41
RTL Example

42
RTL Example

NOT Gate
43
 RTL Example

NOT Gate NOR Gate

44
RTL Example

NOR Gate
45
RTL Example

NOR Gate
46
RTL Example

NOR Gate
47
RTL Example

OR Gate 48
 RTL Example

OR Gate NOR Gate

49
RTL Example

AND Gate
50
RTL Example

AND Gate
51
RTL Example

NAND Gate
52
 RTL Example

NAND Gate AND Gate

53
RTL Example

XOR Gate
54
RTL Example

XNOR Gate
55
 RTL Example

Combining DL and RTL 56

Diode Transistor Logic
(DTL)

57
DTL Example

58
 Why not RTL?
Problems with RTL circuits:
• Input resistor slows down the rate at which the internal
capacitance of the transistor can charge or discharge
• Limits the frequency at which RTL gates can switch states
• Resistors take up significant amount of space on the silicon
chip that comprises the integrated circuit
• High-value resistors generally require more space than
lower-value resistors
• Shape of resistor on chip depends very much on the required
resistance value
• Real estate is very precious, and every effort is made to
develop and use techniques that will minimize the amount of
space required for any circuit
59
 Why DTL?
Advantages of diodes
• Take up far less room than resistors
• Can be constructed to all be the same
• Internal resistance of a diode is small when the diode is
forward biased, thus allowing for faster switching action
• Gates built with diodes in place of most resistors can operate
at higher frequencies.
• Diode-Transistor Logic (DTL) rapidly replaced RTL in most
digital applications.

60
DTL Example

?
NAND Gate
61
DTL Example

NAND Gate
62
DTL Example

NOT Gate
63
DTL Example

NAND Gate
64
DTL Example

NAND Gate
65
DTL Subfamilies

NAND Gate
DTL Example

NOR Gate
67
DTL Example

AND/OR/Invert Gate
68
Subfamilies
Transistor Transistor Logic
(TTL)

70
DTL Subfamilies
7400 Series History
1960s space program drove
development of 7400 series
Consumed all available devices for
internal flight computer
$1000 / device (1960 dollars)
10:1 integration improvement over
discrete transistors
1963 Minuteman missile forced
7400 into mass production
Drove pricing down to $25 / circuit
(1963 dollars)

73
 SSI Devices
Each package contains a code identifying the package

N74LS00

Manufacturers Code
Family
L Member
N = National Semiconductors 00 = Quad 2 input NAND
SN = Signetics LS
H 02 = Quad 2 input Nor
04 = Hex Invertors
Specification 20 = Dual 4 Input NAND
74
75
TTL Subfamilies

76
7400 Series Evolution
BJT storage time reduction by using a BC Schottky diode.
Schottky diode has a Vfw=0.25V. When BC junction becomes forward
biased Schottky diode will bypass base current.
C

77
Too Much of a Good Thing?
Families
Packages
Reliability options
Speed grades
Features
Functions

An availability nightmare! >> 500K unique devices

78
Different Families Don’t all Speak
the Same Language

79
Sometimes Things Get Lost or
Added in the Translation*

Different families aren’t always on speaking terms with one another

80
The World of TTL

81
Success Drives Proliferation

2003 1960

New families introduced based on

Higher performance
Lower power
New features
New signaling threshold
Spawned over 32 unique families! 82
Success Drives Proliferation
Products introduced in the 1960
are near the end of their life
cycle
Decreasing supplier base
Increasing prices
Not recommended for new
designs
Products considered to be
“mature” are about 2 decades
into their life cycle
High-volume production
Multiple suppliers
Low prices
Newer products are only a few
years into their life cycle
High performance
High level of vendor and
supplier support
Newest technologies
Higher prices

83
DTL Subfamilies
DTL Subfamilies
TTL Subfamilies
TTL Subfamilies

NOR Gate
TTL Subfamilies

NOR Gate
TTL Subfamilies

NOR Gate
TTL Subfamilies

NOR Gate
TTL Subfamilies

OR Gate
TTL Subfamilies

OR Gate
 TTL Circuit Operation
+Vcc

4K 1.6K 130
R1 R2 R3
A B I Q Q Q Q Y O/P
CQ1 1 2 3 4
Q 0 0 + ON OFF OFF ON 1
4
Q
2 0 1 + ON OFF OFF ON 1
D3
A
Y O/P 1 0 + ON OFF OFF ON 1
B
Q 1 1 － OFF ON ON OFF 0
1 I CQ1 Q
D 3
1 D2
1K
R4 Table explaining the operation of the
TTL NAND gate circuit

A standard TTL NAND gate circuit

NAND Gate
TTL Subfamilies

NOT Gate
Wired-AND
Open collector outputs connected together to a common pull-
up resistor
Any collector can pull the signal line low
Logically an AND gate

106
107
108
109
Tri-State Logic
Both output transistors of totem-pole output are turned off
Usually used to bus multiple signals on the same wire
Gates not enabled present high-Z to bus and therefore do
not interfere with other gates putting signals on the bus

110
Three-State Output
 In addition to the two usual output
states (HIGH and LOW), has a third
output state called high-impedance
(“high-Z”).
 In the high-Z state, the output is
disconnected from the external
circuit.
 Useful when the outputs of many
chips are tied to the same bus: at
any time, only one of them should
be connected to the bus.
112
The three states of a tristate circuit.

Copyright ©2009 by Pearson Higher Education, Inc.

Upper Saddle River, New Jersey 07458
Digital Fundamentals, Tenth Edition All rights reserved.
Thomas L. Floyd
Tri-State Logic
Tri-state logic includes a switch at the output
In the figure below, the three states are illustrated:
a) Logic High output
b) Logic Low output
c) High impedance (Hi-Z) output

114
Basic tristate inverter circuit.

Copyright ©2009 by Pearson Higher Education, Inc.

Upper Saddle River, New Jersey 07458
Digital Fundamentals, Tenth Edition All rights reserved.
Thomas L. Floyd
116
117
Integrated Injection Logic
(IIL or I2L)
or
Merged Transistor Logic
(MTL)

118
I2L Example
I2L Example
I2L Example
I2L Example
Emitter Coupled Logic
(ECL)
or
Current Mode Logic
(CML)

125
ECL Example
ECL Example
ECL Example
Metal Oxide Semiconductors
(MOS)

140
Types of Logic Family 2

141
Field Effect Transistors (FET)
Junction Field Effect Transistor
(JFET)
Junction Field Effect Transistor
(JFET)
 Field Effect Transistors (FET)
In Field Effect Transistors (FETs)
• Depletion mode
• transistor is in an ON state at zero gate-source voltage
• Enhancement mode
• transistor is in an OFF state at zero gate-source voltage
 Field Effect Transistors (FET)
In MOSFET (Metal–Oxide–Semiconductor FETs)
• E-MOSFETs (Enhancement MOSFETs)
• E-MOSFET are normally OFF at zero gate–source
voltage.
• Are the common switching elements in most integrated
circuits
• NMOS can be turned on by pulling the gate voltage
higher than the source voltage
• PMOS can be turned on by pulling the gate voltage
lower than the source voltage
• In most circuits, this means pulling an enhancement-
mode MOSFET's gate voltage towards its drain voltage
turns it ON.
 Field Effect Transistors (FET)
In MOSFET (Metal–Oxide–Semiconductor FETs)
• D-MOSFETs (Depletion MOSFETs)
• D-MOSFETs are normally ON at zero gate–source
voltage
• Used as load "resistors" in logic circuits
• For N-type depletion-load devices, the threshold voltage
might be about –3 V, so it could be turned off by pulling
the gate 3 V negative
• The drain, by comparison, is more positive than the
source in NMOS
• In PMOS, the polarities are reversed
Enhancement vs Depletion Modes
 Metal Oxide
Semiconductor
Field Effect
Transistor
(MOSFET)
Metal Oxide Semiconductor Field
Effect Transistor
(MOSFET)
Metal Oxide Semiconductor Field
Effect Transistor
(MOSFET)
E-MOSFETs
 MOS AND CMOS ICs
• MOS stands for metal-oxide semiconductor.
• PMOS, NMOS, and CMOS are three technologies used to
manufacture ICs.
• NMOS stands for negative-channel metal-oxide semiconductor.
NMOS ICs are faster than PMOS.
• PMOS stands for positive-channel metal-oxide semiconductor.
• CMOS stands for complementary metal-oxide semiconductor.
Both PMOS and NMOS devices are used it its manufacture.
• CMOS ICs are noted for exceptionally low power consumption.
• CMOS ICs were slower than bipolar digital ICs (such as TTL
devices).
• Transmission gates or bilateral switches are unique digital devices
created using CMOS technology.
 MOSFET
METAL OXIDE SEMICONDUCTOR
FIELD EFFECT TRANSISTORS
P-CHANNEL ENHANCEMENT N-CHANNEL ENHANCEMENT

TO TURN ON GATE MUST BE TO TURN ON GATE MUST BE

LOWER THAN SOURCE HIGHER THAN SOURCE
 CMOS
COMPLIMENTARY
METAL OXIDE SEMICONDUCTOR
C-MOS

5V
+V

P-MOS

0V Vin
Vout

N-MOS
MOS Circuit Operation
+VDD
S
Q1
D
O/P I/ P Q1 Q2 O/P
D
0 ON OFF 1
I/P Q2
S 1 OFF ON 0

Table explaining the operation of

the CMOS inverter circuit
A CMOS inverter circuit

163
N-Channel Metal Oxide
Semiconductors
(NMOS)

164
NMOS Gates

NMOS Inverter
NMOS Gates

NMOS NAND
NMOS NAND
NMOS NOR
P-Channel Metal Oxide
Semiconductors
(PMOS)

174
Complementary Metal Oxide
Semiconductors
(CMOS)

181
CMOS Gates
CMOS Sub families

184
CMOS Family Evolution
CMOS Logic Trend: Reduction of dynamic losses
(cross-conduction, capacitive charge/discharge cycles)
by decreasing supply voltages:
12V→5V →3.3V →2.5V → 1.8V → 1.5V …
Reduction of IC power dissipation is the key to:
lower cost (packaging)
higher integration
improved reliability

186
CMOS Gates
CMOS Gates
CMOS Gates
CMOS Gates
CMOS Gates
Comparison of Logic Families
Characteristics of Logic
Families
Electronic Combinational Logic
Within each of these families there is a large variety of different devices
We can break these into groups based on the number gates per device

Acronym Description No Gates Example

SSI Small-scale integration <12 4 NAND gates
MSI Medium-scale integration 12 – 100 Adder
LSI Large-scale integration 100 – 1000 6800
VLSI Very large-scale integration 1000 – 1M 68000
ULSI Ultra large scale integration > 1M 80486/80586

200
Characteristics of Logic
Families

1. Data Sheets
Electrical Parameters And
Interpretation Of Data Sheets
Voltages and Currents
Noise Margin
Power Dissipation
Propagation Delay
Speed-Power Product
Fan-In, Fan-Out
Comparison of Logic Families
Interpretation of Data Sheets

202
Electrical Characteristics
TTL CMOS
faster (some versions) lower power consumption
strong drive capability simpler to make
rugged greater packing density
better noise immunity

• Complex IC’s contain many millions of transistors

• If constructed entirely from TTL type gates would melt
• A combination of technologies (families) may be used
• CMOS has become most popular and has had greatest development

204
Characteristics of Logic
Families

2. Input & Output Currents

 Characteristic Parameters 1
 HIGH-level input current, IIH (current flowing into
(taken as positive) or out of (taken as negative) an input
when a HIGH-level input voltage equal to the minimum
HIGH-level output voltage specified for the family is applied.
 LOW-level input current, IIL. is the maximum current
flowing into (taken as positive) or out of (taken as negative)
the input of a logic function when the voltage applied at the
input equals the maximum LOW-level output voltage
specified for the family.
 unit load (UL) HIGH-level and LOW-level input current or
loading typically found in data sheets (For devices of the TTL
family, 1 UL (HIGH)=40 A and 1 UL (LOW)=1.6 mA.

206
Characteristic Parameters 2
 HIGH-level output current, IOH. This is the
maximum current flowing out of an output
when the input conditions are such that
the output is in the logic HIGH state.
Typically negative number.
 LOW-level output current, IOL. This is the
maximum current flowing into the output
pin of a logic function when the input
conditions are such that the output is in
the logic LOW state.
207
 Characteristic Parameters 3
 HIGH-level off-state (high-impedance state) output
current, IOZH. Thisis the current flowing into
an output of a tristate logic function with the
ENABLE input chosen so as to establish a
high-impedance state and a logic HIGH
voltage level applied at the output. The input
conditions are chosen so as to produce logic
LOW if the device is enabled.

208
Current-Sourcing and Current-
Sinking

 For TTL:
– A HIGH output sources current
– A LOW output sinks current.
Characteristics of Logic
Families

3. Fan In & Fan Out

Input and output current specifications

211
Fan-In
Fan in- the load an input places on an output.
Number of input signals to a gate
Not an electrical property
Function of the manufacturing process

NAND gate with a

Fan-in of 8

212
Fan-Out (Gate Drive Capability)
A logic gate can supply a maximum output current
IOH(max), in the high state or
IOL(max), in the low state
A logic gate requires a maximum input current
IIH(max), in the high state or
IIL(max), in the low state
Ratio of output and input current decide how many logic
gates can be driven by a logic gate
fan-out(high) = IOH(max) / IIH (max)
fan-out(low) = IOL(max) / IIL(max)
overall fan-out = fan-out(high) or fan-out(low) whichever is lower
A typical figure of fan-out is ten (10)

213
Fan-Out Definition
The fan-out, which is the maximum number of
inputs that can be driven successfully to either
logic level before the output becomes invalid
Fan-out. is the number of inputs of a logic
function that can be driven from a single output
without causing any false output

214
Fan-Out
● A measure of the ability of the output of one gate to
drive the input(s) of subsequent gates
● Usually specified as standard loads within a single
family
● e.g., an input to an inverter in the same family

● May have to compute based on current drive

requirements when mixing families
● Although mixing families is not usually

recommended

215
Current Sourcing and Sinking
Current-source : the driving gate produces a
outgoing current
VOH
Low
IIH
Current-sinking : the driving gate receives an
incoming current
VOL
High
IIL
216
Fan-Out
An illustration of fan-out and the associated source
and sink currents

217
Worked Example
How many 74LS00 NAND gate inputs can be driven
by a 74LS00 NAND gate outputs ?

Solution:
Refer to data sheet of 74LS00, the maximum values of
IOH = 0.4mA, IOL = 8mA, IIH = 20uA, and IIL = 0.4mA
Hence,
fan-out(high) = IOH(max) / IIH (max)=0.4mA/20uA=20
fan-out(low) = IOL(max) / IIL(max)=8mA/0.4mA=20,
the overall fan-out = fan-out(high) or fan-out(low) whichever is lower.
Hence, overall fan-out = 20

218
Characteristics of Logic
Families

4. Input & Output Voltages

 Characteristic Parameters 4
 LOW-level input voltage, [Link] is the
maximum voltage level applied at the input
that is recognized as a legal LOW level for
the specified family.
 HIGH-level output voltage, VOH. This is the
minimum voltage on the output pin of a logic
function when the input conditions establish
logic HIGH at the output for the specified
family.

220
Characteristic Parameters 5
 This is the
HIGH-level output voltage, VOH.
minimum voltage on the output pin of a
logic function when the input conditions
establish logic HIGH at the output for the
specified family.

221
Voltages & Currents Summary
For a High-state gate driving a second gate, we define:
VOH (min), high-level output voltage, the minimum voltage level that a logic
gate will produce as a logic 1 output.
VIH (min), high-level input voltage, the minimum voltage level that a logic
gate will recognize as a logic 1 input. Voltage below this level will not be
accepted as high.
IOH, high-level output current, current that flows from an output in the logic
1 state under specified load conditions.
IIH, high-level input current, current that flows into an input when a logic 1
voltage is applied to that input.

IOH IIH
Test setup for
measuring
values VOH VIH
Ground 222
Voltages & Currents Summary
For a Low-state gate driving a second gate, we
define:
VOL (max), low-level output voltage, the maximum voltage level
that a logic gate will produce as a logic 0 output.
VIL (max), low-level input voltage, the maximum voltage level
that a logic gate will recognize as a logic 0 input. Voltage above
this value will not be accepted as low.
IOL , low-level output current, current that flows from an output in
the logic 0 state under specified load conditions.
IIL , low-level input current, current that flows into an input when
a logic 0 voltage is applied to that input.
I OL I IL
Inputs are
connected to Vcc
instead of V OL V IL
Ground
Ground 223
Electrical Characteristics

Important characteristics are:

logic 1

VOHmin min value of output recognized as a ‘1’

VIHmin min value input recognized as a ‘1’
undetermined
input voltage
VILmax max value of input recognized as a ‘0’
VOLmax max value of output recognized as a ‘0’

logic 0 Values outside the given range are not allowed.

224
Logic Level & Voltage Range
Typical acceptable voltage ranges for positive logic 1 and
logic 0 are shown below
A logic gate with an input at a voltage level within the
‘undetermined’ range will produce an unpredictable output
level.
5.0V 5.0V
Logic 1 Logic 1
3.5V
2.5V Undetermined
Undetermined
1.5V
0.8V
Logic 0 Logic 0
0V 0V
TTL CMOS

225
Logic levels for TTL
 Logic Levels Example
• Voltage characteristic - defines logical 0
(LOW) or logical 1 (HIGH)

TTL Voltage Profiles Chart

Input Output

LOW GND - 0.8V GND - 0.4V (0.1V typical)

HIGH 2.0 - 5.5V 2.4 - 5.5V (3.5V typical)
 INPUT VOLTAGE PROFILES-
TTL AND 4000 SERIES CMOS
Input Voltage Profiles
TTL 100% CMOS
+5V +10V
90%
80% HIGH
HIGH
70%
60%
50%
40%
30% LOW
20% 0 to +3V for CMOS
0 to +0.8V in TTL
LOW 10% LOW
GND 0%
 INPUT VOLTAGE PROFILES-
TTL AND 4000 SERIES CMOS
Input Voltage Profiles
TTL 100% CMOS
+5V +10V
90%
80% HIGH
HIGH
70%
60%
50%
40%
30%
Undefined
20% +3 to +7V for CMOS
LOW 10% LOW +0.8V to +2.0V for TTL
GND 0%
 INPUT VOLTAGE PROFILES-
TTL AND 4000 SERIES CMOS
Input Voltage Profiles
TTL 100% CMOS
+5V +10V
90%
80% HIGH
HIGH
70%
60%
50%
40%
30%
HIGH
20%
+7V to +10V - CMOS
10% LOW
LOW +2V to +5V - TTL
GND 0%
 INPUT VOLTAGE PROFILES-
TTL AND 4000 SERIES CMOS
Input Voltage Profiles
TTL 100% CMOS
+5V +10V
90%
80% HIGH
HIGH
70%
60%
50%
40% CAUTION
30% Output V profile differs
20% Other families V profile differs
LOW 10% LOW
GND 0%
 TEST
TTL Voltage Profiles
INPUT OUTPUT
+5V +5V

H H
+2.4V
Input = +4V +2V
Output = ? ?
? ?
+0.8V
Low +0.4V
Low
GND GND

(Left mouse click for questions and answers)

 TEST
TTL Voltage Profiles
INPUT OUTPUT
+5V +5V

H H
+2.4V
Input = +4V +2V
Output = ? ?
HIGH
? ?
+0.8V
Low +0.4V
Low
GND GND

(Left mouse click for questions and answers)

 TEST
TTL Voltage Profiles
INPUT OUTPUT
+5V +5V

H H
+2.4V
Input = +0.3V +2V
Output = ?
? ? ?
+0.8V
Low +0.4V
Low
GND GND

(Left mouse click for questions and answers)

 TEST
TTL Voltage Profiles
INPUT OUTPUT
+5V +5V

H H
+2.4V
Input = +0.3V +2V
Output = ? LOW
? ?
+0.8V
Low +0.4V
Low
GND GND

(Left mouse click for questions and answers)

 TEST
TTL Voltage Profiles
INPUT OUTPUT
+5V +5V

H H
+2.4V
Input = +1.2V +2V
Output = ?
? ? ?
+0.8V
Low +0.4V
Low
GND GND

(Left mouse click for questions and answers)

 TEST
TTL Voltage Profiles
INPUT OUTPUT
+5V +5V

H H
+2.4V
Input = +1.2V +2V
Output = ?
? ? ?
Undefined
+0.8V
Low +0.4V
Low
GND GND

(Left mouse click for questions and answers)

 TEST
TTL Voltage Profiles
INPUT OUTPUT
+5V +5V

H H
+2.4V
Input = +2.2V +2V
Output = ?
? ? ?
+0.8V
Low +0.4V
Low
GND GND

(Left mouse click for questions and answers)

 TEST
TTL Voltage Profiles
INPUT OUTPUT
+5V +5V

H H
+2.4V
Input = +2.2V +2V
Output = ?
? ? ?
HIGH
+0.8V
Low +0.4V
Low
GND GND

(Left mouse click for questions and answers)

Characteristics of Logic
Families

5. Noise Margin
 Characteristic Parameters 9
 Noise margin. This is a quantitative measure of noise
immunity offered by the logic family. When the output
of a logic device feeds the input of another device of
the same family, a legal HIGH logic state at the output
of the feeding device should be treated as a legal
HIGH logic state by the input of the device being fed.
Similarly, a legal LOW logic state of the feeding device
should be treated as a legal LOW logic state by the
device being fed.

241
Noise Margin
Manufacturers specify voltage limits to represent the logical
0 or 1.
These limits are not the same at the input and output sides.
For example, a particular Gate A may output a voltage of 4.8V when it
is supposed to output a HIGH but, at its input side, it can take a
voltage of 3V as HIGH.
In this way, if any noise should corrupt the signal, there is
some margin for error.

242
Noise Margin
If noise in the circuit is high enough
it can push a logic 0 up or drop a
logic 1 down into the undetermined VOHmin
logic 1
or “illegal” region VIHmin

The magnitude of the voltage

required to reach this level is the Undetermined
noise margin input voltage

Noise margin for logic high is:

NMH = VOHmin – VIHmin VILmax
logic 0
VOLmax

243
Noise Margin
Difference between the worst case output voltage of
one stage and worst case input voltage of next stage
Greater the difference, the more unwanted signal that
can be added without causing incorrect gate
operation
NMhigh = VOHmin - VIHmin

NMlow = VILmax - VOLmax

244
 Noise margins in Logic Circuits

V V(y)
"1" OH
Slope = -1
V V
IH OH

Undefined
Region VM
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH

245
 Noise margins in Logic Circuits

VDD
"1"
V
OH
NMH Noise margin high
V
IH
Undefined
Region
NML V
V
OL
IL Noise margin low

"0"
VGND
Gate Output Gate Input

246
Noise MARGIN

247
Worked Example
Given the following parameters, calculate the
noise margin of 74LS series.
P
a
ram e
t
er 7
4
LS
VIH
(
min
) 2
V
VIL
(
max
) 0
.
8V
V
OH(min
) 2
.
7V
V
OL(
max
) 0
.
4V

Solution:
High Level Noise Margin, VNH = VOH (min) - VIH (min)=2.7V-2.0V=0.7V
Low Level Noise Margin, VNL = VIL (max) - VOL (max)=0.8V-0.4V=0.4V

248
Noise Margin & Noise Immunity
Noise immunity of a logic circuit refers to the circuit’s ability
to tolerate noise voltages on its inputs.
Noise immunity - logic circuit’s insensitivity or resistance to
undesired voltages called “noise.”
A quantitative measure of noise immunity is called noise
margin
High Level Noise Margin, VNH = VOH (min) - VIH (min)
Low Level Noise Margin, VNL = VIL (max) - VOL (max)
Logic 1 Logic 1
VOH (min)
VNH
VIH (min)

VIL (max)
VNL
VOL (max)
Logic 0 249
Logic 0
Output Voltage Ranges Input Voltage Ranges
Characteristics of Logic
Families

6. Supply Voltage & Current

 DC Supply Voltages

 TTL chips are optimized for 5 V supply,

and cannot tolerate voltages far above
or below 5 V.
 CMOS chips may be optimized for 5 V,
3.3 V, 2.5 V, or 1.8 V supplies. Most
CMOS chips can tolerate a much wider
range of supply voltages (up to 15V)
than TTL chips.
Characteristic Parameters 6
 Supply current, ICC. The
supply current when
the output is HIGH, LOW and in the high-
impedance state is respectively designated as
ICCH, ICCL and ICCZ.

252
Characteristics of Logic
Families

7. Timing and Frequencies

Characteristic Parameters 6
 Rise time, tr. Thisis the time that elapses
between 10 and 90 % of the final signal level
when the signal is making a transition from
logic LOW to logic HIGH.
 Fall time, tf . This is the time that elapses
between 90 and 10 % of the signal level
when it is making HIGH to LOW transition.

254
Speed: Rise & Fall Times
Rise Time
Time from 10% to 90% of signal, Low to High
Fall Time
Time from 90% to 10% of signal, High to Low

rise time fall time

10% 90% 90% 10% 255

 Characteristic Parameters 7
 Propagation delay tp. is
the time delay between
the occurrence of change in the logical level at
the input and before it is reflected at the
output. It is the time delay between the
specified voltage points on the input and
output waveforms.
 Propagation delays are separately defined for
LOW-to-HIGH and HIGH-to-LOW
transitions at the output. In addition, we also
define enable and disable time delays that
occur during transition between the high-
impedance state and defined logic LOW or
HIGH states.
256
Speed: Propagation Delay
A logic gate always takes some time to change states
tPLH is the delay time before output changes from low to high
tPHL is the delay time before output changes from high to low
both tPLH & tPHL are measured between the 50% points on the
input and output transitions

Input 50%

Output

0
tPHL tPLH 257
Further Important Characteristics
The propagation delay (tpd) which is the time
taken for a change at the input to appear at the
output

258
 Characteristic Parameters 7
 This is the maximum
Maximum clock frequency, fmax.
frequency at which the clock input of a flip-flop
can be driven through its required sequence
while maintaining stable transitions of logic level
at the output in accordance with the input
conditions and the product specification.

259
Characteristics of Logic
Families

8. Power Dissipation
 Power Dissipation
 Recall that power equals current times
voltage (P=IV).
 So a gate’s power dissipation is given
by its supply voltage (VCC) times its
supply current (ICC).
 A lower-power device wastes less
energy, generates less heat, and costs
less to run than a higher-power device.
 Characteristic Parameters 8
 The power dissipation
Power dissipation.
parameter for a logic family is specified in terms
of power consumption per gate and is the
product of supply voltage VCC and supply
current ICC.

262
Power Dissipation
Static
I2R losses due to passive components, no input signal
Dynamic
I2R losses due to charging and discharging capacitances
through resistances, due to input signal

263
 Characteristic Parameters 9
 Speed–power product. The speed of a logic circuit can
be increased, that is, the propagation delay can be
reduced, at the expense of power dissipation.

264
Speed-Power Product
Speed (propagation delay) and power consumption
are the two most important performance parameters
of a digital IC.
A simple means for measuring and comparing the
overall performance of an IC family is the speed-
power product (the smaller, the better).
For example, an IC has
an average propagation delay of 10 ns
an average power dissipation of 5 mW
the speed-power product = (10 ns) x (5 mW)
= 50 picoJoules (pJ)

265
Characteristics of Logic
Families

9. Logic Families Trade Offs

and Comparison
Logic Family Tradeoffs
Looking for the best
speed/power product
tp and Pd are normally
included in the data
sheet for each device
Older logic families
are the worst
CMOS is one of the
best
FPGAs use CMOS

267
Comparison of Logic Families

268
Comparison of Logic Families

vo

vi

269
Comparison Logic Families

270
Comparison of Logic Families

speed power product = a constant

271
Comparison of Characteristics

272
273
TTL - Example SN74LS00
Recommended operating conditions 5 Volt
Vcc supply voltage 5V ± 0.5 V
input voltages VIH = 2V
VIL = 0.8V Input Output
Range Range
Electrical Characteristics for 1 for 1
output voltage VOH = 2.7V
(worst case) VOL = 0.5V 2.7
max input currents IIH = 20µA 2.0
IIL = -0.4mA
propagation delay tpd = 15 nS

noise margins for a logic 0 = 0.3V Input 0.8

Output
for a logic 1 = 0.7V Range 0.5
Range
for 0
Fan-out 20 TTL loads 0 Volt for 0

274
Characteristics of Logic
Families

10. Types of Outputs

Three Kinds of Outputs

 TTL chips can have three kinds of

outputs:
– Totem-pole (the most common)
– Open-collector
– Three-state
Totem-Pole Output
 Most chips you’ve used up to now
have had totem-pole outputs.
A standard TTL inverter circuit.

Copyright ©2009 by Pearson Higher Education, Inc.

Upper Saddle River, New Jersey 07458
Digital Fundamentals, Tenth Edition All rights reserved.
Thomas L. Floyd
Open-Collector Output
 Missing a transistor internally, so
you must provide an external
pull-up resistor.
 Allows for the use of higher-than-
usual voltages and currents.
 Allows a trick called “wired-AND,”
which means you can AND the
outputs of two chips by tying them
directly together. (Never tie totem-
pole outputs together.)
279
TTL inverter with open-collector output.

Copyright ©2009 by Pearson Higher Education, Inc.

Upper Saddle River, New Jersey 07458
Digital Fundamentals, Tenth Edition All rights reserved.
Thomas L. Floyd
Open-collector symbol in an inverter.

Copyright ©2009 by Pearson Higher Education, Inc.

Upper Saddle River, New Jersey 07458
Digital Fundamentals, Tenth Edition All rights reserved.
Thomas L. Floyd
Some Three-State Chips

 74251 (Data Selectors/Multiplexers with 3-

State Outputs)

 74LS348 (8-Line To 3-Line Priority

Encoders With 3-State Outputs)
A CMOS inverter circuit.

Copyright ©2009 by Pearson Higher Education, Inc.

Upper Saddle River, New Jersey 07458
Digital Fundamentals, Tenth Edition All rights reserved.
Thomas L. Floyd
Three Kinds of CMOS Outputs

 Like TTL chips, CMOS chips can

have two kinds of special-purpose
outputs instead of the usual
outputs:
– Open-drain
● Similar to open-collector in TTL
● Requires an external pull-up resistor
– Three-state
Characteristics of Logic
Families

11. Interfacing
Interfacing Logic Families
 We’ve seen that different logic families
have different voltage and current
specifications.

 These differences can cause problems when

you connect a gate from one family to a
gate from another family.
Interfacing Example: TTL to CMOS
 A TTL HIGH output may be as low as 2.4 V.
 But a CMOS input expects HIGHs to be at
least 3.33 V.
 Solution: use a pull-up resistor, as shown
in Figure.
Interfacing Example: CMOS to TTL
 A CMOS LOW output can only sink 0.51 mA.
 But a TTL LOW input may source as much as
1.6 mA.
 Solution: use a CMOS buffer, as shown in
Figure.