Sai Goutham Sunkara Contact Address:Flat no: 510, Lakshmi Sai Apartments, Satrampadu, Eluru, AP, India-534007

Email:sunkarasaigoutham@[Link] Mobile number:919948299888

Career Vision:To gain deep expertise in both PC technology as well as in systems on a chip (SoCs) that combine various kinds of special-function circuitry on a single piece of silicon. Research Interests:- Simulation, modeling, and design of analog/RF CMOS circuits, VLSI design and verification Education:National Institute of Technology Warangal, Warangal, INDIA (July 2009 -2013) Bachelor of Technology, Department of Electronics and Communication Engineer Current CPI : 8.59/10 (Upto 6th Semester) Rank:- 7 out of 130 Expected Graduation Date: May 2013 Sri Chaitanya Junior College, Hyderabad, INDIA March 2009 Class XII, Intermediate Public Examination, Board of Intermediate Education, Andhra Pradesh Percentage of Marks Scored : 95.5% Bashyam Public School, Kukatpally, INDIA March 2007 Class X, SSC, Andhra Pradesh Percentage of Marks Scored : 94.3%

Awards and Honours: Received Central Sector Merit Scholarship for the years (2009-2013) for being among top 0.02% of 10 lakh students that wrote All India Engineering Entrance Exam (AIEEE-2009) Awarded State Board of Intermediate scholarship for excellent academic performance in High School in 2007 Honoured with Pratibha award from State Government of AndhraPradesh for outstanding performance in 10th Grade. Relevant Experience: Three months of industrial training in summer (2012) at Maven Silicon , a premier VLSI training institute in INDIA. ------ was trained on the advanced design methodologies and various verification technologies. Developed and verified a data Encryption-decryption module of an IC intended for wireless communications to secure the data transferred . Later this module was integrated into a chip and I got firsthand experience on chip level integration. Currently working on improving Power Supply Rejection Ratio (PSRR) to -80db for Low drop out voltage regulators, that are ubiquitous in all battery driven devices. -------- In order to obtain good performance on PSRR, a full differential folded cascode structure error amplifier is used, which also increases the precision of the LDO. A transient enhancement circuit unit (TEU) is used in the LDO to achieve a good transient response performance LDO structure is implemented and simulated with CADENCE using a standard 0.18 m CMOS process.

Designed and carried out layout simulation of Low power sample and hold circuit with a high sampling rate 20MHz to meet the low power (1mW) demands of high-speed Videorate applications(2011) ---------- Since the open loop architecture is found to be the best for Videorate applications, it has been implemented in this project. The buffer amplifier incorporated in the open loop architecture is a folded cascode amplifier meeting the slew rate and unity gain requirement for better settling performance of the sample and hold circuit. This sample and hold circuit design can be employed in 10 bit 20MSPS pipelined ADC for Videorate application. The Power Dissipation is found to be 1mW and hence it is well suited for low power, high-speed Videorate application. The layout area is 0.29 [Link] A thesis on VCO based Sigma Delta Analog to Digital Converter ADC which uses Continuous time Sigma Delta modulator is used which does second orer nose shaping using Voltage Controlled Oscillator as integrator ------------ In this thesis, the ADCs requirements for Position Emission RTomography are investigated. Some of the VCO based architectures present in the literature were studied and new architecture is implemented here and compared with the previous architectures present in the literature. The architecture used in this project is giving better results when compared to previous architectures . Project on Wireless RF controlled land rover with commands on LCD in VHDL language --------- This project Wireless RF controlled land rover with commands showing on LCD display is configured into a Xilinx spartan FPGA device . In this project I used a land rover with a FPGA board and a peripheral or supporting board to receive RF signal, detect pressed key and motor driving. A wireless RF transmitter is used which gives this rover flexibility to work from a distance of 50mt. to 100 mt. range without line of sight condition, that means signal can be transmitted through walls and operate rover can be operated from a room to any other area.

Academic/cocurricular projects: Skills: presented an idea Fingerprint Identification system in NIOS design contest that was selected among top 15 designs in India. (2011) developed a novel parallelization algorithm for Advanced Encryption Scheme ( AES) and modified whole architecture of traditional AES to achieve better speeds (roughly double). designed a practical module, Low cost camera activator using opamps (2010) and received applauds for its cost effectiveness. developed a very robust code for SPEAKER RECOGNITION that could identify the speaker even in very unfavorable conditions. Languages:- VHDL, Verilog, AHDL , C, C++ , Design Tools:- Cadence, Tanner, SPICE, PSPICE

Extra curricular activities: Member of Aashayam team, a student initiative program that aims at eliminating illiteracy from India. Member of an institution named VOICE which offers Vedic spiritual solutions to modern day problems and had participated in many debates, dramas, seminars and group discussions. (2010-2012) Successfully completed Personality development courses like Positive Thinker and pursuing Self Manager, proactive leader courses conducted by VOICE and underwent YOGA training (an ancient spiritual art) during the sophomore days at NITW.(2010-12) Declaration:- I hereby declare that all the information provided here is true to the best of my knowledge and belief.