VLSI Design I
Design for Test
Hes dead Jim...
Overview design for test architectures adbuiltad-hoc, scan based, built-in Goal: You are familiar with testability metrics and adscanyou know ad-hoc test structures as well as scanbased test structures. Built in test structures as BILBO and boundary scan can be applied.
MicroLab, VLSI-23 (1/24)
JMM v1.3
Design For Test
What can we do to increase testability? increase observability add more pins (?!) add small probe bus, selectively enable different values onto bus use a hash function to compress a sequence of values (e.g., the values of a bus over many clock cycles) into a readsmall number of bits for later read-out readcheap read-out of all state information increase controllability subuse muxes to isolate sub-modules and select sources of test data as inputs provide easy setup of internal state Design strategies for test (design for testability): adad-hoc testing scanscan-based approaches selfbuiltself-test and built-in testing
MicroLab, VLSI-23 (2/24)
JMM v1.3
AdAd-hoc testing #1
AdAd-hoc test techniques are a collection of ideas aimed at reducing the test time. Common techniques are:
partitioning large sequential circuits adding test points adding multiplexers providing for easy state access
& =1
co3 Q3 co2
load test 1 0
& =1
co3 Q3 co2 Q2 co1
. . .
load test & test load test 1 0 & =1 1 0 & =1
co3 Q3 co2 Q2 co1 Q1 co0 Q0
& =1
load test 1 0
& =1
Q2 co1
test
& =1
load 1 0
& =1
load test 1 0
& =1
Q1 co0
test
Q1 co0 Q0
test
vdd
& =1
vdd load
1 0
& =1
vdd load
1 0
& =1
Q0 halfhalf-adder
MicroLab, VLSI-23 (3/24)
JMM v1.3
AdAd-hoc testing
#2
bus oriented test technique
bus unit 1 unit 2 unit 3 unit 4
multiplexer based testing
A inp 1 0 1 0 Module B B control Module A Module B B inp Module A Module B
A control Module A
0 1 A out test1 test1 test2 test2
0 B out
Module A test: {test1,test2}={0,1}
MicroLab, VLSI-23 (4/24)
JMM v1.3
ScanScan-based test techniques #1
Idea: Idea: have a mode in which all registers are chained into one giant shift register which can be loaded/ readread-out bit serially. Test remaining (combinational) logic by (1) in test mode, shift in new values for all register bits thus setting up the inputs to the combinational logic (2) clock the circuit once in normal mode, latching the outputs of the combinational logic back into the registers (3) in test mode, shift out the values of all register bits and compare against expected results. One can shift in new test values at the same time (i.e., combine steps 1 and 3).
. . . scanscan-out D Q clk normal/test 1 0 D Q
CL
shift out
1 0
QQ DD QQ DD clk clk clk clk
shift in normal/test
clk scanscan-in normal/test
MicroLab, VLSI-23 (5/24)
JMM v1.3
ScanScan-based test techniques #2
serial scan
scanscan-out DD QQ DD QQ clk clk clk clk scanscan-in CL1 DD QQ DD QQ clk clk clk clk CL2 DD QQ DD QQ clk clk clk clk
Scan registers
serial scan chain
partial serial scan: sometimes it is not area and speed efficient to implement scan in every location where a register is used (signal processing)
R1 CL R2 CL R5 R6 R3
MicroLab, VLSI-23 (6/24)
JMM v1.3
CL
R4 CL
Level sensitive scan design
A popular approach is the level sensitive scan design technique from T.W. Williams (LSSD)
the circuit is level sensitive (steady state response is independent of circuit and wire delays within a circuit): hazard free each register may be converted to a serial shift register
D T C 1 I A L1 D B L2 T2 reg A
D C I A D C I A D C I A B D C I A D C I A D C I A
reg B
B
Comb logic
shiftshift-clk c1 serial data in
c1 shiftshift-clk c2
shift data into reg A
normal operation
shift reg B out
MicroLab, VLSI-23 (7/24)
JMM v1.3
serial data out
c2
Scan Elements
LSSD
D C I A D T C 1 I A L1 & & & & L1 & & T1 D D B L2 & & L2 & & T2 T2
scan FF
D TI
1 0 TE
D Q clk clka
TE D TE TI TE
JMM v1.3
clkb clka clka clkb
clkb
clkb clka
MicroLab, VLSI-23 (8/24)
SelfSelf-Test Techniques: BILBO
ScanProblem: Scan-based approach is great for testing combinational logic but can be impractical when trying to test memory blocks, etc. because because fault of the number of separate test values required to get adequate fault coverage. onSolution: use on-chip circuitry to generate test data powerand check the results. Can be used at every power-on to verify correct operation!
1 0
circuit under test
normal/test FSM A FSM B okay
pseudoGenerate pseudo-random data for most circuits by using, e.g., a linear feedback shift register (LFSR). Memory tests use more systematic FSMs to create ADDR and DATA patterns.
pseudoFor pseudo-random input data simply compute some hash of output values and compare against expected value (signature) at end of test. Memory data can be cycle-bychecked cycle-by-cycle.
MicroLab, VLSI-23 (9/24)
JMM v1.3
Linear Feedback Shift Register (LFSR)
If Cis are not programmable, can eliminate AND gates and some XOR gates... =1 & c1 D Q clk =1 & c2 D Q clk =1 & c3 D Q clk .... =1 & cn-1 D Q clk cn D Q clk &
1 + c1 x + c 2 x 2 + c3 x 3
cn1 x n1 + cn x n
with a small number of XOR gates the cycle time is very fast. Cycle through fixed sequence ns). of states (can be as long as 2n-1 for some ns). moduloHandy for large modulo-n counters. different responses for different initial states different responses for different ci pseudopseudo-random sequence generator (PRSG)
MicroLab, VLSI-23 (10/24)
JMM v1.3
Signature Analysis
signature analysis is used to compact a data stream into a so called signature welldifferent responses for different ci, many wellknown CRC (cyclic redundancy check) polynomials s. correspond to a specific choice of cis. serial in
=1 & c1 D Q clk =1 & c2 D Q clk =1 & c3 D Q clk .... =1 & cn-1 D Q clk cn D Q clk & D Q clk qn-1 zn
MicroLab, VLSI-23 (11/24)
JMM v1.3
=1
parallel in
=1 & c1 =1 D Q clk z1 q1 z2 =1 =1 & c2 D Q clk q2 zn-1 . . . . =1 =1 Cn-1 D Q clk =1 &
qn
LFSR Polynomials
polynomials for maximal long sequences for n equal 1 up to 32 n 1,2,3,4,6,7,15,22 5,11,21,29 10,17,20,25,28,31 9 23 18 8 12 13 14,16 19,27 24 26 30 32 examples of CRCs n 8 16
JMM v1.3
f(x) 1+x+x 1+x+xn 1+x2+xn 1+x3+xn 1+x4+xn 1+x5+xn 1+x7+xn 1+x2+x3+x4+xn 1+x+x4+x6+xn 1+x+x3+x4+xn 1+x3+x4+x5+xn 1+x+x2+x5+xn 1+x+x2+x7+xn 1+x+x2+x6+xn 1+x+x2+x23+xn 1+x+x2+x22+xn CRC 1+x+x4+x5+x7+x8 1+x2+x15+x16 MicroLab, VLSI-23 (12/24)
BILBO
#1
builtbuiltVery popular built-in test structure is the built-in logic block observation (BILBO) from Koenemann BILBO operate in 4 different modes
parallel register mode BILBO register mode PRSG or signature analysis mode BILBO PRSG mode BILBO scan mode reset mode BILBO reset mode
normal operation of circuit
BILBO register mode BILBO signature analysis mode BILBO scan mode BILBO reset mode
MicroLab, VLSI-23 (13/24)
normal operation of circuit
scan mode mode
normal operation of circuit
normal operation of circuit
JMM v1.3
BILBO
#2
example of a BILBO element with polynomials 1+x+x4
c1 c0 scan in 0 1 D0 & D1 & D2 & D3 scan out Q clk Q4 & Q clk Q3 & =1 D
MicroLab, VLSI-23 (14/24)
JMM v1.3
&
=1 D
Q clk Q1
&
=1 D
Q clk Q2
&
=1 D
=1
mode A B C D
c1 c0 0 1 0 1 0 0 1 1
function scan mode reset PRSG or signature analyzer parallel registers
IDDQ Testing
A-meter (measures IDD) met VDD
GND
Idea: CMOS logic should draw no current when its not switching. So after initializing tricircuit to eliminate tri-state fights, disable pseudopowerpseudo-NMOS gates, etc., the power-supply current should be zero after all signals have settled. Good for detecting bridging faults (shorts). May want to try several different circuit states to ensure all parts of the chip have been observed.
MicroLab, VLSI-23 (15/24)
JMM v1.3
SystemSystem-Level Test: Boundary Scan
The IEEE 1149.1 boundary scan architecture provides a standardized serial scan path through the I/O pins of a chip (also called JTAG) at the board level, chips obeying the standard may be connected in a variety of series and parallel combinations for board testing (replacing bead of nails) standardized tests:
connectivity tests between components sampling and setting chip I/Os selfbuilt-indistribution an collection of self-test or built-in-test results
PCB interconnect
serial test interconnect
IO pad and boundary cell
serial data in
JMM v1.3
serial data out
MicroLab, VLSI-23 (16/24)
Boundary Scan: Test Access Port
The test access port (TAP) is a definition of the interface that needs to be included in an IC
TCK: test clock input TMS: test mode select TDI: test date input TDO: test data output TRST: optional signal for asynchronous reset the TAP
the test architecture
test data registers TDI instruction decode instruction registers clocks/control TCK TMS (TRST)
JMM v1.3
0 1
TDO
TAP controller
MicroLab, VLSI-23 (17/24)
Boundary Scan: TAP controller
State machine for the TAP controller. TMS is the control signal.
test1 test-logic reset 0 1 run0 run-test/idle 1
select-DRselect-DR-scan 0 capturecapture-DR 0 shiftshift-DR 1 exit1exit1-DR 0 pausepause-DR 0 1 exit2exit2-DR 1 updateupdate-DR 1 0 0
select-IRselect-IR-scan 1 0 capturecapture-IR 0 shiftshift-IR 1 exit1exit1-IR 0 pausepause-IR 0 1 exit2exit2-IR 1 updateupdate-IR 1 0
0 1 0
1 0
MicroLab, VLSI-23 (18/24)
JMM v1.3
BoundaryBoundary-scan: IR
Instruction register (IR): minimum 2 bits
to next IR bit data from last cell 0 1 shiftIR clockIR D clk updateIR TRST reset & Q D clk Q IR bit
FSM state shiftIR clockIR updateIR
capture- shiftcapture-IR shift-IR
exit1pauseexit2- updateexit1-IR pause-IR exit2-IR update-IR
MicroLab, VLSI-23 (19/24)
JMM v1.3
BoundaryBoundary-scan: DR
TAP data register (DR)
boundary scan registers TDI internal data register bypass register (1 bit) TDO
boundary scan register is a special case of a data register. It allows circuit board interconnections to be tested, external components tested, and the state of the chip digital I/Os to be sampled. The boundary scan register is mandatory. internal data registers are optional and add additional access to the circuit. the bypass register is a 1 bit register used to bypass a whole chip.
MicroLab, VLSI-23 (20/24)
JMM v1.3
BoundaryBoundary-scan: DR
boundary scan input and output cells
out PAD last cell from chip last cell next cell 0 1
shiftDR mode
D Q
clockDR
D Q clk
mode
0 1
to chip
clk
updateDR
next cell 0 1
shiftDR
D Q
clockDR
D Q clk
0 1
out PAD
clk
updateDR
biboundary scan bi-directional cell
next cell
enable
0 1
shiftDR
D Q
clockDR
D Q clk
0 1
clk
updateDR
from chip
0 1
shiftDR
D Q
clockDR
D Q clk
0 1
bidir PAD
clk
updateDR
0 1
last cell shiftDR
D Q clk
clockDR
D Q clk
0 1
to chip
JMM v1.3
updateDR
MicroLab, VLSI-23 (21/24)
Boundary scan: instructions
Minimum 3 instructions
Bypass (all 0): it is used to bypass any serial data registers in a chip with a 1 bit register. This allows serialspecific chips to be tested in a serial-scan chain without having to shift through the accumulated SR stages in all the chips Extest (all 1): testing of off chip circuitry sample/preload: places the boundary scan registers (at the chips I/O pins) in the DR chain, and samples or preloads the chips I/Os
optional recommended instructions:
Intest: singleIntest: single-step testing of internal circuitry via the boundary scan registers Runbist: selfRunbist: run internal self-testing procedures within a chip
MicroLab, VLSI-23 (22/24)
JMM v1.3
Coming Up...
Next time: Top down design. Hardware description languages, logic synthesis. Readings Weste: Weste:
(adscan7.3 through [Link] (ad-hoc & scan-based testing) 7.3.4 through [Link] (BILBO) (Iddq 7.3.5 (Iddq testing) 7.5 (boundary scan)
MicroLab, VLSI-23 (23/24)
JMM v1.3
VLSIExercises: VLSI-22
pseudoEx vlsi22.1 (difficulty: easy): calculate the pseudorandom sequence of an LFSR with the implemented polynomial 1+x+x3 use the start value x=1 Result: 1,3,7,6,5,2,4,1,...
MicroLab, VLSI-23 (24/24)
JMM v1.3
