CPS 104 Computer Organization and Programming Lecture- 18: Memory Elements, Busses, Registers
Feb 18, 2004 Gershon Kedem [Link]
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Homework-3 Due Feb. 23rd 11:59 pm. C++ version is posted. Start NOW!
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Memory Elements
All the circuit we looked at so far are combinational circuits: the output is a Boolean function of the inputs. We need circuits that can remember values. (registers) The output of the circuit is a function of the input AND a function of a stored values (state) . Circuits with memory are called sequential circuits.
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Rest-Set Latch
S Q
Q R
R 0 0 1 1
S 0 1 0 1
Q Q 1 0 -
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Rest-Set Latch (cont.)
0 1 0
S0 Q
1
1 0
Q R
0 1 0
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Rest-Set Latch (cont.)
S1
1
S Q
0 1 0
0 1
Q R
1 0 1
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Positive Edge Data-Latch
Data
Q Enable Q
D 0 1 -
E 1 1 0
Q 0 1 Q
D E
Q
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Time
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Data
Negative Edge D-Latch
Q
Enable Q
D 0 1 -
E 1 1 0
Q 0 1 Q
E Q Time
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Master-Slave Data-Flip-Flop
Data
Master
Slave
Q
Clock
t
On C
D is transferred to the master stage and the slave is stable.
On C the Master stage is transferred into the slave stage (output), and the master stage is stable.
GK Spring 2004
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DFF Timing
Data Q M Q
Clock
Clock
1 0 0 1 0 1 1 0
M
1 0 0 1 0 1 1 0
Time
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Tri-State Driver
The Tri-State driver is like a (one directional) switch: u When the Enable is on (E=1) it transfers the input to the output. u When the Enable is off (E=0) it disconnects the output.
E D Q
D 0 1 -
E 1 1 0
Q 0 1 Z
Z :- High Impedance
E
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Bus Connections
The Bus: Many to many connections. Mutual exclusion: At most one Enable is on!
Dn-1 En-1 En-2
Dn-2 E1
D1 E0
D0
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Register Cells on a bus
Q D
Q D
Q D
Q D
D latch WE
Q
D latch WE
Q
D latch WE
Q
D latch WE
Q
RE
RE
RE
RE
One can source and sink from any cell on the bus by activating the right controls (WE and RE).
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3-Port Register Cell
Data-In
Bus-C Bus-B
Q
Bus-A
DinEnable OutA OutB
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3-Port Register
EC EA EB
Bus-C Bus-B
Q
Bit-2
Q
Bus-A Bus-C Bus-B
Q
Bit-1
Q
Bus-A Bus-C Bus-B
Q
Bit-0
Q
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Bus-A
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Address Decode circuit
Data-In
Bus-C Bus-B
Q
Register address: 01
Q
Bus-A
DinEnable OutA OutB
A0 A1 EA B0 B1 EB C0 C1
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Register File
Reg-3
One-bit Cell
Reg-2
One-bit Cell
Reg-1
One-bit Cell
Reg-0
A3
One-bit Cell
B3 C3 A2 B2 C2 A1 B1 C1 A0 B0 C0
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
One-bit Cell
A-En Add-A1 Add-A0 B-En Add-B1 Add-B0 C-En Add-C1 GK Spring 2004 Add-C0
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Summary
So far we saw how to take a Boolean function and generate a circuit that realize the function. We learned to construct circuits that can add and subtract. We learned about the ALU: a circuit that can add, subtract, detect overflow, compare, and do bit-wise operations (AND, OR, NOT) Saw how to construct a shifter circuit. Learned about the memory elements: RS-Latch, D-Latches and D-Flip-flops. Learned about Tri-State drivers and BUS Communication. (many-to many) Learned about how to construct a register file. Saw how control signals can modify what the circuit will do with inputs. u Examples: ALU, Shift, Register read-write, ...
GK Spring 2004
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The Big Picture: Where are We Now?
The Five Classic Components of a Computer
Processor Input Control Memory Datapath
Output
Todays Topic: Datapath Design
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Review: The MIPS Instruction Formats
All MIPS instructions are 32 bits long. The three instruction formats:
31
u
26 op 6 bits rs 5 bits 26 op 6 bits rs 5 bits 26 op 6 bits
21 rt 5 bits 21 rt 5 bits
16 rd 5 bits 16
11 shamt 5 bits
6 funct 6 bits
R-type I-type J-type
31
0 immediate 16 bits 0
31
target address 26 bits
The different fields are: u op: operation of the instruction u rs, rt, rd: the source and destination register specifiers u shamt: shift amount u funct: selects the variant of the operation in the op field u address / immediate: address offset or immediate value u target address: target address of the jump instruction
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The MIPS Subset (We cant do them all!)
31
26
21
16
11 shamt 5 bits
6 funct 6 bits
ADD and subtract op rs rt rd u add rd, rs, rt 6 bits 5 bits 5 bits 5 bits u sub rd, rs, rt 31 26 21 16 OR Immediate: op rs rt u ori rt, rs, imm16 6 bits 5 bits 5 bits LOAD and STORE u lw rt, rs, imm16 u sw rt, rs, imm16 BRANCH: u beq rs, rt, imm16 JUMP: u j target
31 26 op 6 bits target address 26 bits
0 immediate 16 bits
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The Hardware Program
Instruction
How does one build hardware that implements the MIPS instructions?
Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction
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The Steps of Designing a Processor
Instruction Set Architecture => Register Transfer Language Register Transfer Language => u Datapath components u Datapath interconnect Datapath components => Control signals Control signals => Control logic
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RTL: The ADD Instruction
add rd, rs, rt
u
mem[PC] R[rd] <- R[rs] + R[rt] PC <- PC + 4
Fetch the instruction from memory The ADD operation
Calculate the next instructions address
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RTL: The Load Instruction
lw
u
rt, rs, imm16 mem[PC] Fetch the instruction from memory
Addr <- R[rs] + SignExt(imm16) Calculate the memory address R[rt] <- Mem[Addr] PC <- PC + 4 Load the data into the register
Calculate the next instructions address
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Combinational Logic Elements (Basic Building Blocks)
CarryIn A
32
Adder
Adder
B 32 Select A B 32 32 OP A 32
32
Sum Carry
MUX
MUX ALU
32
ALU
B
32
Result Zero
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32
