Title:-
Nanoscale Devices For Low Power VLSI Design Abstract
In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, sub threshold device design has gained a lot of attention due to the low power and ultra-lowpower consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1m. In deep-sub micrometer regimes leakage current becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components especially gate leakage is very important for estimation and reduction of leakage power, especially for low-power applications. This proposed research topic explores various transistor intrinsic leakage mechanisms, including gate leakage, and gate oxide tunneling and explores techniques to reduce the leakage power consumption and also circuit level implementation to reduced gate leakage current with aid of TCAD software working in the submicron and deep submicron region of CMOS devices separately.
Introduction
Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) has been the major device for integrated circuits over the past two decades. With technology advancement and the high scalability of the device structure, silicon MOSFET based VLSI circuits have continually delivered performance gain and cost reduction to semiconductor chips for data processing and memory functions. A lot of research has gone into device design over the last thirty years, but the evolution of process technologies brings new obstacles as well as new opportunities to device designers. Continuous CMOS scaling has been the main driving factor of silicon technology advancement to improve the performance. Design of low power high-performance CMOS devices and circuits is a big challenge. The process parameters in low power design are channel length, oxide thickness, threshold voltage, and doping concentration in the channel. As the technology is scaled down, process parameter variations have become severe problem for lowpower design. The low-power design technique should be such that it is less sensitive to the process parameter variations. As technology scales down, the variations of these process parameters are expected to be significant in future generations. As a result, the yield of the circuit will be less. The variation of leakage power and delay in the transistors on a given die are
different for different low-power design techniques. The role of threshold voltage (Vth) and sub threshold swing (S) has become increasingly important with VLSI applications emphasizing on low voltage, low-power, and high-speed design. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 m. The dependence of Vth on channel length is stronger as compared to other factors that also cause Vth fluctuation at small device dimension such as random dopant distribution. The gate oxide thickness in recent process technologies has approached the limit when direct tunneling starts to play a significant role in both off-state and on-state MOSFET transistor operation modes. This phenomenon, in addition to sub-threshold leakage, results in dramatic total standby leakage power dissipation. Thus, better design strategies to control the total leakage power are necessary. It is well known that gate tunneling currents are highly sensitive to the voltage variation across the gate oxide. Supply voltage attenuation can give significant reduction in VLSI Design gate leakage power consumption. Circuit design techniques to mitigate the impact of gate leakage would be much less efficient than the use of high-k material since gate leakage is a stronger function of process-induced oxide thickness fluctuation as compared to change in Vdd and threshold voltage. In addition to the gate-oxide scaling issue, higher doping concentrations would degrade sub-threshold swing (S). Furthermore, Vdd scaling necessitates threshold voltage (Vth) reduction, which exponentially increases IOFF. IOFF reduction is critical where chips are often in standby mode of operation, and even during active operation, acceptable IOFF is required since leakage power consumption is rapidly increasing at a much faster rate compared to dynamic power. Few front ends of line challenges faced by transistors in the deep submicron and ultra deep submicron region include diminishing Vgs Vth, larger Vth/Vdd, thin junctions drive dopant levels to saturation, dopant loss and statistical dopant fluctuation on small geometry devices increase device variability, and increase in channel doping concentration to control DIBL reduces carrier mobility while increasing body effect, gate oxide scaling slowing as it approaches the monolayer thickness of SiO2.This proposed research topic is divided into main sections. Section 1 Discusses the CMOS scaling trends facing the challenges due to the feature size, supply voltage, threshold voltage, and oxide thickness. Section 2 Focuses on the limitations of technology scaling, especially on gate leakages and Section 3 Therefore the potential solutions to be sought to face the above challenges. Section 4 Also gives the complete roadmap to device designers.
