Foundation for Innovation and Technology Transfer, IIT Delhi
invites you to a workshop on Design Experiences in Silicon
IIT Delhi, April 29, 200
The seminars will cover possible ways in which mistakes can be overlooked and ways in which
they could be debugged in silicon. Real examples will be used to give an idea of 'clever' mistakes
that a designer could overlook. Rapidly reducing supply voltages and non-proportional changes in
transistor parameters pose big challenges for analog designs in deep sub-micron technologies. This,
in conjunction with ever increasing performance demands force numerous trade-offs irrespective of
whether the circuit is operating at ! or at high fre"uency. #mplementation trade-offs will be
examined using case studies. $hrinking dimensions have led to novel concepts at all levels of
design, from the architectural level to the physical levels of layout and mask generation. %uidelines
and prevalent practices of esign for &anufacturability will also be discussed.
Invited Spea!ers fro" the Industry include
Mr. Rajat Gupta, Beceem Communications, Bangalore
Rajat %upta is &anaging irector of 'eceem !ommunications (vt. )td. , and was formerly &anaging
irector of !ypress $emiconductors #ndia, and earlier, *( Technology evelopment at +rcus Technology
(vt. )td., +t +rcus, Rajat developed embedded microprocessors, analog , mixed signal design technology
in-house to enable +rcus to address the emerging mixed-signal #( market.
Dr. Kaushik Saha, ST Microelectronics, Noida
r. -aushik $aha is currently &anager of the #ndia unit of the +dvanced $ystems Technologies group of
$T&icroelectronics. The group is involved in research and development of future generations of devices and
systems planned by the company for the markets of tomorrow. .is research interests are in the areas of
+dvanced (rocessor +rchitectures and (arallel +lgorithms , +rchitectures for igital $ignal (rocessing
+pplications and he holds various patents in these areas.
Mr. Mohandas .S., C!press Semiconductor, Bangalore
&ohandas.(.$. formerly worked as a design engineer on analog building blocks in +rcus technologies,
'angalore. .e has been working in !ypress semiconductors, 'angalore for the last / years on analog designs
such as ())s, trans-impedance amplifiers, voltage references, voltage regulators etc. .is recent work
involves clock chip designs for (!s as well as the design of sigma delta +!s for microcontrollers. .e holds
0 issued patents in the area of analog design with 1 applications pending with 2$ (T3.
Mr. D. ". #. Ra$ikumar, National Semiconductor, Bangalore
*4 Ravi -umar holds a &asters degree in &icro-electronics from #T-'.2 and has 51 years of industry
experience, including /.6 years at 7ational $emiconductor !orporation. (rior to working at 7ational, Ravi
has worked for $T&icroelectronics, (hilips $emiconductors, and Tritech &icro-electronics. .e has
experience with a host of analog systems including 3versampled convertors, ())'s , ())'#$T, #ntegrated
!&3$ *oltage Regulators, R8#, and isk drive electronics. .e holds 0 2$ patents , an additional 9 are in
the process.
ro%. #a!ade$a, Ms. Sudeshna Guha, Mr. " Girish, Mr. &noop C Nair
will present the design experiences, methodology followed and the issues faced in the first student
designs taped out from ##T elhi.
#egistration $on or %efore April 20&
Academia Industry
Non-IEEE Members Rs 2500/- Rs 000/-
IEEE Members with va!id I" Rs 2250/- Rs 2#50/-
After April 20, the registration fee 'ill %e a (at #s) *000 for all participants)
$he re%istration &ee wi!! is payab!e by che'ue or dra&t in &avour o& ()I$$* II$ "e!hi+
For #egistration please contact+
,r) -tta" As'al, FITT + 2.9 /01, 9220 2.2*/ $utta"as'al3hot"ail)co"&
Re%istration )orm "own!oad the &orm here
For ,ore Infor"ation 4lease 5ontact+
Mr, Anoop Nair - ./#0 .01.0
2anoopcnair3%mai!,com4
Mr, 5, 6irish - .505 /550#7 2%irish,v%!3%mai!,com4
E!ectrica! En%ineerin% "epartment
II$ "e!hi* 8au9 :has* New "e!hi,
;hone- 215. 00/#* 215. 1007 )a<- 215/021=
