EECS 105 Spring 2004, Lecture 30

Lecture 30:

Prof J. S. Smith

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Context
In todays lecture, by request, we will
look at more single transistor active
circuits and example problems, and
start multi-stage amplifiers

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Reading
z

We are starting on chapter 9, multi-stage amplifiers

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Lecture Outline
z
z
z

LED driver
Peak detector
CS amplifier with active pullup

z
z
z
z
z

Department of EECS

small signal model

Frequency response

Transimpedance Amplifier
Source Follower
Current Mirror
Push-Pull Amplifier
Multistage Amplifiers
University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Example: turn on an LED

z

z
z

In this example, we have a low power CMOS

output, 0-3 volts, and we want to turn on an LED
when the output goes high
Use a NPN bipolar discrete transistor.
First cut:
Problem: The transistor will go into
saturation, drawing too much current
from the CMOS output
Problem: The current through the LED
will not be limited, and it will burn out

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Put in a current limiting resistor

First, limit the current through the LED. The voltage
drop across the resistor will be about 5 volts 1.7
volts3.3 volts, so if we want a current of 10
milliamps through the LED, pick a resistor of 330
5 volts
ohms
The transistor will still
saturate, pulling too much
current from the CMOS

R=330 ohms

If the beta of our transistor

Is about 100, then we would
Like a current of about 100
Microamps into the base

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Put in a base resistor

If the voltage from the CMOS output is 5 volts when
the output is high, the voltage drop from the base to
the emitter is about .7 volts, and we want 100
microamps of current, so put in a 50 kilo-ohm
5 volts
resistor
The resistor limits the current
Into the base, limiting the current
draw from the CMOS output
50 Kohms

R=330 ohms

If you want to be sure the

transistor stays out of
saturation, pick a larger base
resistor, (remember beta may
vary!)

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Example: find the peak of a signal

z

In a communication circuit, you may not know the

strength of a signal, so to detect data you need to
scale your trigger by the peak value of the signal.
A simple peak detector:
Problem: the sample voltage
will be .7 volts below the peak
Problem: If there is a noise
spike, the peak will be too high
for a long time

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Example: pull down and current limit

z

Put in a pull down resistor to let the detected

voltage decay in an R2C time, and a current limiting
resistor to limit the pull up for short spikes. We
will want R2C>> the bit time, and R1<<R2
R1

+
R2

Vout

Problem: the sample voltage

will still be .7 volts below the peak,
And this circuit might load the input
too much
Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Put in a voltage follower

z

Lets put in a voltage follower, a common drain FET

amplifier. The input is no longer loaded, and the voltage
detected is close to the input peak, but not very accurate at
low voltages. (if we used a common drain BJT, we would
be closer to the input voltage). We will need R3<R1
+V

R3

R1

R2
We will do this better
later with a two stage C
amplifier and negative
feedback

Vout

We probably also need another voltage follower at the output

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Example: active pullup CS amplifier

z
z
z

Begin the analysis by replacing M2 with a resistor of value 1/gm2

Replace M1 with a current source of value gm1vin
Note that this approach assumes:

1/gm2 << ro
Low frequency operation
the body effect can be neglected in both transistors.

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Small Signal Analysis

The amplifier gain is the ratio of the ss output voltage to the ss input
voltage:
i 1g
v
g
Av = out = d
= m1
1
vin
id g
gm2
m2

m1

Taking into account the finite resistance of the FET (ro) gives:
1
ro1 ro 2
v
g m1
g
Av = out =
=

1
vin
g m 2 + r 1r
g
m2

o1

Department of EECS

o2

m1

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Frequency Response
To find the frequency response of the active pull up common source
Amplifier, we need to put in the parasitic capacitances:

Use the Miller approximation to convert the GD capacitance to

separate capacitances at the input and output
Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

CS Amplifier: Frequency Response

Figure 22.5
z

Frequency dependence at the amplifier input

p in =

1
RS (CMI + C gs1 )

CMI = C gd 1 1 +

g m1
gm2

Frequency dependence at the amplifier output

p out =

Department of EECS

1
2 g m 2 (C gs 2 + C MO + Cdb1 + Cdb 2 )
1

CMO = C gd 1 1 +

gm2
g m1

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Transimpedance Amplifier

Figure 22.8

The transimpedance is:

AR =

id g1
vout
W1 L3
= W3mL21 =
iin
g m 2W3 L1
id W1L3

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Source Follower
Figure 22.11

Gain:

Department of EECS

v
Av = out =
vin

1
g m1
1
g m1

1
gm 2

1
1
=
g m1
1 + g m 2 1 + WW1LL2
2 1
University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Using a Current Source as a Load

Gain is given by:

Av =
z

2 1
g m1
=
1
1
(1 + 2 ) I D
ro1 + ro 2

Notice that the gain can be adjusted by changing the bias

current

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Current Mirror

Since Vgs1 = Vgs2

Department of EECS

I D 2 W2 L1
=
I D1 W1 L2

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Push-Pull Amplifier

Gain:
Av =

vout id (ro1 ro 2 )
=
= ( g m1 + g m 2 ) (ro1 ro 2 )
vin
id g1m1 g1m 2

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Multistage Amplifiers
Necessary to meet typical specifications for any of the 4 types
We have 2 flavors (NMOS, PMOS) of CS, CG, and CD and
the npn versions of CE, CB, and CC (for a BiCMOS
process)
What are the constraints?
1. Input/output resistance matching
2. DC coupling (no passive elements to block the signal)

Department of EECS

University of California, Berkeley

10

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Summary of Cascaded Amplifiers

General goals:
1. Boost the gain (except for buffers)
2. Optimize the input and output resistances:
Rin

Rout

Voltage:
Current:
Transconductance:
Transresistance:

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Start: Two-Stage Voltage Amplifier

Use two-port models to explore whether the combination
works
CS2

CS1

CS1,2

Results of new 2-port: Rin = Rin1, Rout = Rout2

Av = Gm1 ( Rin 2 || Rout1 ) ( Gm 2 Rout 2 )
Av = Gm1Gm 2 ( Rin 2 || Rout1 )( Rout 2 )
Department of EECS

University of California, Berkeley

11

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Cascading stages

CS2

CS1

CD3

Input resistance:
Voltage gain (2-port parameter):
Av = g m1 ( ro1 || roc1 ) g m 2 ( ro 2 || roc 2 )

Output resistance:
Rout =

1
g m + g mb

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Multistage Current Buffers

Are two cascaded common-base stages better than
one?
CB1

CB2

Input resistance: Rin = Rin1

Department of EECS

University of California, Berkeley

12

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Two-Port Models

Rout = Rout 2 r02 (1 + g m 2 r 2 || RS 2 ) || roc 2

Output impedance of stage #1 (large)

Rout r02 ( g m 2 r 2 ) || roc 2 = ( o ro 2 ) || roc 2

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Common-Gate

2nd

Stage

Rout = Rout 2 r02 (1 + g m 2 RS 2 ) || roc 2

Rout = Rout 2 r02 (1 + g m 2 ro1 || roc1 ) || roc 2

Department of EECS

University of California, Berkeley

13

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Second Design Issue: DC Coupling

Constraint: large inductors and capacitors are not
available
Output of one stage is directly connected to the
input of the next stage must consider DC
levels

3.2V

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

Alternative CG-CC Cascade

Use a PMOS CD Stage: DC level shifts upward

3.2V

Department of EECS

University of California, Berkeley

14

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

CG Cascade: DC Biasing
Two stages can have different supply currents
Extreme case:
IBIAS2 = 0 A

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

CG Cascade: Sharing a Supply

First stage has no current
supply of its own its output
resistance is modified

Department of EECS

University of California, Berkeley

15

EECS 105 Spring 2004, Lecture 30

Prof. J. S. Smith

The Cascode Configuration

Common source / common gate
cascade is one version of a cascode
(all have shared supplies)

DC bias:

Two-port model: first stage

has no current supply of its own

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University of California, Berkeley

16