Analog IC Design

Chapter 8. Reference Circuits

Outline
8.1. Voltage Primitives
8.2. Proportional-to-Absolute-Temperature Currents
8.3. Complementary-to-Absolute-Temperature Currents
8.4. Temperature Compensation
8.5. Startup
8.6. Frequency Compensation and Noise
8.7. Bandgap References

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Analog IC Design

8.1. Voltage Primitives

Extract voltages and currents from predictable voltages.
Diode Voltage vD:
v
%
" v
V
V
i D = IS $ e 1' ISe
'
$
&
#
D

" i % KT " i %
v D Vt ln $$ D '' =
ln $$ D ''
# IS & q # IS &

Logarithm suppresses variations in diode current iD.

vD 0.60.7 V 2% at TROOM and falls 2.2 mV/C.
vD is accurate and consistent across close to five decades of current.
Breakdown Voltage vBD:
Logarithm-like response suppresses variations in current iD.
vBD(ZENER) < 5 V 2% to 4% at TROOM and falls with temperature.
vBD(AVALANCHE) > 5 V 2% to 4% at TROOM and rises with temperature.
Typically, vBD 57 V and rises +2+4 mV/C vBD is high.

GateSource Voltage vGS in Strong Inversion:

"W%
i DS 0.5$ ' K' v GS v T
#L&

v GS = v T +

2i DS
v T + VDS(SAT)
K'(W/L)

Square root suppresses variations in drainsource current iDS.

vT 100150 mV, K' 20%, and both fall with temperature.
vGS 5% to 10% at TROOM Less accurate than diode.
GateSource Voltage vGS in Subthreshold:
v

GS
"W%
i DS(SUB) $ ' IST e nVt
#L&

Where n = 1.53.

Logarithm suppresses variations in drainsource current iDS(SUB).

vGS is sensitive to noise energy in subthreshold.
Behavior of vGS is consistent across one or two decades of currents.

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Analog IC Design

8.2. Proportional-to-Absolute-Temperature Currents

Definition: Rises with temperature vPTAT and iPTAT T.
KT
Popular Example: Thermal voltage
Vt =
q
Features of Vt: Predictable, linear across temperature, consistent,
and good to cancel Vt effects gm BJT = iPTAT/Vt T/T.
vPTAT Generation: Difference of two matched, but ratioed
diode or gatesource voltages in subthreshold is PTAT.
$i I '
$i A '
v D = v D1 v D2 Vt ln && D1 S2 )) = Vt ln && D1 D2 )) = v PTAT
% A D1i D2 (
% IS1i D2 (

Where IS AD.

*
$W' , i DS1 & ) /
% L (2 /
=v
v GS = v GS1 v GS2 nVt ln ,
,$ W '
/ PTAT
, & ) i DS2 /
Where IST W/L.
+ % L (1
.

If currents, areas, and widthlength ratios match ln term is constant.

iPTAT = vPTAT/RP RP should drift little across temperature.
Poly-silicon resistances vary 20% RP requires adjustment Trimming.

A. Cross-Coupled Quad
Difference of four matched baseemitter voltages.
iR =

v BE v BE1 + v BE4 v BE3 v BE2 Vt # i1i 4 A 3A 2 & Vt

=
=
ln %
ln C2 D3 = i PTAT
(
RP
RP
R P %$ A1A 4i 3i 2 (' R P

iRB (vIN 2vBE)/RB

vIN(MIN) vRB + 2vBE (High)
Base-current error:
iB4 iB1 iO = iC4 iC2
iC2 = iPTAT iB2 < iPTAT
Voltage error: vCE1 vCE2 + vRP and vCE3 vCE4
PTAT for close to five decades of current.

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Analog IC Design

B. Latched Cells: i. BJT Cell

PTAT Generation: Difference of two matched baseemitter voltages.
Current mirror matches currents and positive feedback latches cell into PTAT state.
iR =

v BE Vt " i P1A P2 % Vt
=
ln $
ln C = i PTAT
'
RP
R P $# A P1i P2 '& R P

( )

vIN(MIN) VSD(SAT) + vBE

Base-current error:
iC1 iC2 and iC2 = iPTAT iB2 < iPTAT
Voltage error: vC1 vC2
PTAT for close to five decades of current.
Circuit is stable when: iC1 iC2 vBE/RP = iPTAT
iC1 iC2 = 0 Bi-stable
Requires a startup circuit.

Error Compensated
Replace diode connection with voltage-matching feedback loop.
vIN(MIN) Max{vSG + VCE(MIN), VSD(SAT) + vBE}
Low base-current error:
iCB1 2iCP iBB1 2iBP and iCP1 iCP2,
But iM2 = iPTAT + iBP1 > iPTAT
Low voltage error: RP' = RP, so
vSD1 vSD2 and vCE1 vCE2 vBEP1 vR
PTAT for close to five decades of current.
Bi-stable Requires a startup circuit.
Ensure + and feedback loops are stable.

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Analog IC Design

ii. CMOS Cell

PTAT Generation: Difference of two matched gatesource voltages.
Current mirror matches currents and positive feedback latches cell into PTAT state.
In Subthreshold
iR =

v GS
RP

) #W& ,
+ i P1 % ( .
nV
$ L 'P2 . nVt
=
t ln +
ln C = i PTAT
. R
R P +# W &
P
+ % ( i P2 .
* $ L 'P1 -

( )

vIN(MIN) VSD(SAT) + vGS

No base-current error.
Voltage error: vD1 vD2
PTAT for maybe two decades of current.
To operate in subthreshold:
VDS(SAT) STRONG INV 50 mV

Bi-stable Requires a startup circuit.

Less linear across temperature than BJT.

iii. Diode Cell

PTAT Generation: Difference of two matched diode voltages.
Current mirror matches currents and gate-coupled pair matches voltages.

vIN(MIN) VSD(SAT) + vGS + vD (High)

No base-current error.
Voltage error: vDM1 vDM2
PTAT for close to five decades of current.
Bi-stable Requires a startup circuit.

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Error Compensated
PTAT Generation: Difference of two matched diode voltages.
Amplifier diode-connects MM2
Mirror matches currents and feedback matches voltages.
vIN(MIN)
Max{VSD(SAT) + vD, vSG + vOA(MIN)}
No base-current error.
Low voltage error: vDM1 vDM2
PTAT for close to five decades of current.
Bi-stable Requires a startup circuit.
Ensure + and feedback loops are stable.

8.3. Complementary-to-Absolute-Temperature Currents

CTAT is the complement and counterpart to PTAT.
Definition: vCTAT and iCTAT fall with rising temperatures.
Popular Examples:
Diode voltage falls 2.2 mV/C.
Threshold voltage vT falls with temperature.
Transconductance parameter K' falls with temperature.
Feature of vCTAT: Good to cancel PTAT effects
For temperature independence sREF = sPTAT + sCTAT f(Temperature)
Benefit of Temperature-Independent Current:
Good to bias blocks Quiescent power does not rise with temperature.
iCTAT Generation: Impress diode voltage vD across a resistor.
iR =

v D Vt ! i D $
=
ln # & = i
R C R C #" IS &% CTAT

vD is not perfectly linear with temperature iCTAT is not perfectly linear.

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A. BJT and B. Diode Implementations

Use negative feedback to sample and convert a diode voltage vD into a CTAT current.
Current-Sampled BJT

Voltage-Sampled Diode

MS diodeconnects
QC.

AG diodeconnects
M M.

"T" mixes/mirrors iCTAT and iS.

AG mixes/mirrors vD and vR.

MS series-samples iCTAT.

MM series-samples/mirrors iCTAT to iO.

MMMMO mirrors iCTAT to iO.

vIN(MIN) =

vIN(MIN) vSG + VDS(SAT) + vBE (High)

Max{VSD(SAT) + vD, vSG + vOA(MIN)}

8.4. Temperature Compensation

Approach: Use PTAT behavior to cancel CTAT component.
PTAT Primitive: Thermal voltage Vt is zero at 0 K and linear with temperature.
CTAT Primitive: Diode voltage vD is VBG 1.2 V at 0 K and 0.60.7 V at 27C.

Taylor-series expansion of vD when iD = KXTX:

#V v
&
# T &
D(ROOM)
(( T1 x Vt ln %%
v D VBG %% BG
((
TROOM
$ TROOM '
$
'

Where 4 and
x is from iD = KATX.

vD has T0-, T1-, and T ln T terms vD is nonlinear with temperature.

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Compensated vD leaves bandgap voltage VBG 1.2 V.

At TROOM, vD + vPTAT VBG vPTAT 1.2 V vD(ROOM) 0.50.6 V.
Compensated reference current iREF: vPTAT cancels vD's K1T1 term.
i REF = i CTAT + i PTAT =

V
v D v D v D Vt
+
=
+
ln C BG
RC RP RC RP
RC

( )

% 1 V ( +
.
t
* ln - T 0 VBG
'
'& R C *) , TROOM 0/ R C

Nonlinearity
If:

i PTAT(ROOM) =

Vt(ROOM)
RP

( )

ln C

VBG v D(ROOM)

RC
RC

R C VBG v D(ROOM)

R P Vt(ROOM) ln C

( )

iD = iPTAT reduces vD's nonlinearity 1 in T1 corresponds to 1 in 1.

T ln T term causes curvature.
When TMIN is higher, optimal iREF' requires more iPTAT iREF' > iREF.

Design Example
Objective: What resistances produce a temperature-compensated 5-A
reference current when the diode voltage at room temperature is 0.62 V
and the area ratio of the matched diodes is eight?
Solution:
R C VBG v D(ROOM)
1.2 0.62

= 10.73
R P Vt(ROOM) ln C
26m ln 8

( ) (

RC

) ()

VBG 1.2
=
= 240 k
i REF 5

"R %
" 1 %
R P R C $$ P '' = 240k $
' = 22.4 k
# 10.73 &
# RC &

After, simulate and adjust RP or RC until iREF flattens across temperature.

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Analog IC Design

A. BJT Implementation
PTAT-to-Reference Conversion:
Use resistors across matching and mirrored vD's or vBE's
to pull matched and compensating iCTAT's from mirror.
Error-Compensated BJT Current Reference:
QP1QP2RP establishes iPTAT and
RC1 and RC2 pull matched iCTAT's
from mirror
i REF

v BE v BE
+
= i CTAT + i PTAT
RC
RP

Base currents and transistor

voltages still match: iBB 2iBP,
vSD1 vSD2, and vCE1 vCE2.

B. Diode Implementations
Error-Compensated Diode-Derived

Diode-Derived Current Reference

Current Reference

DP1DP2RP establishes iPTAT and

RC1RC2 pulls matched iCTAT's i REF

v D v D
+
= i CTAT + i PTAT .
RC RP

To relax vIN(MIN) and AG's ICMR, AG can mix fraction of vD across RC's.

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Analog IC Design

8.5. Startup: A. Continuous

Challenge: Latched positive-feedback cells are bi-stable: iOUT = 0 or iBIAS.
Fix: Ensure positive-feedback currents are not 0 iOUT can latch to iBIAS.
Continuous: Supply/pull ITRICKLE continuously from/to positive-feedback node.
ITRICKLE is independent of circuit's state.
ITRICKLE dissipates power and can produce error iST << iPTAT.
Use narrow- and long-channel JFETs or PFETs to generate ITRICKLE.

iC1 iC2 + iST Error

iC1 iC2 Low Error when iCB nears iC1.

Design Example
Objective: What PMOS widthlength dimensions for a diode-connected
PFET can generate 250 nA at room temperature when impressing
2.5 V across the device and |vTP| = 0.5 V, KP' = 25 A/V2,
LMIN = 0.5 m, and WMIN = 2 m?
Solution:
ITRICKLE is low Use minimum width W = WMIN = 2 m.
PMOS is in saturation
"W%
iSD 0.5$ ' K P' vSG v TP
#L&

" 0.5W %
L $$
'' K P' vSG v TP
# iSD &

) 0.5 2 ,

) = ++ (250n)) ..(25))*(2.5)(0.5),- = 400 m

2

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Analog IC Design

B. On Demand: i. Voltage Mode

On Demand: Supply/pull ITRICKLE only when iPTAT nears zero.
Must sense the state of the circuit.
Voltage Mode: Engage ITRICKLE when vBE or vGS drops.
Example:
Differential pair QS1QS2 senses
and compares vBEP1 with vBESR.
AS1 > AS2 QS1QS2 favors vBEP1.
QS2 is off when vBEP1 vBESR.
QS2 pulls iST when vBEP1 << vBESR.
In practice, iST is low, but not zero.

ii. Current Mode

On Demand
Current Mode: Engage ITRICKLE when iBIAS drops.
Example:
Mirror MM2MMB senses
and compares iPTAT with iLONG.
MS is off when iPTAT > iLONG.
MS pulls iST when iPTAT < iLONG.
CS keeps noise from triggering iST.
Design Notes:

iLONG << iPTAT across temperature and fabrication corners.

Connect CS to the positive supply vDD to
keep noise from affecting MS's vSG and iST.

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8.6.A. Frequency Compensation

Latching cells employ positive feedback to latch iO to iBIAS.
and negative feedback to diode-connect the mirroring transistor.
Design: ALG+ > ALG when circuit is off.
Use iST to raise ALG+.
ALG > ALG+ when circuit is on.
Attenuate ALG+ with a

Example

low-pass filter RFCF.

Use RP to degenerate ALG+

CC

RP
boosts
ALG.

stabilizes
ALG.

or boost ALG.
Stabilize ALG with CC's.

Notes: More feedback loops raises the number of stable states Difficult to start.
Startup is often cumbersome and empirical Involves some trial and error.

B. Supply-Noise Suppression
Modern ICs integrate sensor-interface circuits, power amplifiers (PA), receivers,
analog/digital (A/D) and digital/analog (D/A) converters, power supplies,
digital-signal processors (DSP), regulators, bias circuits, and more.
Switching power supplies produce supply noise.
Time-variant components pull power from the supply to produce supply
and ground noise.
Power-Supply Rejection (PSR): Ability to suppress noise.
Noise Rejectors:
Negative feedback opposes the effects of noise disturbances up to f0dB.
Differential pairs reject common-mode noise
in inputs because iO = (vP vN)GM.
Transistors reject common-mode noise in inputs because io = (vg/b vs/e)gm.
Common-mode capacitors couple source/emitter noise to/from
gate/base terminals for transistors to reject noise.

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C. Sample Implementation

RP boosts ALG.
*
$ 1 '$ 1 '
$ 1
'
A LG
,rB1 || roP1 + R P' || rsdM1 || &&
+ R P )) g mP1
))/ g mB1 &&
)) g mM2 &&
i i ,+
% g mB2 (
% g mP2
(
% sCC (/.
i p1

RFCF filters ALG+.

# 1 &,
# 1 &#
&
i m1 )
1
A LG+
+rB1 || roP1 + R P' || rsdM1 || %%
((. g mB1 %%
((%%
(( g mM1
i i +*
$ g mB2 '$ 1+ R FC Fs '
$ sCC '.-

How much circuit favors ALG over ALG+.

&
A LG g mM2 # 1

+ R P (( g mP1 1+ R FC Fs
%%
A LG+ g mM1 $ g mP2
'

! 1
$
= ##
+ R P && g mP1 1+ R FC Fs
" g mP2
%

CC couples emitter ground noise to QB1's base.

CF couples source supply noise to MM1's gate.
Negative feedback opposes the effects of noise.

8.7. Bandgap References: A. Current, i. BJT Implementation

Integrate baseemitter-derived CTAT currents into PTAT-current generators.
QP2QP1QB1MB2
diode-connects MM2, so
MM2MM1MB2MMO
mirrors currents and
sources both iPTAT and iCTAT.
RC1 and RC2 pull matched iCTAT's.
QP1QP2RP generates iPTAT.
QB1 and QP1QP2 pull
similar base currents.
RFCF filters the + feedback loop.

v
v
i REF = i CTAT + i PTAT = D + D
RC RP

CC stabilizes the feedback loop.

MLONG starts the circuit.

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ii. Diode Implementation

Integrate diode-derived CTAT currents into PTAT-current generators.
AG mixes fraction of MM1MM2's
drain voltages, so
RC1 and RC2 pull matched iCTAT's.
AG diode-connects MM2, so
MM2MM1MMBMMO
mirrors currents and
sources both iPTAT and iCTAT.
DP1DP2RP generates iPTAT.
RFCF filters the + feedback loop.
CC stabilizes the feedback loop.

v
v
i REF = i CTAT + i PTAT = D + D
RC RP

iii. Precision
i REF = i CTAT + i PTAT =

MMBMLONGMS starts the circuit.

v D v D VBG
+
=
R C R P R EQ

If RC and RP match, vCTAT and vPTAT shift proportionately

with RC and RP's 20% tolerance.
iREF's temperature drift is nearly independent of tolerance.
But since iREF 1/Resistance,
iREF drifts with RC and RP's temperature drift.
Choose low-drift resistors.
Absolute value of iREF shifts with RC and RP's 20% tolerance.
Bias current shifts 20% across fabrication corners.
If more precision is necessary,
adjust RC and RP after fabrication (i.e., trim).

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B. Voltage: i. CurrentVoltage Translation BJT Implementation

Establish vPTAT: Generate iPTAT and steer into a resistor RPTAT.
Establish vREF: Stack PTAT-generating diode on vPTAT.

Example

Compensated vD reduces to VBG 1.2 V.

QP1, QB1, and MB2 diode-connect MM2, so
MM1, MM2, and MB2 mirror iPTAT.
QP1, QP2, and RP generate iPTAT.
RP' matches vCEP1 and vCEP2.
CO shunts noise coupled and injected.
4iPTAT into RPTAT establishes vPTAT.
QP1 establishes vCTAT.
RF and CF filter ALG+.

v REF = 4i PTAT R PTAT + v BEP1

Note iST + iCB1 2iPTAT and mirror voltages and base currents match.
Reacting to noise in vREF alters iPTAT.

Diode Implementation
Diode-Derived Example

AG diode-connects MM2, so
MM1 and MM2 mirror iPTAT.
AG impresses vDP1 on RP and DP2, so
Mirror voltages match and
DP1, DP2, and RP generate iPTAT.
2iPTAT into RPTAT establishes vPTAT.
DP1 establishes vD.
AG shunt-samples vREF.
RFCF filters ALG+.
CO shunts noise coupled and injected.

v REF = 2i PTAT R PTAT + v DP1

Reacting to noise in vREF alters iPTAT.

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ii. Shunt Feedback

Noise Rejection: Shunt impedance at vREF suppresses coupled noise.
How: Modify diode-connecting loop to drive vREF with a source or an emitter.
AV impresses vRL2 on vRL1, so
RL1 and RL2 mirror iPTAT.
QP1, QP2, and RP generate iPTAT.
QP1 shunt-samples vREF.
2iPTAT into RPTAT establishes vPTAT.
QP1's vBEP1 establishes vD.
RP' matches vCEP1 and vCEP2.
AV sources base currents, so
no base-current error.

v REF = 2i PTAT R PTAT + v BEP1

CO shunts noise coupled and injected.

BJT Implementation
AV impresses vRL2 on vRL1, so
RL1 and RL2 mirror iPTAT.
QP1, QP2, and RP generate iPTAT.
QP1 shunt-samples vREF.
2iPTAT into RPTAT
establishes vPTAT.
QP1's vBEP1
establishes vD.
RF and CF filter ALG+.
RP' matches vCEP1 and vCEP2.

RBP1 matches RIF's vRIF.

AV sources base currents.

RP degenerates ALG+ and MD1,2 series-mixes vRL's.

RMFCMF and RIFCIF filter ALG+.

CO shunts noise coupled and injected.

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iii. Precision
First-order compensation cancels first-order T1 term only.
Higher-order terms in T ln T produces curvature in vREF.
vREF = vD + vPTAT VBG 1.2 V vD 0.60.7 V and vPTAT 0.50.6 V at TROOM.
Typical commercial range can be 0 to 85C, so TMID = 42.5C.
Extended commercial range can be 40 to 125C, so TMID = 42.5C.
When trimmed,
vREF at TMIN vREF at TMAX
dvREF/dT 0 near TMID
dvREF/dT > 0 near TROOM
" 1 %" v %
''$ REF '
Fractional Temperature Coefficient: TC $$
# v REF &# T &

Typical 3- TC is 20100 ppm/C 315 mV across 125C at 1.2 V.

Mismatch between non-degenerated transistors offset iREF.

Match

PTAT-generating pair DP1DP2, QP1QP2, or MP1MP2,

PTAT Resistors RP and RPTAT,
Mirroring Devices QM1QM2, MM1MM2 or RL1RL2, and
Non-degenerated transistors in diode-connecting loop.

The effect of mismatch between degenerated transistors is low in iREF.

Cascode transistors need not match as well.
Best-Matched Layout Cross-coupled, common centroid, same orientation,
compact, low spread, and
dummy devices.
Typical Layout Strategies
for the PTAT-generating pair:
A. 8 around 1 Compact.
B. 1 or 2 on either side of 1.

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Final Notes on Analog IC Design

Too many factors can spoil performance Risk only when necessary.
A bad layout or a poorly packaged die can spoil a good circuit.
Consider all vertical issues from devices to application.
Good designers balance optimism with pragmatism.
Challenge convention, but design for worst-case possibilities.
Specifications should guide architectural and parametric design choices.
The simplest circuit is usually the fastest and most reliable solution.
The simulator is good for tweaking and validating a design,
But not for conceptualizing circuits.
Simulate only when you believe you know what to expect.
Meaningful innovation is usually the result of
Insightful understanding of related technologies.

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The END

Thanks for your interest!

And best wishes.
[Link]
References: Rincn-Mora, Analog IC Design with Low-Dropout Regulators
Allen and Holberg, CMOS Analog Circuit Design

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