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Moore Sequence Detector Design

This document describes implementing a Moore type finite state machine for sequence detection in Verilog. It will detect the 10100101 sequence. The state diagram and Verilog code for the Moore FSM module and testbench are provided. In a Moore machine, the output is determined solely by the current state, whereas in a Mealy machine the output depends on both the current state and inputs. For sequence detection, Moore machines have an extra state where the output goes high to indicate detection of the target sequence.

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409 views9 pages

Moore Sequence Detector Design

This document describes implementing a Moore type finite state machine for sequence detection in Verilog. It will detect the 10100101 sequence. The state diagram and Verilog code for the Moore FSM module and testbench are provided. In a Moore machine, the output is determined solely by the current state, whereas in a Mealy machine the output depends on both the current state and inputs. For sequence detection, Moore machines have an extra state where the output goes high to indicate detection of the target sequence.

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Priya Apte
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We take content rights seriously. If you suspect this is your content, claim it here.
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EE5703 : VLSI DESIGN LAB

Sequence Detector(Moore type)

A sequence detector accepts as input a string of bits: either 0 or 1. Its output


goes to 1 when a target sequence has been detected. A finite state machine can
be divided into two types :Mealy and Moore . A Mealy machine is a finite-state
machine whose output values are determined both by its current state and the
current inputs. This is in contrast to a Moore machine, whose output values are
determined solely by its current state.
In this assignment we are implementing Moore type fsm with non overlapping
sequence detection .The sequence to be detected is 10100101.
State machine diagram is given below :
Verilog code :
module pattern_moore (clk, reset, in, out );

input clk, reset;


input in;
output out;
reg out;

parameter S0 = 0,
S1 = 1,
S2 = 2,
S3 = 3,
S4 = 4,
S5 = 5,
S6 = 6,
S7 = 7,
S8 = 8;

// Registers to hold current and next state


reg [3:0]cstate, nstate;

always @(posedge clk) begin


if (reset) begin
cstate <= S0;
end else begin
cstate <= nstate;
end
end

always @(cstate or in) begin


nstate = cstate;

case (cstate)
S0: begin
if (in == 'b1) begin
nstate = S1;
end
else begin
nstate = S0;
end
end
S1: begin
if (in == 'b0) begin
nstate = S2;
end
else begin
nstate = S0;
end
end
S2: begin
if (in == 'b1) begin
nstate = S3;
end
else begin
nstate = S0;
end
end
S3: begin
if (in == 'b0) begin
nstate = S4;
end
else begin
nstate = S1;
end
end
S4: begin
if (in == 'b0) begin
nstate = S5;
end
else begin
nstate = S3;
end
end
S5: begin
if (in == 'b1) begin
nstate = S6;
end
else begin
nstate = S0;
end
end
S6: begin
if (in == 'b0) begin
nstate = S7;
end

else begin
nstate = S1;
end
end
S7: begin
if (in == 'b1) begin
nstate = S8;
end
else begin
nstate = S0;
end
end
S8: begin
if (in == 'b1) begin
nstate = S1;
end
else begin
nstate = S0;
end
end
default: begin

nstate = S0;
end
endcase // case (cstate)
end // always @ (cstate or in)

always @ (cstate) begin

out = (cstate == S8);

end //
// always @ (cstate)
endmodule // fsm

Verilog code for testbench :


module pattern_moore_tb;
parameter NUMINPUTS = 100;

reg clk, reset, in;


wire out;
reg inputs[0:NUMINPUTS-1];
integer i;

// Instantiate module to be tested


pattern_moore dut(.clk(clk),
.reset(reset),
.in(in),
.out(out));

always #5 clk = ~clk;

initial begin
$readmemb("[Link]", inputs);
$monitor($time, "in = %b, out = %b", in, out);

clk = 0;
reset = 1;
#10 reset = 0;

// Simple way to wait until next clock edge:


@ (posedge clk);

for (i=0; i<NUMINPUTS; i=i+1) begin


in = inputs[i];
@ (posedge clk);
end
$finish;

end

endmodule // pattern_tb

Results :
Exercise : In the example sequence detector to detect 101 sequence it was Mealy
fsm. A Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. This is in contrast to
a Moore machine, whose output values are determined solely by its current state.
In Moore we have one extra state which has its output value set high to indicate
that he pattern is detected .

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