2011 International Conference on Recent Trends in Information Systems

Low Power Single Bitline 6T SRAM Cell

With High Read Stability

Budhaditya Majumdar Sumana Basu

PG Student, School of VLSI Technology PG Student, Dept. of Computer Sc. & Engg.
Bengal Engineering & Science University, Shibpur Jadavpur University
West Bengal, India Kolkata, West Bengal, India
[email protected] [email protected]

Abstract— This paper presents a novel CMOS 6-transistor performance, efficiency and reliability. Most of the embedded
SRAM cell for different purposes including low power embedded and portable devices use SRAM cells because of their ease of
SRAM applications and stand-alone SRAM applications. The use as well as low standby leakage.
data is retained by the cell with the help of leakage current and
positive feedback, and does not use any refresh cycle. The size of A six-transistor SRAM cell (6T SRAM cell) is
the new cell is comparable to the conventional six-transistor cell conventionally used as the memory cell. However, the 6T
of same technology and design rules. Also, the proposed cells uses SRAM cell produces a cell of larger size than that of a DRAM
a single bit-line for both read and write purposes. cell, resulting in a low memory density. Therefore,
conventional SRAM cells that use the 6T RAM cell have
The cell proposed in this paper consumes less dynamic power difficulty in meeting the growing demand of a larger memory
and has higher read stability than the standard one. In capacity in mobile applications.
conventional six-transistor (6T) SRAM cell, read stability is very
low due to the voltage division between the access and driver Also the conventional six transistor (6T) SRAM cell shows
transistors during read operation. In existing SRAM topologies poor stability at very small feature size with low power supply.
of 8T, 9T and higher transistor count, the read static noise During the read operation, the stability drastically decreases
margin (SNM) is increased but size of the cell and power due to the voltage division between the access and driver
consumption increases relatively. transistors.
In the proposed technique, the SRAM cell operates by charging / Considerable research work has been done over the past
discharging of a single bit-line (BL) during read and write several years to design a low power SRAM cell, which also
operation, resulting in reduction of dynamic power consumption resulted in a significant degradation in SRAM cell data
to only 40% to 60% (best case / worst case) of that of a stability. With each technology generation, the scaling of
conventional 6T SRAM cell. The power consumption is further CMOS devices results in random variations in the number of
decreased if the switching operational voltage of the bit-line lies dopant atoms in the channel region of the device. This causes
between 0.25VDD to 0.5VDD. All simulations are done using random variations in the device parameters like the threshold
0.18um Technology. voltage (Vt) and is usually known as random dopant
fluctuation (RDF) [1].
Keywords-single bit-line, low power, SRAM, 6T Cell, read stable
Since SRAM cells operate on delicately balanced
Transistors, and the conventional six transistor (6T) SRAM cell
I. INTRODUCTION shows poor stability during read operation, it is very important
Exponential increase in VLSI fabrication process has to consider these issues during new memory cell designs.
resulted in the increase of the densities of Integrated Circuits
by decreasing the device geometries. But devices with such Design proposed in various papers provides topologies for
high densities are susceptible to high power consumption and cells with higher read stability at the cost of increased area due
run time failures. Apart from such concerns, other factors such to higher transistor counts. Also isolated read bit-lines (separate
as a growing class of portable devices like PDA, cellular from the write bit lines) increase dynamic power consumption
phones, portable multimedia devices etc have given designers a and complexity while designing the overall memory unit.
motivation to look into low power design and today, not only
device geometries are a technology focus, but also reducing the II. BACKGROUND
existing topologies keeping the functionality intact is also a Rapid development of low power, low voltage SRAM cells
major area. has been experienced during recent years. This is due to an
Memories are an integral part of most of the digital devices increasing demand of embedded devices, notebooks, laptops,
and hence reducing power consumption of memories as well as hand held communication devices and IC memory cards. Due
area reduction is very important as of today to improve system to these concerns limiting power consumption is a must and

978-1-4577-0792-6/11/$26.00 ©2011 IEEE

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hence new techniques are being realized to improve energy requirements for reading and writing, a SRAM cell can also
efficiency at all levels of the design. In this paper an overall achieve that by modifying itself. A write operation to an
analysis has been carried-out for a novel SRAM cell with unselected column of a 6T standard SRAM cell can result in
respect to stability and switching power consumption. stability issues, when the word line is activated while both bit
lines are held high; a bias condition similar to a read operation.
Such problems resulted in design of different topologies of
SRAM cell to improve the data stability and leakage power
consumption [3].

III. PROPOSED 6T SRAM CELL

The proposed design has increased the read stability and
SNM, without affecting the Size or Power Consumption of a
Standard 6 Transistor SRAM cell.

A. Minimization of a 6T Srandard Cell

Figure 1. Traditional SRAM Cell with Dual Bit Line

In the traditional 6T-SRAM (Fig.1), the cells are expected

to be both read stable and also writable and such functionality
must be preserved for each cell under worst-case variation. At
the cell level, the static noise margin and write margin are both
maintained by the selection of calculated transistor strength
ratios, which in turn presents conflicting constraints on the cell
transistor strengths. For the cell stability during a read
operation, the storage inverters are usually made strong and the
pass-gates weak. Whereas the opposite is usually the case for
cell write ability which is a weak storage inverter and strong
pass-gates. Device variations common in nano-scale
fabrication can severely impact this delicate balance of
Figure 2. 6 Transistor Standard SRAM Cell
transistor strength ratios, which dramatically degrades stability
and write margins. These problems are further exacerbated by The schematic of Fig 2 once again shows the 6 Transistor
low voltage operations as threshold voltage variation consumes SRAM cell which uses two bit-lines and one word-lines (tied to
a larger fraction of these voltage margins. Variability can thus two access transistors).
limit the minimum operating voltage of SRAM [2].
Many design techniques circumventing variability
problems have been proposed to enable low-voltage operation
of 6T cells. One such method is the addition of a second higher
supply voltage dedicated to the SRAM array which is very
effective and ensures sufficient margins with scaling of the
logic supply voltage. The SRAM voltage does not scale with
technology in such cases and could even be increased as
variability intensifies. Instead of being tied to a fixed higher
supply, dynamically modulated supplies could also be used
with SRAM arrays that are pulsed to different levels when a
read or write event occurs. To an extent, this helps decoupling
read and write events from the standby condition such that the
optimum bias conditions can be used in each case. Such Figure 3. 5 Transistor (Single Ended) SRAM Cell
techniques may add complexity to the design, but can be used
to improve cell stability and write-ability or standby leakage. With the Transistor M6 being taken away a schematic like
These methods may reduce the trade-offs between cell Fig 3 is obtained, which still functions like the 6T SRAM but
optimization for read and write but cannot eliminate them as a the advantages of this design are reduction in cell area and
whole. power consumption. The cell area decreases by one transistor
and one bit line. The power consumption from charging the bit
Conflicting needs of cell read stability and write-ability line decreases by approximately a factor of 2 because only one
compromises the variability tolerance of a 6T standard cell. bit line is charged during a read operation instead of two, and
Balanced conditions are used for the same pass-gate devices the bit line is charged during a write operation about half of the
for reading and writing the cell, and it is inevitable that the two time (assume equal probability of writing 0 and 1) instead of
conditions cannot be simultaneously optimized. Similar to the every time when a write operation is required.
dynamically modulated power supplies which separate

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  Write: The word-line WL is charged to VDD as in 6T
Standard SRAM. Since NMOS is a stronger driver
than PMOS, no problem is incurred while writing a 0
into the cell. The absence of the pull down NMOS for
memory node Q allows writing a 1 into the cell easily.
Writing a 1 is done by pre-charging bit-line BL to
VDD. While writing 0, the bit-line BL is discharged
and then word-line WL is charged to VDD as in 6T
Standard SRAM.
 Read: Considering the case of reading Q=0; before
reading a value from the storage nodes, the bit line BL
is pre-charged to VDD. The read word line RL is then
asserted to VDD. The storage node Q' that stores a 1 is
Figure 4. 4 Transistor (Single Ended) SRAM Cell
statically connected to the gate of MRA (Read Access
Transistor) and will drain the charges on the bit line
With the Transistor M1 being taken away a schematic like through MRD to GND as the RL is 1, which means
Fig 4 if obtained, which has the functionality of a SRAM and that the bit line has just read a 0. On the contrary, when
the main advantage of this design is the further reduction Q=1, Q' will be 0 and MRA will be in cutoff and the
power consumption. Other advantages include significant bit line BL would not be able to discharge through
larger write margin and smaller delay for writing 1, and MRD to Gnd, and it would read a 1.
slightly smaller cell area.

B. The Proposed 6T New SRAM Cell

Figure 6. Schematic of Proposed 6T SRAM Cell in Multisim 11

IV. SIMULATION RESULTS

A. Dynamic Power Consumption

In an SRAM operation, power is consumed in two phases:
the setup phase and the operation phase.
Figure 5. 6 Transistor (Single Ended) SRAM Cell (Proposed) Energy consumed during the setup phase is dominated by
pre-charging/discharging various buses such as bit lines and
The proposed 6 Transistor new SRAM Cell is created by word lines. Using the formula Eline = 0.5 * Cline * Vline2, in which
adding two more transistors MRA (Read Access Transistor) Cline is the line capacitance and Vline is the change in line
and MRD (Read Driver Transistor) which shall work voltage, the energy drawn from the supply by the bus can be
independently during read operation and won’t affect the Cell calculated. From this information, the average power of an
SNM in any way. SRAM operation is obtained by dividing the clock period,
assuming that each SRAM cell can only perform one operation
C. Memory Cell Operations per clock period, and all word lines and bit lines are discharged
 Hold: If the cell content is a 1 (Q=VDD, Q’=0), both to 0 after performing each operation. Also the clock has 50%
memory nodes will lock each other at their respective duty cycle. In the simulation performed, a clock with 40ns
voltages. However, if the cell content is a 0 (Q=0, Q’= clock period is used (or equivalent to 25MHz clock frequency
VDD), Q is floating. Referring to Fig 5, the leakage and 1pF bit-line capacitance).
current through M5 must be greater than that of M2 to Therefore, consumed power Pline = Cline * Vline2 * F
ensure Q stays at 0. Fortunately, since NMOS (M5) is
a stronger current driver than PMOS (M2), this Dynamic power dissipation can be lowered by reducing the
condition is satisfied. switching activity and clock frequency but it affects the

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performance [9]. Reduction of supply voltage leads to same as switching the bit line. Note that for read operation,
degradation of the cell data stability. Hence dynamic power since the bit line is pre-charged to VDD, there is no significant
dissipation can be lowered by reducing bit-line capacitance of current flow and voltage changes across the access transistor if
the SRAM cell without degrading the performance. the cell contains a 1. Therefore, read 1 delay is not defined.
Power consumed during the operation phase is dominated The proposed 6T SRAM Cell has the smallest write 1
by active power and leakage power. Active power is the power delays because there is no pull-down NMOS that keeps the
consumed when both pull-up and pull-down networks are memory node from being pulled up to VDD. For the same
active, creating a direct current path from VDD to ground. reason, it also has the worst write 0 delays, because there is no
Leakage power is the power consumed when charges “leak” pull-down NMOS that helps to bring the memory node to 0.
through a transistor that is off.
TABLE II. DELAY ANALYSIS RESULTS
TABLE I. CALCULATED SWITCHING POWER Simulation Results from Multisim 11
Charging and Discharging of only Bit-Line considered
6T Standard SRAM Cell Proposed 6T SRAM Cell
6T Standard SRAM Cell Proposed 6T SRAM Cell WRITE 0 5.1 nS 6nS
WRITE 1 5.5 nS 0nS
WRITE 0 162uW 0uW
8.5nS @ 600nM
WRITE 1 162uW 81uW READ 0 7.5nS 6.5nS @ 800nM
{MRD/MRA}
READ 0 243uW 162uW C. Static Noise Margin
READ 1 243uW 81uW
SRAM cell design has to achieve high integration density
nowadays and it has led to a stringent constraint on the cell
area in modern embedded systems or memory modules.
Choosing minimal width-to-length ratios for the SRAM cell
For every write operation of a 6T Standard Cell, the transistors is the first step to achieve such a design. As
complementary data is placed on both the bit-lines and then the previously mentioned, variations in the threshold voltage Vth,
pre-charge circuit is activated. Only one of the bit-lines gets increase steadily due to random dopant density fluctuations in
charged depending on the data value. Once the write is channel, source and drain as the dimensions scale down to
completed, it is assumed that the capacitor is discharged. So nanometer regime [11]. Therefore, differences are common,
power dissipation happens twice during a write phase. During a between two closely placed transistors which were supposed to
read cycle, again both the bit-lines are charged and then one is be identical. The differences are mainly in their their electrical
discharged during reading a Zero, while the other is discharged parameters such as Vth and make the design of the SRAM less
after the operation is complete. predictable and controllable. Moreover, the stability of the
For the proposed 6T SRAM Cell, only a single bit-line is SRAM cell is seriously affected by the increase in variability
either charged if it is a 1 or does not get charged at all and by the decrease in supply voltage Vdd. Considerable
assuming that the data was already present before the pre- research in understanding and modeling the stability of the
charge circuit has been activated. After the write 1 operation, SRAM cell has been done in the past. Development of several
the bit-line is assumed to get discharged. During a read 0 cycle, analytical models of the static noise margin (SNM) have been
the bit-line capacitance is pre-charged and discharged through done in the past. Each of the work tried to optimize the design
the cell, where as in a read 1 cycle, the bit-line is pre-charged of the cell, to forecast the effect of parameter changes on the
and assumed to be discharged after the read process is over. SNM [12] and to estimate the impact of intrinsic parameter
variations on the cell stability [13]. Further, maximization of
B. Delay Calculation cell stability has been done in new SRAM cell circuit for future
technology nodes [14].
SRAM delays are usually defined as the time it takes to
read or write a value from an SRAM cell. When a node is The data retention of the Standard 6T SRAM cell in hold
switching, delay is measured as the time difference between state and the read state are important constraints in advanced
10% and 90% of the voltage swing. For example, if node A is technologies. The cell becomes less stable at low VDD, with
being changed over from 0V to 1.8V, then the delay is the time increase in leakage currents and increasing variability. “The
node A takes to go from 0.18V to 1.62V. stability is usually defined by the static noise margin as the
maximum value of the DC noise voltage that can be tolerated
In the simulation, it is assumed that the bit-line(s) have 1pF by the SRAM cell without altering the stored bits.” [15]
capacitance which is much higher a value than node
capacitance at VNode1. Therefore, it takes much less effort to In the standard 6T SRAM cell the read static-noise-margin
switch memory nodes than to switch bit line. This is why, in (SNM) is much affected with decrease in supply voltage
general, delays for write operation are smaller than that of read (VDD) and transistor mismatch [12], [16]. This mismatch
operation in SRAMs, because writing into a cell is the same as happens due to variations in physical quantities the devices
switching the memory node, and reading from a cell is the designed to be identical. Commonly known physical quantities

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are threshold voltages, body factor and current factor. Though 100mV of noise at Q’ when Q’ is at 1, can easily flip the state.
SNM decreases at low VDD the overall delay of the SRAM But it is very unlikely that a noise can flip Q’ from 0 to 1.
increases and also data destruction takes place with low VDD
read operation in SRAM cells [12]. But in the proposed SRAM D. Improving Noise Margin – Dual Vt
cell, reading from the cell has no effect on the static noise
The static noise margin at Hold State is very low as seen in
margin because the data retention and the data output blocks
Fig 7 and a slight disturbance of as less as 100mV at Q' can flip
are isolated.
the state of the Cell. To prevent this from happening, a higher
The main operations of the SRAM cell are the write, read Vt for M2 of Fig 5 can be implemented.
and hold. The static noise margin is certainly more important at
hold and read operations [6], specifically in read operation
when the wordline is 1 and the bitlines are precharged to 1. The
internal node of SRAM which stores 0 will be pulled up
through the access transistor across the access transistor and
the driver transistor. This increase in voltage severely degrades
the SNM during read operation.

Figure 8. The SNM Curve plotted for different VBS changing from 0.0V to
1.8V in steps of 300mV

It can be seen that the risk of Q’=1 being flipped with a

little noise reduces with increasing VBS for M2 of Fig 5.

V. CONCLUSION
Figure 7. Hold State SNM Curve for the proposed 6T Cell
Continuing technology scaling puts a limit on how much
During read/hold operation, the requirement is that the supply voltage can be scaled. Therefore, limiting the power
SRAM cell must be as robust as possible so that a sudden consumption with new architectures are the design
disturbance will not change the content in the memory nodes. requirements in recent integrated circuits. In the case of
For example, read noise margin of 200mV means that during SRAM, one seemingly counter intuitive approach is to utilize
read operation, if one of the memory nodes (Q or Q’) changes only a single bit-line without jeopardizing read stability, which
by less than 200mV, then we can be sure that after the read leads to the development of a Single Ended 6T SRAM. The
operation, the content of Q and Q’ will remain the same, and new SRAM operating scheme, gives a significant power
any disturbance to the voltage in the cell will be eliminated. reduction by reducing the amount of switching on bit lines.
Therefore, a larger read/hold noise margin is preferred. During Extending this operating scheme also allows us to propose a
write operation, the situation is reversed; the requirement is to single bit line design that achieves a relatively smaller area
switch the content of Q and Q’ easily. Therefore, the write while retaining all of the power saving advantages. For a small
noise margin (more commonly referred to as the “write penalty in delay, Single Ended 6T SRAMs are attractive
margin”) is defined as the range of voltage disturbances that alternatives as memory storage for applications that do not
will flip the content of the memory nodes. For example, if require high clock frequency. Although, higher operating
write margin is 500mV, then a range of at least 500mV frequency may be obtained by lowering the bit-line capacitance
disturbance in the memory nodes will cause their content to in the order of Femto Farads, instead of the 1pF, as assumed in
flip, thus achieving write operation. this paper.

It can be deduced from Fig 7 that Q’ is very zero stable

where as Q is pretty much 1 stable. And the risk is that a mere

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 REFERENCES
[16] Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro
[1] S. Borkar, T. Karnik, S. Narendra, J.T schanz, A. Keshavarzi, and V.de,
Nomura, Member, IEEE, Yoetsu Nakazawa, Toshio Ishii, and Hiroyuki
“Parameter Variations and Impact on Circuits & Microarchitecture,"
Kobatake, “A readstatic-noise-margin-free SRAM cell for low-VDD and
Proceedings of Design Automation Conerence., pp. 338-342, Jun.2003
high-speed applications,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2005,
pp. 478–479.
[2] Jawar Singh, DhirajK.Pradhan et al,” A single ended 6T SRAM cell
design for ultra low voltage applications”,IEICE Electronic
[17] Ultra-Low Voltage Nano-Scale Memories, Itoh, Kiyoo; Horiguchi,
Express,2008,pp-750-755
Masashi; Tanaka, Hitoshi (Eds.), Springer Publications

[3] Yen Chen,Gary Chen et al., “A 0.6V dual rail compiler SRAM design
[18] Digital Integrated Circuits A Design Perspective, Second Edition, Jan
on 45nm CMOS technology with Adaptive SRAM power for lower
M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Prentice-Hall /
Vdd_min VLSIs,Solid-State Circuits, IEEE Journal,vol. 44 ,April.2009,
Pearson Publications
Issue 4 , pp.1209-1214

[19] Shilpi Birla, Neeraj Kr. Shukla, Manisha Pattanaik, R.K.Singh, “Device
[4] Koichi Takeda et al, “A Read Static Noise Margin Free SRAM cell for
and Circuit Design Challenges for Low Leakage SRAM for Ultra Low
Low Vdd and High Speed Applications”,Solid-State Circuits, IEEE
Power Applications”, Canadian Journal on Electrical & Electronics
Journal vol. 41, Jan.2006, Issue 1 , pp.113-121
Engineering Vol. 1, No. 7, December 2010,

[5] Aly, R.E. Bayoumi, M.A., “Low-Power Cache Design Using 7T SRAM
[20] Shilpi Birla, Neeraj Kr.Shukla, Manisha Pattnaik, R.K.Singh
Cell” Circuits and Systems II: Express Briefs, IEEE Transactions, vol.
“ANALYSIS OF THE DATA STABILITY AND LEAKAGE POWER
54 April 2007, Issue: 4, pp. 318-322
IN THE VARIOUS SRAM CELLS TOPOLOGIES”, International
Journal of Engineering Science and Technology, Vol. 2(7), 2010, 2936-
[6] Benton H. Calhoun Anantha P. Chandrakasan “A 256-kb 65-nm Sub- 2944
threshold SRAM Design for Ultra-Low-Voltage Operation”,Solid-State
Circuits, IEEE Journal vol. 42, March 2007, Issue 3 , pp.680-688.
[21] Benton Highsmith Calhoun, Member, IEEE, and Anantha P.
Chandrakasan, Fellow, “A 256-kb 65-nm Sub-threshold SRAM Design
[7] Peter Geens, WimDehaene, “A dual port dual width 90nm SRAM with for Ultra-Low-Voltage Operation”, IEEE IEEE JOURNAL OF SOLID-
guaranteed data retention at minimal standby supply voltage”,34th STATE CIRCUITS, VOL. 42, NO. 3, MARCH 2007
European Solid-State Circuits Conference, 2008. ESSCIRC 2008.pp-
290-293.
[22] Prashant Upadhyay, Mr. Rajesh Mehra, Niveditta Thakur, “Low Power
Design of an SRAM Cell for Portable Devices”, Int’l Conf. on
[8] Farshad Moradi etal., “65nm Sub threshold 11 T SRAM for ultra low Computer & Communication Technology, ICCCT’10
voltage Application ,IEEE xplore,2008,pp-113-117
[23] Yen Hsiang Tseng, Yimeng Zhang , Leona Okamura and Tsutomu
[9] Dake Liu, and Christer Svenson, “Power Consumption Estimation in Yoshihara, Graduate School of Information, Production and Systems,
CMOS VLSI Chips," IEEE Journal of Solid State Circuits, vol. 29, No. Waseda University, Fukuoka, 808-0135, Japan, “A New 7-Transistor
6, pp. 663-670, June 1994 SRAM Cell Design with High Read Stability”, 2010 International
Conference on Electronic Devices, Systems and Applications
(ICEDSA2010)
[10] K. Itoh et. al., “Trends in Low-Power RAM Circuit Technologies”,
Proceedings of the IEEE, pp.524-543, April 1995
[24] Sandeep R, Narayan T Deshpande, A R Aswatha, “Design and Analysis
of a New Loadless 4T SRAM Cell in Deep Submicron CMOS
[11] B. Cheng et al., “The impact of random doping effects on CMOS SRAM Technologies”, Second International Conference on Emerging Trends in
cell,” in Proc. ESSCIRC, Sep. 2004, pp. 219–222 Engineering and Technology, ICETET-09

[12] E. Seevinck et al., “Static-noise margin analysis of MOS SRAM cells,” [25] Paridhi Athe, S. Dasgupta, “A Comparative Study of 6T, 8T and 9T
IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748–754, Oct. 1987 Decanano SRAM cell”, 2009 IEEE Symposium on Industrial
Electronics and Applications (ISIEA 2009), October 4-6, 2009, Kuala
[13] J. Bhavnagarwala et al., “The impact of intrinsic device fluctuations on Lumpur, Malaysia
CMOS SRAM cell stability,” IEEE J. Solid-State Circuits, vol. 36, no. 4,
pp. 658–665, Apr. 2001 [26] Abhijit Sil, Soumik Ghosh, Neeharika Gogineni, Magdy Bayoumi, “A
Novel High Write Speed, Low Power, Read-SNM-Free 6T SRAM
[14] L. Chang et al., “Stable SRAM cell design for the 32 nm node and Cell”, The Center for Advanced Computer Studies, University of
beyond,” in Symp. VLSI Technology Dig. Tech. Papers, Jun. 2005, pp. Louisiana at Lafayette, Lafayette, Louisiana 70504
128–129
[27] Ramy E. Aly and Magdy A. Bayoumi, Fellow, “Low-Power Cache
[15] Evelyn Grossar, Michele Stucchi, Karen Maex, Member, IEEE, and Design Using 7T SRAM Cell”, IEEE, IEEE TRANSACTIONS ON
Wim Dehaene, Senior Member, “Read stability and write-ability CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 4,
analysis of SRAM Cells for nanometer Technologies” IEEE Journal Of APRIL 2007
Solid-State Circuits, Vol. 41, No. 11, November 2006.

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