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Tic Tac Toe CAD Project Report

The CAD project report describes the design of a digital logic circuit to implement a Tic-Tac-Toe game. The circuit includes modules for position registers, a winner detector, an illegal move detector, and a finite state machine controller. The design was synthesized using a hardware description language and the resulting netlist was analyzed to generate area and power reports.

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Avinash Baldi

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0% found this document useful (1 vote)

204 views70 pages

Tic Tac Toe CAD Project Report

Uploaded by

Avinash Baldi

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as DOCX, PDF, TXT or read online on Scribd

CAD Project Report on TIC TAC

TOE Gaming Architecture

Submitted By:
Abhilash Rai 2018H1230242P
Piyush Ahuja 2018H1230248P

Submitted To:
Prof. Abhijit Asati

Electrical and Electronics Department, BITS Pilani (Pilani Campus)

1: Introduction

Tic tac toe is a very popular paper-and-pencil game in a 3x3

grid for two players. The player who makes the first three of
their marks in a diagonal, vertical, or horizontal row wins the
game.
The rules for the game at first. In this game, a player plays the
Tic Tac Toe game with a computer. When the player/ computer
plays the game, a 2-bit value is stored into one of the nine
positions in the 3x3 grid like Xs/ Os in the real paper-and-pencil
version.
2'b00 is stored into a position when neither the player nor
computer played in that position. Similarly, 2'b01 (X) is the
value to be stored when the player played in the position and
2'b10 (O) is the value to be saved when the computer played in
the position. The player/ computer plays the game by pressing
their corresponding button.
Red/ Green LED is lit in a position when the position is played
by the player/ computer respectively.
Consider the 3x3 grid table below as the order of the positions
being played:

1 2 3
4 5 6
7 8 9
The player/ computer wins the game when successfully placing
three similar (01-Xs) or (10-Os) values in the following row
pairs: (1,2,3); (4,5,6);(7,8,9); (1,4,7); (2,5,8); (3,6,9); (1,5,9);
(3,5,7).
The winner detecting circuit is designed to find the winner when
the above winning rule is matched. To detect an illegal move, a
comparator is needed to check if the current position was
already played by either the computer or player. Moreover, “No
space” detector is to check if all the positions are played and no
winner is found.

To control the Tic Tac Toe game, a FSM controller is designed

as follows.

1. IDLE(00): when waiting for the player/ computer to play or

when resetting the circuit, the FSM is at the IDLE state.
2. PLAYER(01): The player turns to play and “01” to be stored
into the decoded position.
3. COMPUTER(10):
The computer turns to play and “01” to be stored into the
decoded position.
4. Game_over(11): The game is finished when there is a winner
or no more space to play.
Inputs of the controller of the Tic Tac Toe game:
a. Reset :
Reset = 1: Reset the game when in the Game_Over state.
Reset = 0: The game begins.
b. Play:
Play = 1: When in the IDLE state, play = 1 is to switch the
controller to the PLAYER state and the player plays.
Play =0: Stay in the IDLE state.
c. PC
PC = 1: When in COMPUTER state, PC = 1 is to switch to the
IDLE state and the computer plays.
PC =0 : stay in COMPUTER state.
d. Illegal_move
Illegal_move = 0: When in PLAYER state, Illegal_move = 0 is to
switch to COMPUTER state and let computer plays when PC =
1.
Illegal_move = 1: Illegal moving from the player/ computer and
switch to the IDLE state.
e. No_space
No_space = 0: still have space to play, continue the game.
No_space = 1: no more space to play, game over, and need to
reset the game before playing again.
f. Win
Win = 0: Still waiting for the winner
Win = 1: There is a winner, finish the game, and need to reset
the game before playing again.

Blocks are:

1. No space detector
2. Fsm Controller
3. Two position decoders( one for player and one for
computer)
4. Illegal move detector
5. Positional registers unit
6. Winner detector

1: Simulation of the code

SYNTHESIS:

1. USING RC COMPILER
2. LAYOUT ( SOC ENCOUNTER)
3. AFTER ROUTING SCHEMATIC
4. REPORT SUMMARY
(i) Result 1
(ii) # ####################################################################
(iii)
(iv) # Created by Encounter(R) RTL Compiler v08.10-s116_1 on Thu Apr 11 [Link] IST
2019
(v)
(vi) # ####################################################################
(vii)
(viii) set sdc_version 1.7
(ix)
(x) set_units -capacitance 1000.0fF
(xi) set_units -time 1000.0ps
(xii)
(xiii) # Set the current design
(xiv) current_design tic_tac_toe_game
(xv)
(xvi) create_clock -name "clock" -add -period 3.5 -waveform {0.0 1.75} [get_ports clock]
(xvii) set_clock_gating_check -setup 0.0
(xviii) set_wire_load_mode "enclosed"
(xix) set_wire_load_selection_group "DEFAULT" -library "fsd0k_a_generic_core_1d0vtc"
(xx) set_dont_use [get_lib_cells fsd0k_a_generic_core_1d0vtc/CKLDRL]
(xxi) ## List of unsupported SDC commands ##
(xxii)

(iii) Area Report ( PRE ROUTE):

============================================================
Generated by: Encounter(R) RTL Compiler v08.10-s116_1
Generated on: Apr 11 2019 [Link] PM
Module: tic_tac_toe_game
Technology library: fsd0k_a_generic_core_1d0vtc 2007Q2v1.3
Operating conditions: _nominal_ (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================

Instance Cells Cell Area Net Area Wireload

--------------------------------------------------------------------
tic_tac_toe_game 211 1418 0 enG5K (S)
position_reg_unit 65 564 0 enG5K (S)
win_detect_unit 73 426 0 enG5K (S)
u8 8 45 0 enG5K (S)
u7 8 45 0 enG5K (S)
u6 8 45 0 enG5K (S)
u5 8 45 0 enG5K (S)
u4 8 45 0 enG5K (S)
u3 8 45 0 enG5K (S)
u2 8 45 0 enG5K (S)
u1 8 45 0 enG5K (S)
imd_unit 20 127 0 enG5K (S)
tic_tac_toe_controller 16 110 0 enG5K (S)
pd2 16 75 0 enG5K (S)
pd1 16 75 0 enG5K (S)
nsd_unit 5 41 0 enG5K (S)

(S) = wireload was automatically selected

(iii) Gate Report ( PRE ROUTE):

Gate Instances Area Library

----------------------------------------------------------------
AN2B1RLXLP 6 30.000 fsd0k_a_generic_core_1d0vtc
AN2RLX1 10 50.000 fsd0k_a_generic_core_1d0vtc
AN2RLXLP 16 80.000 fsd0k_a_generic_core_1d0vtc
AN3B2RLX1 8 56.000 fsd0k_a_generic_core_1d0vtc
AN3RLX1 1 7.000 fsd0k_a_generic_core_1d0vtc
AN4B1RLX1 2 16.000 fsd0k_a_generic_core_1d0vtc
AO12RLX1 10 70.000 fsd0k_a_generic_core_1d0vtc
AO22RLX1 1 9.000 fsd0k_a_generic_core_1d0vtc
AOI122RLX1 1 9.000 fsd0k_a_generic_core_1d0vtc
AOI122RLXLP 8 72.000 fsd0k_a_generic_core_1d0vtc
AOI12RLX1 1 6.000 fsd0k_a_generic_core_1d0vtc
AOI22RLX1 6 42.000 fsd0k_a_generic_core_1d0vtc
INVCKRLX1 1 3.000 fsd0k_a_generic_core_1d0vtc
INVRLX1 11 33.000 fsd0k_a_generic_core_1d0vtc
INVRLXLP 1 3.000 fsd0k_a_generic_core_1d0vtc
ND2RLX1 20 80.000 fsd0k_a_generic_core_1d0vtc
ND2RLXLP 10 40.000 fsd0k_a_generic_core_1d0vtc
ND3RLX1 1 6.000 fsd0k_a_generic_core_1d0vtc
ND3RLXLP 2 12.000 fsd0k_a_generic_core_1d0vtc
NR2RLX1 21 84.000 fsd0k_a_generic_core_1d0vtc
NR2RLXLP 8 32.000 fsd0k_a_generic_core_1d0vtc
NR3RLX1 1 6.000 fsd0k_a_generic_core_1d0vtc
OA222RLX1 1 12.000 fsd0k_a_generic_core_1d0vtc
OAI122RLX1 1 9.000 fsd0k_a_generic_core_1d0vtc
OAI22RLX1 21 147.000 fsd0k_a_generic_core_1d0vtc
OAI23RLX1 1 8.000 fsd0k_a_generic_core_1d0vtc
OR2B1RLXLP 4 20.000 fsd0k_a_generic_core_1d0vtc
OR2RLX1 8 40.000 fsd0k_a_generic_core_1d0vtc
OR3B2RLX1 2 14.000 fsd0k_a_generic_core_1d0vtc
OR4B1RLX1 1 8.000 fsd0k_a_generic_core_1d0vtc
OR4B1RLXLP 2 16.000 fsd0k_a_generic_core_1d0vtc
OR4B2RLX1 1 8.000 fsd0k_a_generic_core_1d0vtc
OR4RLX1 1 10.000 fsd0k_a_generic_core_1d0vtc
OR4RLXLP 2 20.000 fsd0k_a_generic_core_1d0vtc
QDFFRBRLX1 20 360.000 fsd0k_a_generic_core_1d0vtc
----------------------------------------------------------------
total 211 1418.000

Type Instances Area Area %

-------------------------------------
sequential 20 360.000 25.4
inverter 13 39.000 2.8
logic 178 1019.000 71.9
-------------------------------------
total 211 1418.000 100.0

(iii) Gate power Report ( PRE ROUTE):

Leakage Dynamic Total

Instance Cells Power(nW) Power(nW) Power(nW)
-------------------------------------------------------------
tic_tac_toe_game 211 3.924 69985.007 69988.931
position_reg_unit 65 1.754 48644.582 48646.336
win_detect_unit 73 1.065 2897.477 2898.542
u5 8 0.098 343.515 343.613
u6 8 0.098 479.797 479.895
u8 8 0.096 426.400 426.496
u7 8 0.095 271.690 271.785
u3 8 0.093 213.637 213.730
u2 8 0.091 357.859 357.950
u4 8 0.091 164.895 164.986
u1 8 0.089 181.926 182.015
imd_unit 20 0.419 1445.340 1445.759
tic_tac_toe_controller 16 0.322 7418.562 7418.883
pd2 16 0.147 543.062 543.209
pd1 16 0.144 670.651 670.795
nsd_unit 5 0.073 444.190 444.263
(iii) Netlist ( PRE ROUTE):

// Generated by Cadence Encounter(R) RTL Compiler v08.10-s116_1

module illegal_move_detector(pos1, pos2, pos3, pos4, pos5, pos6,

pos7,
pos8, pos9, PC_en, PL_en, illegal_move);
input [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
input [8:0] PC_en, PL_en;
output illegal_move;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire [8:0] PC_en, PL_en;
wire illegal_move;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
wire n_16, n_17, n_18;
OR4B2RLX1 g596(.I1 (n_17), .I2 (n_18), .B1 (n_9), .B2 (n_12), .O
(illegal_move));
ND3RLXLP g597(.I1 (n_16), .I2 (n_11), .I3 (n_8), .O (n_18));
ND3RLXLP g598(.I1 (n_15), .I2 (n_14), .I3 (n_13), .O (n_17));
AOI122RLX1 g599(.A1 (n_10), .B1 (n_2), .B2 (PC_en[4]), .C1 (n_0),
.C2
(PC_en[5]), .O (n_16));
AOI22RLX1 g600(.A1 (n_4), .A2 (PC_en[7]), .B1 (n_3), .B2
(PL_en[2]),
.O (n_15));
AOI22RLX1 g601(.A1 (n_1), .A2 (PL_en[1]), .B1 (n_6), .B2
(PC_en[8]),
.O (n_14));
AOI22RLX1 g602(.A1 (n_5), .A2 (PL_en[0]), .B1 (n_7), .B2
(PL_en[3]),
.O (n_13));
AOI22RLX1 g603(.A1 (n_5), .A2 (PC_en[0]), .B1 (n_6), .B2
(PL_en[8]),
.O (n_12));
AOI22RLX1 g604(.A1 (n_7), .A2 (PC_en[3]), .B1 (n_2), .B2
(PL_en[4]),
.O (n_11));
AO22RLX1 g605(.A1 (n_0), .A2 (PL_en[5]), .B1 (n_4), .B2
(PL_en[7]),
.O (n_10));
AOI22RLX1 g606(.A1 (n_1), .A2 (PC_en[1]), .B1 (n_3), .B2
(PC_en[2]),
.O (n_9));
OAI22RLX1 g607(.A1 (pos7[1]), .A2 (pos7[0]), .B1 (PC_en[6]), .B2
(PL_en[6]), .O (n_8));
OR2RLX1 g608(.I1 (pos4[1]), .I2 (pos4[0]), .O (n_7));
OR2RLX1 g609(.I1 (pos9[1]), .I2 (pos9[0]), .O (n_6));
OR2RLX1 g610(.I1 (pos1[1]), .I2 (pos1[0]), .O (n_5));
OR2RLX1 g611(.I1 (pos8[1]), .I2 (pos8[0]), .O (n_4));
OR2RLX1 g612(.I1 (pos3[1]), .I2 (pos3[0]), .O (n_3));
OR2RLX1 g613(.I1 (pos5[1]), .I2 (pos5[0]), .O (n_2));
OR2RLX1 g614(.I1 (pos2[1]), .I2 (pos2[0]), .O (n_1));
OR2RLX1 g615(.I1 (pos6[1]), .I2 (pos6[0]), .O (n_0));
endmodule

module nospace_detector(pos1, pos2, pos3, pos4, pos5, pos6, pos7,

pos8,
pos9, no_space);
input [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
output no_space;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire no_space;
wire n_0, n_1, n_2, n_3;
NR3RLX1 g205(.I1 (n_1), .I2 (n_0), .I3 (n_3), .O (no_space));
OAI122RLX1 g206(.A1 (n_2), .B1 (pos6[0]), .B2 (pos6[1]), .C1
(pos3[1]), .C2 (pos3[0]), .O (n_3));
OA222RLX1 g207(.A1 (pos7[1]), .A2 (pos7[0]), .B1 (pos2[0]), .B2
(pos2[1]), .C1 (pos1[1]), .C2 (pos1[0]), .O (n_2));
OAI22RLX1 g208(.A1 (pos5[1]), .A2 (pos5[0]), .B1 (pos4[0]), .B2
(pos4[1]), .O (n_1));
OAI22RLX1 g209(.A1 (pos8[1]), .A2 (pos8[0]), .B1 (pos9[0]), .B2
(pos9[1]), .O (n_0));
endmodule

module position_decoder(in, enable, out_en);

input [3:0] in;
input enable;
output [15:0] out_en;
wire [3:0] in;
wire enable;
wire [15:0] out_en;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6;
assign out_en[9] = 1'b0;
assign out_en[10] = 1'b0;
assign out_en[11] = 1'b0;
assign out_en[12] = 1'b0;
assign out_en[13] = 1'b0;
assign out_en[14] = 1'b0;
assign out_en[15] = 1'b0;
AN4B1RLX1 g313(.I1 (enable), .I2 (n_4), .I3 (in[3]), .B1 (in[0]),
.O
(out_en[8]));
NR2RLX1 g314(.I1 (n_0), .I2 (n_5), .O (out_en[7]));
NR2RLX1 g315(.I1 (n_1), .I2 (n_5), .O (out_en[5]));
NR2RLX1 g316(.I1 (n_1), .I2 (n_6), .O (out_en[4]));
NR2RLX1 g317(.I1 (n_2), .I2 (n_5), .O (out_en[3]));
NR2RLX1 g318(.I1 (n_2), .I2 (n_6), .O (out_en[2]));
NR2RLX1 g319(.I1 (n_0), .I2 (n_6), .O (out_en[6]));
AN2B1RLXLP g320(.I1 (n_4), .B1 (n_5), .O (out_en[1]));
AN2B1RLXLP g321(.I1 (n_4), .B1 (n_6), .O (out_en[0]));
ND2RLX1 g322(.I1 (enable), .I2 (n_3), .O (n_6));
OR3B2RLX1 g323(.I1 (in[3]), .B1 (enable), .B2 (in[0]), .O (n_5));
NR2RLX1 g324(.I1 (in[2]), .I2 (in[1]), .O (n_4));
NR2RLXLP g325(.I1 (in[0]), .I2 (in[3]), .O (n_3));
OR2B1RLXLP g326(.I1 (in[2]), .B1 (in[1]), .O (n_2));
OR2B1RLXLP g327(.I1 (in[1]), .B1 (in[2]), .O (n_1));
ND2RLXLP g328(.I1 (in[2]), .I2 (in[1]), .O (n_0));
endmodule

module position_decoder_169(in, enable, out_en);

module position_registers(clock, reset, illegal_move, PC_en, PL_en,

pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9);
input clock, reset, illegal_move;
input [8:0] PC_en, PL_en;
output [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire clock, reset, illegal_move;
wire [8:0] PC_en, PL_en;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
wire n_16, n_17, n_18, n_19, n_20, n_21, n_22, n_23;
wire n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31;
wire n_32, n_33, n_34, n_35, n_36, n_37, n_38, n_39;
wire n_40, n_41, n_42, n_43, n_44, n_45, n_46;
QDFFRBRLX1 \pos1_reg[1] (.RB (n_5), .CK (clock), .D (n_46), .Q
(pos1[1]));
QDFFRBRLX1 \pos3_reg[1] (.RB (n_5), .CK (clock), .D (n_45), .Q
(pos3[1]));
QDFFRBRLX1 \pos4_reg[1] (.RB (n_5), .CK (clock), .D (n_44), .Q
(pos4[1]));
QDFFRBRLX1 \pos5_reg[1] (.RB (n_5), .CK (clock), .D (n_43), .Q
(pos5[1]));
QDFFRBRLX1 \pos6_reg[1] (.RB (n_5), .CK (clock), .D (n_42), .Q
(pos6[1]));
QDFFRBRLX1 \pos2_reg[1] (.RB (n_5), .CK (clock), .D (n_39), .Q
(pos2[1]));
QDFFRBRLX1 \pos7_reg[1] (.RB (n_5), .CK (clock), .D (n_41), .Q
(pos7[1]));
QDFFRBRLX1 \pos8_reg[1] (.RB (n_5), .CK (clock), .D (n_40), .Q
(pos8[1]));
QDFFRBRLX1 \pos9_reg[1] (.RB (n_5), .CK (clock), .D (n_38), .Q
(pos9[1]));
QDFFRBRLX1 \pos3_reg[0] (.RB (n_5), .CK (clock), .D (n_34), .Q
(pos3[0]));
QDFFRBRLX1 \pos4_reg[0] (.RB (n_5), .CK (clock), .D (n_37), .Q
(pos4[0]));
QDFFRBRLX1 \pos5_reg[0] (.RB (n_5), .CK (clock), .D (n_36), .Q
(pos5[0]));
QDFFRBRLX1 \pos6_reg[0] (.RB (n_5), .CK (clock), .D (n_33), .Q
(pos6[0]));
QDFFRBRLX1 \pos2_reg[0] (.RB (n_5), .CK (clock), .D (n_30), .Q
(pos2[0]));
QDFFRBRLX1 \pos7_reg[0] (.RB (n_5), .CK (clock), .D (n_32), .Q
(pos7[0]));
QDFFRBRLX1 \pos8_reg[0] (.RB (n_5), .CK (clock), .D (n_31), .Q
(pos8[0]));
QDFFRBRLX1 \pos1_reg[0] (.RB (n_5), .CK (clock), .D (n_35), .Q
(pos1[0]));
QDFFRBRLX1 \pos9_reg[0] (.RB (n_5), .CK (clock), .D (n_29), .Q
(pos9[0]));
AO12RLX1 g1300(.A1 (n_21), .B1 (pos1[1]), .B2 (n_18), .O (n_46));
AO12RLX1 g1301(.A1 (n_24), .B1 (pos3[1]), .B2 (n_11), .O (n_45));
AO12RLX1 g1302(.A1 (n_26), .B1 (pos4[1]), .B2 (n_25), .O (n_44));
AO12RLX1 g1303(.A1 (n_23), .B1 (pos5[1]), .B2 (n_22), .O (n_43));
AO12RLX1 g1304(.A1 (n_20), .B1 (pos6[1]), .B2 (n_19), .O (n_42));
AO12RLX1 g1305(.A1 (n_17), .B1 (pos7[1]), .B2 (n_16), .O (n_41));
AO12RLX1 g1306(.A1 (n_13), .B1 (pos8[1]), .B2 (n_14), .O (n_40));
AO12RLX1 g1307(.A1 (n_15), .B1 (pos2[1]), .B2 (n_27), .O (n_39));
AO12RLX1 g1308(.A1 (n_12), .B1 (pos9[1]), .B2 (n_28), .O (n_38));
OAI22RLX1 g1309(.A1 (PC_en[3]), .A2 (n_25), .B1 (n_26), .B2 (n_8),
.O
(n_37));
OAI22RLX1 g1310(.A1 (PC_en[4]), .A2 (n_22), .B1 (n_9), .B2 (n_23),
.O
(n_36));
OAI22RLX1 g1311(.A1 (PC_en[0]), .A2 (n_18), .B1 (n_21), .B2 (n_2),
.O
(n_35));
OAI22RLX1 g1312(.A1 (PC_en[2]), .A2 (n_11), .B1 (n_24), .B2 (n_1),
.O
(n_34));
OAI22RLX1 g1313(.A1 (PC_en[5]), .A2 (n_19), .B1 (n_20), .B2 (n_4),
.O
(n_33));
OAI22RLX1 g1314(.A1 (PC_en[6]), .A2 (n_16), .B1 (n_17), .B2 (n_0),
.O
(n_32));
OAI22RLX1 g1315(.A1 (PC_en[7]), .A2 (n_14), .B1 (n_13), .B2 (n_7),
.O
(n_31));
OAI22RLX1 g1316(.A1 (PC_en[1]), .A2 (n_27), .B1 (n_15), .B2 (n_6),
.O
(n_30));
OAI22RLX1 g1317(.A1 (PC_en[8]), .A2 (n_28), .B1 (n_12), .B2 (n_3),
.O
(n_29));
ND2RLX1 g1318(.I1 (n_10), .I2 (PL_en[8]), .O (n_28));
ND2RLX1 g1319(.I1 (n_10), .I2 (PL_en[1]), .O (n_27));
AN2RLX1 g1320(.I1 (n_10), .I2 (PC_en[3]), .O (n_26));
ND2RLX1 g1321(.I1 (n_10), .I2 (PL_en[3]), .O (n_25));
AN2RLX1 g1322(.I1 (n_10), .I2 (PC_en[2]), .O (n_24));
AN2RLX1 g1323(.I1 (n_10), .I2 (PC_en[4]), .O (n_23));
ND2RLX1 g1324(.I1 (n_10), .I2 (PL_en[4]), .O (n_22));
AN2RLX1 g1325(.I1 (n_10), .I2 (PC_en[0]), .O (n_21));
AN2RLX1 g1326(.I1 (n_10), .I2 (PC_en[5]), .O (n_20));
ND2RLX1 g1327(.I1 (n_10), .I2 (PL_en[5]), .O (n_19));
ND2RLX1 g1328(.I1 (n_10), .I2 (PL_en[0]), .O (n_18));
AN2RLX1 g1329(.I1 (n_10), .I2 (PC_en[6]), .O (n_17));
ND2RLX1 g1330(.I1 (n_10), .I2 (PL_en[6]), .O (n_16));
AN2RLX1 g1331(.I1 (n_10), .I2 (PC_en[1]), .O (n_15));
ND2RLX1 g1332(.I1 (n_10), .I2 (PL_en[7]), .O (n_14));
AN2RLX1 g1333(.I1 (n_10), .I2 (PC_en[7]), .O (n_13));
AN2RLX1 g1334(.I1 (n_10), .I2 (PC_en[8]), .O (n_12));
ND2RLX1 g1335(.I1 (n_10), .I2 (PL_en[2]), .O (n_11));
INVRLX1 g1336(.I (illegal_move), .O (n_10));
INVRLX1 g1337(.I (pos5[0]), .O (n_9));
INVRLX1 g1338(.I (pos4[0]), .O (n_8));
INVRLX1 g1339(.I (pos8[0]), .O (n_7));
INVRLX1 g1340(.I (pos2[0]), .O (n_6));
INVCKRLX1 g1341(.I (reset), .O (n_5));
INVRLX1 g1342(.I (pos6[0]), .O (n_4));
INVRLX1 g1343(.I (pos9[0]), .O (n_3));
INVRLX1 g1344(.I (pos1[0]), .O (n_2));
INVRLX1 g1345(.I (pos3[0]), .O (n_1));
INVRLX1 g1346(.I (pos7[0]), .O (n_0));
endmodule

module fsm_controller(clock, reset, play, pc, illegal_move,

no_space,
win, computer_play, player_play);
input clock, reset, play, pc, illegal_move, no_space, win;
output computer_play, player_play;
wire clock, reset, play, pc, illegal_move, no_space, win;
wire computer_play, player_play;
wire \current_state[0] , \current_state[1] , n_0, n_3, n_4, n_5,
n_6,
n_7;
wire n_8, n_11, n_12, n_19, n_23, n_24;
AN3RLX1 g250(.I1 (n_19), .I2 (\current_state[1] ), .I3 (pc), .O
(computer_play));
NR2RLX1 g251(.I1 (\current_state[1] ), .I2 (n_19), .O
(player_play));
INVRLX1 g252(.I (\current_state[0] ), .O (n_19));
QDFFRBRLX1 \current_state_reg[1] (.RB (n_0), .CK (clock), .D
(n_12),
.Q (\current_state[1] ));
OAI22RLX1 g457(.A1 (n_7), .A2 (n_23), .B1 (n_24), .B2 (n_19), .O
(n_12));
QDFFRBRLX1 \current_state_reg[0] (.RB (n_0), .CK (clock), .D
(n_11),
.Q (\current_state[0] ));
OAI23RLX1 g459(.A1 (n_5), .A2 (n_3), .B1 (n_6), .B2 (n_4), .B3
(reset), .O (n_11));
AN2B1RLXLP g462(.I1 (n_6), .B1 (illegal_move), .O (n_8));
AN2RLX1 g463(.I1 (n_3), .I2 (pc), .O (n_7));
AO12RLX1 g464(.A1 (player_play), .B1 (\current_state[1] ), .B2
(n_19), .O (n_6));
ND3RLX1 g465(.I1 (\current_state[1] ), .I2 (n_19), .I3 (pc), .O
(n_5));
AN2B1RLXLP g466(.I1 (n_19), .B1 (play), .O (n_4));
NR2RLX1 g467(.I1 (no_space), .I2 (win), .O (n_3));
INVRLXLP g470(.I (reset), .O (n_0));
ND2RLX1 g2(.I1 (n_6), .I2 (n_19), .O (n_23));
AOI12RLX1 g472(.A1 (n_8), .B1 (\current_state[1] ), .B2 (n_0), .O
(n_24));
endmodule

module winner_detect_3(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4;
AN2RLXLP g144(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g145(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
AOI122RLXLP g146(.A1 (n_4), .B1 (n_1), .B2 (pos0[0]), .C1 (n_2),
.C2
(pos0[1]), .O (winner));
OAI22RLX1 g147(.A1 (pos0[0]), .A2 (n_3), .B1 (n_0), .B2 (pos0[1]),
.O
(n_4));
AN3B2RLX1 g148(.I1 (pos1[1]), .B1 (pos2[0]), .B2 (pos1[0]), .O
(n_3));
ND2RLXLP g149(.I1 (pos2[1]), .I2 (pos1[1]), .O (n_2));
ND2RLX1 g150(.I1 (pos2[0]), .I2 (pos1[0]), .O (n_1));
NR2RLXLP g151(.I1 (pos2[1]), .I2 (pos1[1]), .O (n_0));
endmodule

module winner_detect_3_101(pos0, pos1, pos2, winner, who);

module winner_detect_3_106(pos0, pos1, pos2, winner, who);

module winner_detect_3_111(pos0, pos1, pos2, winner, who);

module winner_detect_3_116(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4;
AN2RLXLP g144(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g145(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
AOI122RLXLP g146(.A1 (n_4), .B1 (n_1), .B2 (pos0[0]), .C1 (n_2),
.C2
(pos0[1]), .O (winner));
OAI22RLX1 g147(.A1 (pos0[0]), .A2 (n_3), .B1 (n_0), .B2 (pos0[1]),
.O
(n_4));
AN3B2RLX1 g148(.I1 (pos1[1]), .B1 (pos1[0]), .B2 (pos2[0]), .O
(n_3));
ND2RLXLP g149(.I1 (pos1[1]), .I2 (pos2[1]), .O (n_2));
ND2RLX1 g150(.I1 (pos1[0]), .I2 (pos2[0]), .O (n_1));
NR2RLX1 g151(.I1 (pos2[1]), .I2 (pos1[1]), .O (n_0));
endmodule

module winner_detect_3_121(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4;
AN2RLXLP g144(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g145(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
AOI122RLXLP g146(.A1 (n_4), .B1 (n_1), .B2 (pos0[0]), .C1 (n_2),
.C2
(pos0[1]), .O (winner));
OAI22RLX1 g147(.A1 (pos0[0]), .A2 (n_3), .B1 (n_0), .B2 (pos0[1]),
.O
(n_4));
AN3B2RLX1 g148(.I1 (pos1[1]), .B1 (pos1[0]), .B2 (pos2[0]), .O
(n_3));
ND2RLXLP g149(.I1 (pos1[1]), .I2 (pos2[1]), .O (n_2));
ND2RLX1 g150(.I1 (pos1[0]), .I2 (pos2[0]), .O (n_1));
NR2RLX1 g151(.I1 (pos2[1]), .I2 (pos1[1]), .O (n_0));
endmodule

module winner_detect_3_126(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4;
AN2RLXLP g144(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g145(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
AOI122RLXLP g146(.A1 (n_4), .B1 (n_1), .B2 (pos0[0]), .C1 (n_2),
.C2
(pos0[1]), .O (winner));
OAI22RLX1 g147(.A1 (pos0[0]), .A2 (n_3), .B1 (n_0), .B2 (pos0[1]),
.O
(n_4));
AN3B2RLX1 g148(.I1 (pos1[1]), .B1 (pos1[0]), .B2 (pos2[0]), .O
(n_3));
ND2RLXLP g149(.I1 (pos1[1]), .I2 (pos2[1]), .O (n_2));
ND2RLX1 g150(.I1 (pos1[0]), .I2 (pos2[0]), .O (n_1));
NR2RLX1 g151(.I1 (pos2[1]), .I2 (pos1[1]), .O (n_0));
endmodule

module winner_detect_3_131(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4;
AN2RLXLP g144(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g145(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
AOI122RLXLP g146(.A1 (n_4), .B1 (n_1), .B2 (pos0[0]), .C1 (n_2),
.C2
(pos0[1]), .O (winner));
OAI22RLX1 g147(.A1 (pos0[0]), .A2 (n_3), .B1 (n_0), .B2 (pos0[1]),
.O
(n_4));
AN3B2RLX1 g148(.I1 (pos1[1]), .B1 (pos1[0]), .B2 (pos2[0]), .O
(n_3));
ND2RLXLP g149(.I1 (pos1[1]), .I2 (pos2[1]), .O (n_2));
ND2RLX1 g150(.I1 (pos1[0]), .I2 (pos2[0]), .O (n_1));
NR2RLX1 g151(.I1 (pos2[1]), .I2 (pos1[1]), .O (n_0));
endmodule

module winner_detector(pos1, pos2, pos3, pos4, pos5, pos6, pos7,

pos8,
pos9, winner, who);
input [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
output winner;
output [1:0] who;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4, n_5, \who1[0] , \who1[1] ;
wire \who2[0] , \who2[1] , \who3[0] , \who3[1] , \who4[0] ,
\who4[1]
, \who5[0] , \who5[1] ;
wire \who6[0] , \who6[1] , \who7[0] , \who7[1] , \who8[0] ,
\who8[1]
, win1, win2;
wire win3, win4, win5, win6, win7, win8;
winner_detect_3 u1(pos1, pos2, pos3, win1, {\who1[1] , \who1[0]
});
winner_detect_3_101 u2(pos4, pos5, pos6, win2, {\who2[1] ,
\who2[0]
});
winner_detect_3_106 u3(pos7, pos8, pos9, win3, {\who3[1] ,
\who3[0]
});
winner_detect_3_111 u4(pos1, pos4, pos7, win4, {\who4[1] ,
\who4[0]
});
winner_detect_3_116 u5(pos2, pos5, pos8, win5, {\who5[1] ,
\who5[0]
});
winner_detect_3_121 u6(pos3, pos6, pos9, win6, {\who6[1] ,
\who6[0]
});
winner_detect_3_126 u7(pos1, pos5, pos9, win7, {\who7[1] ,
\who7[0]
});
winner_detect_3_131 u8(pos3, pos5, pos6, win8, {\who8[1] ,
\who8[0]
});
OR4B1RLX1 g76(.I1 (win3), .I2 (n_5), .I3 (win4), .B1 (n_4), .O
(winner));
OR4RLX1 g77(.I1 (win5), .I2 (win8), .I3 (win7), .I4 (win6), .O
(n_5));
NR2RLX1 g78(.I1 (win1), .I2 (win2), .O (n_4));
OR4B1RLXLP g82(.I1 (\who3[1] ), .I2 (n_3), .I3 (\who4[1] ), .B1
(n_2), .O (who[1]));
OR4RLXLP g83(.I1 (\who7[1] ), .I2 (\who5[1] ), .I3 (\who8[1] ),
.I4
(\who6[1] ), .O (n_3));
NR2RLXLP g84(.I1 (\who1[1] ), .I2 (\who2[1] ), .O (n_2));
OR4B1RLXLP g85(.I1 (\who3[0] ), .I2 (n_1), .I3 (\who4[0] ), .B1
(n_0), .O (who[0]));
OR4RLXLP g86(.I1 (\who7[0] ), .I2 (\who5[0] ), .I3 (\who8[0] ),
.I4
(\who6[0] ), .O (n_1));
NR2RLXLP g87(.I1 (\who1[0] ), .I2 (\who2[0] ), .O (n_0));
endmodule

module tic_tac_toe_game(clock, reset, play, pc, computer_position,

player_position, pos1, pos2, pos3, pos4, pos5, pos6, pos7,
pos8,
pos9, who);
input clock, reset, play, pc;
input [3:0] computer_position, player_position;
output [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9,
who;
wire clock, reset, play, pc;
wire [3:0] computer_position, player_position;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9,
who;
wire \PC_en[0] , \PC_en[1] , \PC_en[2] , \PC_en[3] , \PC_en[4] ,
\PC_en[5] , \PC_en[6] , \PC_en[7] ;
wire \PC_en[8] , \PL_en[0] , \PL_en[1] , \PL_en[2] , \PL_en[3] ,
\PL_en[4] , \PL_en[5] , \PL_en[6] ;
wire \PL_en[7] , \PL_en[8] , UNCONNECTED, UNCONNECTED0,
UNCONNECTED1,
UNCONNECTED2, UNCONNECTED3, UNCONNECTED4;
wire UNCONNECTED5, UNCONNECTED6, UNCONNECTED7, UNCONNECTED8,
UNCONNECTED9, UNCONNECTED10, UNCONNECTED11, UNCONNECTED12;
wire computer_play, illegal_move, no_space, player_play, win;
illegal_move_detector imd_unit(pos1, pos2, pos3, pos4, pos5, pos6,
pos7, pos8, pos9, {\PC_en[8] , \PC_en[7] , \PC_en[6] ,
\PC_en[5]
, \PC_en[4] , \PC_en[3] , \PC_en[2] , \PC_en[1] , \PC_en[0]
},
{\PL_en[8] , \PL_en[7] , \PL_en[6] , \PL_en[5] , \PL_en[4] ,
\PL_en[3] , \PL_en[2] , \PL_en[1] , \PL_en[0] },
illegal_move);
nospace_detector nsd_unit(pos1, pos2, pos3, pos4, pos5, pos6,
pos7,
pos8, pos9, no_space);
position_decoder pd1(computer_position, computer_play,
{UNCONNECTED,
UNCONNECTED0, UNCONNECTED1, UNCONNECTED2, UNCONNECTED3,
UNCONNECTED4, UNCONNECTED5, \PC_en[8] , \PC_en[7] , \PC_en[6]
,
\PC_en[5] , \PC_en[4] , \PC_en[3] , \PC_en[2] , \PC_en[1] ,
\PC_en[0] });
position_decoder_169 pd2(player_position, player_play,
{UNCONNECTED6,
UNCONNECTED7, UNCONNECTED8, UNCONNECTED9, UNCONNECTED10,
UNCONNECTED11, UNCONNECTED12, \PL_en[8] , \PL_en[7] ,
\PL_en[6]
, \PL_en[5] , \PL_en[4] , \PL_en[3] , \PL_en[2] , \PL_en[1] ,
\PL_en[0] });
position_registers position_reg_unit(clock, reset, illegal_move,
{\PC_en[8] , \PC_en[7] , \PC_en[6] , \PC_en[5] , \PC_en[4] ,
\PC_en[3] , \PC_en[2] , \PC_en[1] , \PC_en[0] }, {\PL_en[8] ,
\PL_en[7] , \PL_en[6] , \PL_en[5] , \PL_en[4] , \PL_en[3] ,
\PL_en[2] , \PL_en[1] , \PL_en[0] }, pos1, pos2, pos3, pos4,
pos5, pos6, pos7, pos8, pos9);
fsm_controller tic_tac_toe_controller(clock, reset, play, pc,
illegal_move, no_space, win, computer_play, player_play);
winner_detector win_detect_unit(pos1, pos2, pos3, pos4, pos5,
pos6,
pos7, pos8, pos9, win, who);
endmodule

(iii) Slack ( PRE ROUTE):

path 1:

Pin Type Fanout Load Slew Delay

Arrival
(fF) (ps) (ps)
(ps)
--------------------------------------------------------------------
-----
(clock clock) launch
0 R
tic_tac_toe_controller
current_state_reg[0]/CK 0
0 R
current_state_reg[0]/Q QDFFRBRLX1 1 3.1 29 +311
311 F
g252/I +0
311
g252/O INVRLX1 7 24.5 152 +196
507 R
g251/I2 +0
507
g251/O NR2RLX1 4 13.5 66 +163
671 F
tic_tac_toe_controller/player_play
pd2/enable
g323/B1 +0
671
g323/O OR3B2RLX1 4 13.7 106 +175
846 R
g315/I2 +0
846
g315/O NR2RLX1 2 6.4 40 +105
950 F
pd2/out_en[5]
imd_unit/PL_en[5]
g605/A2 +0
950
g605/O AO22RLX1 1 2.8 31 +265
1215 F
g599/A1 +0
1215
g599/O AOI122RLX1 1 2.7 127 +189
1404 R
g597/I1 +0
1404
g597/O ND3RLXLP 1 3.0 59 +134
1537 F
g596/I2 +0
1537
g596/O OR4B2RLX1 2 6.0 70 +232
1769 F
imd_unit/illegal_move
position_reg_unit/illegal_move
g1336/I +0
1769
g1336/O INVRLX1 18 64.4 383 +482
2251 R
g1318/I1 +0
2251
g1318/O ND2RLX1 2 5.9 103 +232
2483 F
g1308/B2 +0
2483
g1308/O AO12RLX1 1 2.2 29 +249
2732 F
pos9_reg[1]/D QDFFRBRLX1 +0
2732
pos9_reg[1]/CK setup 0 +233
2965 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
(clock clock) capture
3500 R
--------------------------------------------------------------------
-----
Timing slack : 535ps
Start-point : tic_tac_toe_controller/current_state_reg[0]/CK
End-point : position_reg_unit/pos9_reg[1]/D

path 2:

Pin Type Fanout Load Slew Delay

Arrival
(fF) (ps) (ps)
(ps)
--------------------------------------------------------------------
-----
(clock clock) launch
0 R
tic_tac_toe_controller
current_state_reg[0]/CK 0
0 R
current_state_reg[0]/Q QDFFRBRLX1 1 3.1 29 +311
311 F
g252/I +0
311
g252/O INVRLX1 7 24.5 152 +196
507 R
g251/I2 +0
507
g251/O NR2RLX1 4 13.5 66 +163
671 F
tic_tac_toe_controller/player_play
pd2/enable
g323/B1 +0
671
g323/O OR3B2RLX1 4 13.7 106 +175
846 R
g315/I2 +0
846
g315/O NR2RLX1 2 6.4 40 +105
950 F
pd2/out_en[5]
imd_unit/PL_en[5]
g605/A2 +0
950
g605/O AO22RLX1 1 2.8 31 +265
1215 F
g599/A1 +0
1215
g599/O AOI122RLX1 1 2.7 127 +189
1404 R
g597/I1 +0
1404
g597/O ND3RLXLP 1 3.0 59 +134
1537 F
g596/I2 +0
1537
g596/O OR4B2RLX1 2 6.0 70 +232
1769 F
imd_unit/illegal_move
position_reg_unit/illegal_move
g1336/I +0
1769
g1336/O INVRLX1 18 64.4 383 +482
2251 R
g1332/I1 +0
2251
g1332/O ND2RLX1 2 5.9 103 +232
2483 F
g1306/B2 +0
2483
g1306/O AO12RLX1 1 2.2 29 +249
2732 F
pos8_reg[1]/D QDFFRBRLX1 +0
2732
pos8_reg[1]/CK setup 0 +233
2965 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
(clock clock) capture
3500 R
--------------------------------------------------------------------
-----
Timing slack : 535ps
Start-point : tic_tac_toe_controller/current_state_reg[0]/CK
End-point : position_reg_unit/pos8_reg[1]/D

path 3:
Pin Type Fanout Load Slew Delay
Arrival
(fF) (ps) (ps)
(ps)
--------------------------------------------------------------------
-----
(clock clock) launch
0 R
tic_tac_toe_controller
current_state_reg[0]/CK 0
0 R
current_state_reg[0]/Q QDFFRBRLX1 1 3.1 29 +311
311 F
g252/I +0
311
g252/O INVRLX1 7 24.5 152 +196
507 R
g251/I2 +0
507
g251/O NR2RLX1 4 13.5 66 +163
671 F
tic_tac_toe_controller/player_play
pd2/enable
g323/B1 +0
671
g323/O OR3B2RLX1 4 13.7 106 +175
846 R
g315/I2 +0
846
g315/O NR2RLX1 2 6.4 40 +105
950 F
pd2/out_en[5]
imd_unit/PL_en[5]
g605/A2 +0
950
g605/O AO22RLX1 1 2.8 31 +265
1215 F
g599/A1 +0
1215
g599/O AOI122RLX1 1 2.7 127 +189
1404 R
g597/I1 +0
1404
g597/O ND3RLXLP 1 3.0 59 +134
1537 F
g596/I2 +0
1537
g596/O OR4B2RLX1 2 6.0 70 +232
1769 F
imd_unit/illegal_move
position_reg_unit/illegal_move
g1336/I +0
1769
g1336/O INVRLX1 18 64.4 383 +482
2251 R
g1330/I1 +0
2251
g1330/O ND2RLX1 2 5.9 103 +232
2483 F
g1305/B2 +0
2483
g1305/O AO12RLX1 1 2.2 29 +249
2732 F
pos7_reg[1]/D QDFFRBRLX1 +0
2732
pos7_reg[1]/CK setup 0 +233
2965 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
(clock clock) capture
3500 R
--------------------------------------------------------------------
-----
Timing slack : 535ps
Start-point : tic_tac_toe_controller/current_state_reg[0]/CK
End-point : position_reg_unit/pos7_reg[1]/D

path 4:

Pin Type Fanout Load Slew Delay

Arrival
(fF) (ps) (ps)
(ps)
--------------------------------------------------------------------
-----
(clock clock) launch
0 R
tic_tac_toe_controller
current_state_reg[0]/CK 0
0 R
current_state_reg[0]/Q QDFFRBRLX1 1 3.1 29 +311
311 F
g252/I +0
311
g252/O INVRLX1 7 24.5 152 +196
507 R
g251/I2 +0
507
g251/O NR2RLX1 4 13.5 66 +163
671 F
tic_tac_toe_controller/player_play
pd2/enable
g323/B1 +0
671
g323/O OR3B2RLX1 4 13.7 106 +175
846 R
g315/I2 +0
846
g315/O NR2RLX1 2 6.4 40 +105
950 F
pd2/out_en[5]
imd_unit/PL_en[5]
g605/A2 +0
950
g605/O AO22RLX1 1 2.8 31 +265
1215 F
g599/A1 +0
1215
g599/O AOI122RLX1 1 2.7 127 +189
1404 R
g597/I1 +0
1404
g597/O ND3RLXLP 1 3.0 59 +134
1537 F
g596/I2 +0
1537
g596/O OR4B2RLX1 2 6.0 70 +232
1769 F
imd_unit/illegal_move
position_reg_unit/illegal_move
g1336/I +0
1769
g1336/O INVRLX1 18 64.4 383 +482
2251 R
g1319/I1 +0
2251
g1319/O ND2RLX1 2 5.9 103 +232
2483 F
g1307/B2 +0
2483
g1307/O AO12RLX1 1 2.2 29 +249
2732 F
pos2_reg[1]/D QDFFRBRLX1 +0
2732
pos2_reg[1]/CK setup 0 +233
2965 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
(clock clock) capture
3500 R
--------------------------------------------------------------------
-----
Timing slack : 535ps
Start-point : tic_tac_toe_controller/current_state_reg[0]/CK
End-point : position_reg_unit/pos2_reg[1]/D

(iii) DRC
============================================================
Generated by: Encounter(R) RTL Compiler v08.10-s116_1
Generated on: Apr 11 2019 [Link] PM
Module: tic_tac_toe_game
Technology library: fsd0k_a_generic_core_1d0vtc 2007Q2v1.3
Operating conditions: _nominal_ (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================

Timing
------
Tracing clock networks.
Levelizing the circuit.
Computing delays.
Computing arrivals and requireds.
Warning : Possible timing problems have been detected in this
design. [TIM-11]
: The design is 'tic_tac_toe_game'.

Slack Endpoint Cost Group

--------------------------------------------------------
+535ps position_reg_unit/pos9_reg[1]/D default

Area
----

Instance Cells Cell Area Net Area Wireload

------------------------------------------------------------
tic_tac_toe_game 211 1418 0 enG5K (S)

(S) = wireload was automatically selected

Design Rule Check

-----------------
Initializing DRC engine.

Max_transition design rule: no violations.

Max_capacitance design rule: no violations.

Max_fanout design rule: no violations.

(iii) RESULT 1 (After route)

#
####################################################################

# Created by Encounter(R) RTL Compiler v08.10-s116_1 on Thu Apr 11

[Link] IST 2019

#
####################################################################
set sdc_version 1.7

set_units -capacitance 1000.0fF

set_units -time 1000.0ps

# Set the current design

current_design tic_tac_toe_game

create_clock -name "clock" -add -period 3.5 -waveform {0.0 1.75}

[get_ports clock]
set_clock_gating_check -setup 0.0
set_wire_load_mode "enclosed"
set_wire_load_selection_group "DEFAULT" -library
"fsd0k_a_generic_core_1d0vtc"
set_dont_use [get_lib_cells fsd0k_a_generic_core_1d0vtc/CKLDRL]
## List of unsupported SDC commands ##

(iii) Area Report ( AFTER ROUTE):

Instance Cells Cell Area Net Area Wireload

--------------------------------------------------------------------
tic_tac_toe_game 216 1445 0 enG5K (S)
position_reg_unit 65 564 0 enG5K (S)
win_detect_unit 81 466 0 enG5K (S)
u8 9 51 0 enG5K (S)
u7 9 51 0 enG5K (S)
u6 9 51 0 enG5K (S)
u5 9 51 0 enG5K (S)
u3 9 51 0 enG5K (S)
u2 9 51 0 enG5K (S)
u4 9 47 0 enG5K (S)
u1 9 47 0 enG5K (S)
imd_unit 18 122 0 enG5K (S)
tic_tac_toe_controller 15 102 0 enG5K (S)
pd2 16 75 0 enG5K (S)
pd1 16 75 0 enG5K (S)
nsd_unit 5 41 0 enG5K (S)

(S) = wireload was automatically selected

(iii) Gate Report ( AFTER ROUTE):
============================================================
Generated by: Encounter(R) RTL Compiler v08.10-s116_1
Generated on: Apr 11 2019 [Link] PM
Module: tic_tac_toe_game
Technology library: fsd0k_a_generic_core_1d0vtc 2007Q2v1.3
Operating conditions: _nominal_ (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================

Gate Instances Area Library

---------------------------------------------------------------
AN2B1RLXLP 12 60.000 fsd0k_a_generic_core_1d0vtc
AN2RLX1 9 45.000 fsd0k_a_generic_core_1d0vtc
AN2RLXLP 16 80.000 fsd0k_a_generic_core_1d0vtc
AN3RLX1 1 7.000 fsd0k_a_generic_core_1d0vtc
AN4B1RLX1 3 24.000 fsd0k_a_generic_core_1d0vtc
AN4RLX1 1 10.000 fsd0k_a_generic_core_1d0vtc
AO12RLX1 10 70.000 fsd0k_a_generic_core_1d0vtc
AO222RLX1 1 12.000 fsd0k_a_generic_core_1d0vtc
AOI112RLX1 2 14.000 fsd0k_a_generic_core_1d0vtc
AOI222RLX1 1 11.000 fsd0k_a_generic_core_1d0vtc
AOI22RLX1 4 28.000 fsd0k_a_generic_core_1d0vtc
AOI23RLX1 1 8.000 fsd0k_a_generic_core_1d0vtc
INVCKRLX1 1 3.000 fsd0k_a_generic_core_1d0vtc
INVRLX1 22 66.000 fsd0k_a_generic_core_1d0vtc
MAOI1RLX1 6 54.000 fsd0k_a_generic_core_1d0vtc
MOAI1RLX1 1 8.000 fsd0k_a_generic_core_1d0vtc
MXL2RLXLP 8 56.000 fsd0k_a_generic_core_1d0vtc
ND2RLX1 17 68.000 fsd0k_a_generic_core_1d0vtc
ND2RLXLP 6 24.000 fsd0k_a_generic_core_1d0vtc
NR2RLX1 17 68.000 fsd0k_a_generic_core_1d0vtc
NR2RLXLP 13 52.000 fsd0k_a_generic_core_1d0vtc
NR3RLX1 1 6.000 fsd0k_a_generic_core_1d0vtc
OA112RLX1 6 54.000 fsd0k_a_generic_core_1d0vtc
OA222RLX1 1 12.000 fsd0k_a_generic_core_1d0vtc
OAI122RLX1 1 9.000 fsd0k_a_generic_core_1d0vtc
OAI22RLX1 15 105.000 fsd0k_a_generic_core_1d0vtc
OAI23RLX1 1 8.000 fsd0k_a_generic_core_1d0vtc
OR2B1RLXLP 4 20.000 fsd0k_a_generic_core_1d0vtc
OR2RLX1 7 35.000 fsd0k_a_generic_core_1d0vtc
OR3B2RLX1 2 14.000 fsd0k_a_generic_core_1d0vtc
OR4B1RLX1 1 8.000 fsd0k_a_generic_core_1d0vtc
OR4B1RLXLP 2 16.000 fsd0k_a_generic_core_1d0vtc
OR4RLX1 1 10.000 fsd0k_a_generic_core_1d0vtc
OR4RLXLP 2 20.000 fsd0k_a_generic_core_1d0vtc
QDFFRBRLX1 20 360.000 fsd0k_a_generic_core_1d0vtc
---------------------------------------------------------------
total 216 1445.000
Type Instances Area Area %
-------------------------------------
sequential 20 360.000 24.9
inverter 23 69.000 4.8
logic 173 1016.000 70.3
-------------------------------------
total 216 1445.000 100.0

(iii) Power Report ( AFTER ROUTE):

Leakage Dynamic Total

Instance Cells Power(nW) Power(nW) Power(nW)
-------------------------------------------------------------
tic_tac_toe_game 216 4.134 69951.473 69955.607
position_reg_unit 65 1.758 48362.211 48363.968
win_detect_unit 81 1.317 3599.944 3601.261
u3 9 0.132 291.221 291.353
u6 9 0.130 605.573 605.703
u8 9 0.128 530.970 531.099
u5 9 0.128 438.996 439.124
u2 9 0.128 474.159 474.287
u7 9 0.127 281.433 281.560
u4 9 0.114 308.829 308.942
u1 9 0.112 302.459 302.571
imd_unit 18 0.391 1346.227 1346.618
tic_tac_toe_controller 15 0.302 7081.341 7081.643
pd2 16 0.147 543.581 543.728
pd1 16 0.144 670.054 670.198
nsd_unit 5 0.074 451.973 452.047

(iii) Netlist ( AFTER ROUTE):

// Generated by Cadence Encounter(R) RTL Compiler v08.10-s116_1

module illegal_move_detector(pos1, pos2, pos3, pos4, pos5, pos6,

pos7,
pos8, pos9, PC_en, PL_en, illegal_move);
input [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
input [8:0] PC_en, PL_en;
output illegal_move;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire [8:0] PC_en, PL_en;
wire illegal_move;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
wire n_16;
ND2RLX1 g633(.I1 (n_16), .I2 (n_15), .O (illegal_move));
AN4B1RLX1 g634(.I1 (n_10), .I2 (n_12), .I3 (n_13), .B1 (n_14), .O
(n_16));
AN4RLX1 g635(.I1 (n_7), .I2 (n_8), .I3 (n_11), .I4 (n_9), .O
(n_15));
AO222RLX1 g636(.A1 (n_3), .A2 (PL_en[1]), .B1 (n_0), .B2
(PC_en[7]),
.C1 (n_4), .C2 (PC_en[8]), .O (n_14));
AOI222RLX1 g637(.A1 (n_1), .A2 (PL_en[2]), .B1 (n_2), .B2
(PL_en[0]),
.C1 (n_6), .C2 (PL_en[3]), .O (n_13));
AOI22RLX1 g638(.A1 (n_3), .A2 (PC_en[1]), .B1 (n_4), .B2
(PL_en[8]),
.O (n_12));
AOI22RLX1 g639(.A1 (n_5), .A2 (PC_en[4]), .B1 (n_0), .B2
(PL_en[7]),
.O (n_11));
AOI22RLX1 g640(.A1 (n_1), .A2 (PC_en[2]), .B1 (n_2), .B2
(PC_en[0]),
.O (n_10));
AOI22RLX1 g641(.A1 (n_6), .A2 (PC_en[3]), .B1 (n_5), .B2
(PL_en[4]),
.O (n_9));
OAI22RLX1 g642(.A1 (pos7[0]), .A2 (pos7[1]), .B1 (PC_en[6]), .B2
(PL_en[6]), .O (n_8));
OAI22RLX1 g643(.A1 (pos6[1]), .A2 (pos6[0]), .B1 (PC_en[5]), .B2
(PL_en[5]), .O (n_7));
OR2RLX1 g644(.I1 (pos4[1]), .I2 (pos4[0]), .O (n_6));
OR2RLX1 g645(.I1 (pos5[1]), .I2 (pos5[0]), .O (n_5));
OR2RLX1 g646(.I1 (pos9[1]), .I2 (pos9[0]), .O (n_4));
OR2RLX1 g647(.I1 (pos2[1]), .I2 (pos2[0]), .O (n_3));
OR2RLX1 g648(.I1 (pos1[1]), .I2 (pos1[0]), .O (n_2));
OR2RLX1 g649(.I1 (pos3[1]), .I2 (pos3[0]), .O (n_1));
OR2RLX1 g650(.I1 (pos8[1]), .I2 (pos8[0]), .O (n_0));
endmodule

module nospace_detector(pos1, pos2, pos3, pos4, pos5, pos6, pos7,

pos8,
pos9, no_space);
input [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
output no_space;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire no_space;
wire n_0, n_1, n_2, n_3;
NR3RLX1 g225(.I1 (n_1), .I2 (n_0), .I3 (n_3), .O (no_space));
OAI122RLX1 g226(.A1 (n_2), .B1 (pos1[0]), .B2 (pos1[1]), .C1
(pos2[0]), .C2 (pos2[1]), .O (n_3));
OA222RLX1 g227(.A1 (pos7[0]), .A2 (pos7[1]), .B1 (pos3[0]), .B2
(pos3[1]), .C1 (pos6[0]), .C2 (pos6[1]), .O (n_2));
OAI22RLX1 g228(.A1 (pos4[0]), .A2 (pos4[1]), .B1 (pos5[0]), .B2
(pos5[1]), .O (n_1));
OAI22RLX1 g229(.A1 (pos9[0]), .A2 (pos9[1]), .B1 (pos8[0]), .B2
(pos8[1]), .O (n_0));
endmodule

module position_decoder(in, enable, out_en);

input [3:0] in;
input enable;
output [15:0] out_en;
wire [3:0] in;
wire enable;
wire [15:0] out_en;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6;
assign out_en[9] = 1'b0;
assign out_en[10] = 1'b0;
assign out_en[11] = 1'b0;
assign out_en[12] = 1'b0;
assign out_en[13] = 1'b0;
assign out_en[14] = 1'b0;
assign out_en[15] = 1'b0;
AN4B1RLX1 g245(.I1 (enable), .I2 (n_4), .I3 (in[3]), .B1 (in[0]),
.O
(out_en[8]));
NR2RLX1 g246(.I1 (n_0), .I2 (n_5), .O (out_en[7]));
NR2RLX1 g247(.I1 (n_1), .I2 (n_5), .O (out_en[5]));
NR2RLX1 g248(.I1 (n_1), .I2 (n_6), .O (out_en[4]));
NR2RLX1 g249(.I1 (n_2), .I2 (n_5), .O (out_en[3]));
NR2RLX1 g250(.I1 (n_2), .I2 (n_6), .O (out_en[2]));
NR2RLX1 g251(.I1 (n_0), .I2 (n_6), .O (out_en[6]));
AN2B1RLXLP g252(.I1 (n_4), .B1 (n_5), .O (out_en[1]));
AN2B1RLXLP g253(.I1 (n_4), .B1 (n_6), .O (out_en[0]));
ND2RLX1 g254(.I1 (enable), .I2 (n_3), .O (n_6));
OR3B2RLX1 g255(.I1 (in[3]), .B1 (enable), .B2 (in[0]), .O (n_5));
NR2RLX1 g256(.I1 (in[2]), .I2 (in[1]), .O (n_4));
NR2RLXLP g257(.I1 (in[0]), .I2 (in[3]), .O (n_3));
OR2B1RLXLP g258(.I1 (in[2]), .B1 (in[1]), .O (n_2));
OR2B1RLXLP g259(.I1 (in[1]), .B1 (in[2]), .O (n_1));
ND2RLXLP g260(.I1 (in[2]), .I2 (in[1]), .O (n_0));
endmodule

module position_decoder_169(in, enable, out_en);

input [3:0] in;
input enable;
output [15:0] out_en;
wire [3:0] in;
wire enable;
wire [15:0] out_en;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6;
assign out_en[9] = 1'b0;
assign out_en[10] = 1'b0;
assign out_en[11] = 1'b0;
assign out_en[12] = 1'b0;
assign out_en[13] = 1'b0;
assign out_en[14] = 1'b0;
assign out_en[15] = 1'b0;
AN4B1RLX1 g245(.I1 (enable), .I2 (n_4), .I3 (in[3]), .B1 (in[0]),
.O
(out_en[8]));
NR2RLX1 g246(.I1 (n_0), .I2 (n_5), .O (out_en[7]));
NR2RLX1 g247(.I1 (n_1), .I2 (n_5), .O (out_en[5]));
NR2RLX1 g248(.I1 (n_1), .I2 (n_6), .O (out_en[4]));
NR2RLX1 g249(.I1 (n_2), .I2 (n_5), .O (out_en[3]));
NR2RLX1 g250(.I1 (n_2), .I2 (n_6), .O (out_en[2]));
NR2RLX1 g251(.I1 (n_0), .I2 (n_6), .O (out_en[6]));
AN2B1RLXLP g252(.I1 (n_4), .B1 (n_5), .O (out_en[1]));
AN2B1RLXLP g253(.I1 (n_4), .B1 (n_6), .O (out_en[0]));
ND2RLX1 g254(.I1 (enable), .I2 (n_3), .O (n_6));
OR3B2RLX1 g255(.I1 (in[3]), .B1 (enable), .B2 (in[0]), .O (n_5));
NR2RLX1 g256(.I1 (in[2]), .I2 (in[1]), .O (n_4));
NR2RLXLP g257(.I1 (in[0]), .I2 (in[3]), .O (n_3));
OR2B1RLXLP g258(.I1 (in[2]), .B1 (in[1]), .O (n_2));
OR2B1RLXLP g259(.I1 (in[1]), .B1 (in[2]), .O (n_1));
ND2RLXLP g260(.I1 (in[2]), .I2 (in[1]), .O (n_0));
endmodule

module position_registers(clock, reset, illegal_move, PC_en, PL_en,

pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9);
input clock, reset, illegal_move;
input [8:0] PC_en, PL_en;
output [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire clock, reset, illegal_move;
wire [8:0] PC_en, PL_en;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
wire n_16, n_17, n_18, n_19, n_20, n_21, n_22, n_23;
wire n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31;
wire n_32, n_33, n_34, n_35, n_36, n_37, n_38, n_39;
wire n_40, n_41, n_42, n_43, n_44, n_45, n_46;
QDFFRBRLX1 \pos1_reg[1] (.RB (n_5), .CK (clock), .D (n_46), .Q
(pos1[1]));
QDFFRBRLX1 \pos3_reg[1] (.RB (n_5), .CK (clock), .D (n_45), .Q
(pos3[1]));
QDFFRBRLX1 \pos4_reg[1] (.RB (n_5), .CK (clock), .D (n_44), .Q
(pos4[1]));
QDFFRBRLX1 \pos5_reg[1] (.RB (n_5), .CK (clock), .D (n_43), .Q
(pos5[1]));
QDFFRBRLX1 \pos6_reg[1] (.RB (n_5), .CK (clock), .D (n_42), .Q
(pos6[1]));
QDFFRBRLX1 \pos2_reg[1] (.RB (n_5), .CK (clock), .D (n_39), .Q
(pos2[1]));
QDFFRBRLX1 \pos7_reg[1] (.RB (n_5), .CK (clock), .D (n_41), .Q
(pos7[1]));
QDFFRBRLX1 \pos8_reg[1] (.RB (n_5), .CK (clock), .D (n_40), .Q
(pos8[1]));
QDFFRBRLX1 \pos9_reg[1] (.RB (n_5), .CK (clock), .D (n_38), .Q
(pos9[1]));
QDFFRBRLX1 \pos3_reg[0] (.RB (n_5), .CK (clock), .D (n_34), .Q
(pos3[0]));
QDFFRBRLX1 \pos4_reg[0] (.RB (n_5), .CK (clock), .D (n_37), .Q
(pos4[0]));
QDFFRBRLX1 \pos5_reg[0] (.RB (n_5), .CK (clock), .D (n_36), .Q
(pos5[0]));
QDFFRBRLX1 \pos6_reg[0] (.RB (n_5), .CK (clock), .D (n_33), .Q
(pos6[0]));
QDFFRBRLX1 \pos2_reg[0] (.RB (n_5), .CK (clock), .D (n_30), .Q
(pos2[0]));
QDFFRBRLX1 \pos7_reg[0] (.RB (n_5), .CK (clock), .D (n_32), .Q
(pos7[0]));
QDFFRBRLX1 \pos8_reg[0] (.RB (n_5), .CK (clock), .D (n_31), .Q
(pos8[0]));
QDFFRBRLX1 \pos1_reg[0] (.RB (n_5), .CK (clock), .D (n_35), .Q
(pos1[0]));
QDFFRBRLX1 \pos9_reg[0] (.RB (n_5), .CK (clock), .D (n_29), .Q
(pos9[0]));
AO12RLX1 g987(.A1 (n_21), .B1 (pos1[1]), .B2 (n_18), .O (n_46));
AO12RLX1 g988(.A1 (n_24), .B1 (pos3[1]), .B2 (n_11), .O (n_45));
AO12RLX1 g989(.A1 (n_26), .B1 (pos4[1]), .B2 (n_25), .O (n_44));
AO12RLX1 g990(.A1 (n_23), .B1 (pos5[1]), .B2 (n_22), .O (n_43));
AO12RLX1 g991(.A1 (n_20), .B1 (pos6[1]), .B2 (n_19), .O (n_42));
AO12RLX1 g992(.A1 (n_17), .B1 (pos7[1]), .B2 (n_16), .O (n_41));
AO12RLX1 g993(.A1 (n_13), .B1 (pos8[1]), .B2 (n_14), .O (n_40));
AO12RLX1 g994(.A1 (n_15), .B1 (pos2[1]), .B2 (n_27), .O (n_39));
AO12RLX1 g995(.A1 (n_12), .B1 (pos9[1]), .B2 (n_28), .O (n_38));
OAI22RLX1 g996(.A1 (PC_en[3]), .A2 (n_25), .B1 (n_26), .B2 (n_8),
.O
(n_37));
OAI22RLX1 g997(.A1 (PC_en[4]), .A2 (n_22), .B1 (n_9), .B2 (n_23),
.O
(n_36));
OAI22RLX1 g998(.A1 (PC_en[0]), .A2 (n_18), .B1 (n_21), .B2 (n_2),
.O
(n_35));
OAI22RLX1 g999(.A1 (PC_en[2]), .A2 (n_11), .B1 (n_24), .B2 (n_1),
.O
(n_34));
OAI22RLX1 g1000(.A1 (PC_en[5]), .A2 (n_19), .B1 (n_4), .B2 (n_20),
.O
(n_33));
OAI22RLX1 g1001(.A1 (PC_en[6]), .A2 (n_16), .B1 (n_17), .B2 (n_0),
.O
(n_32));
OAI22RLX1 g1002(.A1 (PC_en[7]), .A2 (n_14), .B1 (n_13), .B2 (n_7),
.O
(n_31));
OAI22RLX1 g1003(.A1 (PC_en[1]), .A2 (n_27), .B1 (n_15), .B2 (n_6),
.O
(n_30));
OAI22RLX1 g1004(.A1 (PC_en[8]), .A2 (n_28), .B1 (n_3), .B2 (n_12),
.O
(n_29));
ND2RLX1 g1005(.I1 (n_10), .I2 (PL_en[8]), .O (n_28));
ND2RLX1 g1006(.I1 (n_10), .I2 (PL_en[1]), .O (n_27));
AN2RLX1 g1007(.I1 (n_10), .I2 (PC_en[3]), .O (n_26));
ND2RLX1 g1008(.I1 (n_10), .I2 (PL_en[3]), .O (n_25));
AN2RLX1 g1009(.I1 (n_10), .I2 (PC_en[2]), .O (n_24));
AN2RLX1 g1010(.I1 (n_10), .I2 (PC_en[4]), .O (n_23));
ND2RLX1 g1011(.I1 (n_10), .I2 (PL_en[4]), .O (n_22));
AN2RLX1 g1012(.I1 (n_10), .I2 (PC_en[0]), .O (n_21));
AN2RLX1 g1013(.I1 (n_10), .I2 (PC_en[5]), .O (n_20));
ND2RLX1 g1014(.I1 (n_10), .I2 (PL_en[5]), .O (n_19));
ND2RLX1 g1015(.I1 (n_10), .I2 (PL_en[0]), .O (n_18));
AN2RLX1 g1016(.I1 (n_10), .I2 (PC_en[6]), .O (n_17));
ND2RLX1 g1017(.I1 (n_10), .I2 (PL_en[6]), .O (n_16));
AN2RLX1 g1018(.I1 (n_10), .I2 (PC_en[1]), .O (n_15));
ND2RLX1 g1019(.I1 (n_10), .I2 (PL_en[7]), .O (n_14));
AN2RLX1 g1020(.I1 (n_10), .I2 (PC_en[7]), .O (n_13));
AN2RLX1 g1021(.I1 (n_10), .I2 (PC_en[8]), .O (n_12));
ND2RLX1 g1022(.I1 (n_10), .I2 (PL_en[2]), .O (n_11));
INVRLX1 g1023(.I (illegal_move), .O (n_10));
INVRLX1 g1024(.I (pos5[0]), .O (n_9));
INVRLX1 g1025(.I (pos4[0]), .O (n_8));
INVRLX1 g1026(.I (pos8[0]), .O (n_7));
INVRLX1 g1027(.I (pos2[0]), .O (n_6));
INVCKRLX1 g1028(.I (reset), .O (n_5));
INVRLX1 g1029(.I (pos6[0]), .O (n_4));
INVRLX1 g1030(.I (pos9[0]), .O (n_3));
INVRLX1 g1031(.I (pos1[0]), .O (n_2));
INVRLX1 g1032(.I (pos3[0]), .O (n_1));
INVRLX1 g1033(.I (pos7[0]), .O (n_0));
endmodule

module fsm_controller(clock, reset, play, pc, illegal_move,

no_space,
win, computer_play, player_play);
input clock, reset, play, pc, illegal_move, no_space, win;
output computer_play, player_play;
wire clock, reset, play, pc, illegal_move, no_space, win;
wire computer_play, player_play;
wire \current_state[1] , n_0, n_1, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_12, n_15;
AN3RLX1 g113(.I1 (n_15), .I2 (\current_state[1] ), .I3 (pc), .O
(computer_play));
NR2RLX1 g114(.I1 (\current_state[1] ), .I2 (n_15), .O
(player_play));
INVRLX1 g115(.I (n_12), .O (n_15));
QDFFRBRLX1 \current_state_reg[1] (.RB (n_0), .CK (clock), .D
(n_10),
.Q (\current_state[1] ));
INVRLX1 g253(.I (n_9), .O (n_10));
AOI23RLX1 g254(.A1 (n_5), .A2 (n_7), .B1 (n_12), .B2
(\current_state[1] ), .B3 (n_0), .O (n_9));
QDFFRBRLX1 \current_state_reg[0] (.RB (n_0), .CK (clock), .D
(n_8),
.Q (n_12));
OAI23RLX1 g256(.A1 (n_1), .A2 (n_3), .B1 (n_5), .B2 (n_4), .B3
(reset), .O (n_8));
MOAI1RLX1 g257(.A1 (n_15), .A2 (illegal_move), .B1 (n_15), .B2
(n_6),
.O (n_7));
ND2RLX1 g258(.I1 (n_3), .I2 (pc), .O (n_6));
AO12RLX1 g259(.A1 (player_play), .B1 (\current_state[1] ), .B2
(n_15), .O (n_5));
NR2RLXLP g260(.I1 (play), .I2 (n_12), .O (n_4));
NR2RLX1 g261(.I1 (no_space), .I2 (win), .O (n_3));
INVRLX1 g263(.I (computer_play), .O (n_1));
INVRLX1 g264(.I (reset), .O (n_0));
endmodule

module winner_detect_3(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4, n_5;
AN2RLXLP g165(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g166(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
AOI112RLX1 g167(.A1 (n_5), .B1 (n_4), .C1 (n_1), .C2 (pos2[0]), .O
(winner));
OAI22RLX1 g168(.A1 (pos2[0]), .A2 (n_2), .B1 (n_3), .B2 (pos2[1]),
.O
(n_5));
MXL2RLXLP g169(.S (pos0[1]), .A (n_0), .B (pos1[1]), .OB (n_4));
AN2B1RLXLP g170(.I1 (pos0[0]), .B1 (pos1[1]), .O (n_3));
NR2RLXLP g171(.I1 (pos1[0]), .I2 (pos0[0]), .O (n_2));
ND2RLX1 g172(.I1 (pos0[0]), .I2 (pos1[0]), .O (n_1));
INVRLX1 g173(.I (pos2[1]), .O (n_0));
endmodule

module winner_detect_3_101(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4, n_5;
AN2RLXLP g167(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g168(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
OA112RLX1 g169(.A1 (n_5), .B1 (n_4), .C1 (n_1), .C2 (pos2[0]), .O
(winner));
MAOI1RLX1 g170(.A1 (n_3), .A2 (pos2[0]), .B1 (pos2[1]), .B2 (n_2),
.O
(n_5));
MXL2RLXLP g171(.S (pos0[1]), .A (pos2[1]), .B (n_0), .OB (n_4));
ND2RLXLP g172(.I1 (pos1[0]), .I2 (pos0[0]), .O (n_3));
AN2B1RLXLP g173(.I1 (pos0[0]), .B1 (pos1[1]), .O (n_2));
NR2RLXLP g174(.I1 (pos0[0]), .I2 (pos1[0]), .O (n_1));
INVRLX1 g175(.I (pos1[1]), .O (n_0));
endmodule

module winner_detect_3_106(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4, n_5;
AN2RLXLP g167(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g168(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
OA112RLX1 g169(.A1 (n_5), .B1 (n_4), .C1 (n_1), .C2 (pos2[0]), .O
(winner));
MAOI1RLX1 g170(.A1 (n_3), .A2 (pos2[0]), .B1 (pos2[1]), .B2 (n_2),
.O
(n_5));
MXL2RLXLP g171(.S (pos0[1]), .A (pos2[1]), .B (n_0), .OB (n_4));
ND2RLX1 g172(.I1 (pos0[0]), .I2 (pos1[0]), .O (n_3));
AN2B1RLXLP g173(.I1 (pos0[0]), .B1 (pos1[1]), .O (n_2));
NR2RLXLP g174(.I1 (pos1[0]), .I2 (pos0[0]), .O (n_1));
INVRLX1 g175(.I (pos1[1]), .O (n_0));
endmodule

module winner_detect_3_111(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4, n_5;
AN2RLXLP g166(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g167(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
AOI112RLX1 g168(.A1 (n_5), .B1 (n_4), .C1 (n_1), .C2 (pos2[0]), .O
(winner));
OAI22RLX1 g169(.A1 (pos2[0]), .A2 (n_2), .B1 (n_3), .B2 (pos2[1]),
.O
(n_5));
MXL2RLXLP g170(.S (pos0[1]), .A (n_0), .B (pos1[1]), .OB (n_4));
AN2B1RLXLP g171(.I1 (pos0[0]), .B1 (pos1[1]), .O (n_3));
NR2RLXLP g172(.I1 (pos1[0]), .I2 (pos0[0]), .O (n_2));
ND2RLX1 g173(.I1 (pos0[0]), .I2 (pos1[0]), .O (n_1));
INVRLX1 g174(.I (pos2[1]), .O (n_0));
endmodule

module winner_detect_3_116(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4, n_5;
AN2RLXLP g168(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g169(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
OA112RLX1 g170(.A1 (n_5), .B1 (n_4), .C1 (n_1), .C2 (pos2[0]), .O
(winner));
MAOI1RLX1 g171(.A1 (n_3), .A2 (pos2[0]), .B1 (pos2[1]), .B2 (n_2),
.O
(n_5));
MXL2RLXLP g172(.S (pos0[1]), .A (pos2[1]), .B (n_0), .OB (n_4));
ND2RLXLP g173(.I1 (pos1[0]), .I2 (pos0[0]), .O (n_3));
AN2B1RLXLP g174(.I1 (pos0[0]), .B1 (pos1[1]), .O (n_2));
NR2RLXLP g175(.I1 (pos0[0]), .I2 (pos1[0]), .O (n_1));
INVRLX1 g176(.I (pos1[1]), .O (n_0));
endmodule

module winner_detect_3_121(pos0, pos1, pos2, winner, who);

input [1:0] pos0, pos1, pos2;
output winner;
output [1:0] who;
wire [1:0] pos0, pos1, pos2;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4, n_5;
AN2RLXLP g168(.I1 (winner), .I2 (pos0[1]), .O (who[1]));
AN2RLXLP g169(.I1 (winner), .I2 (pos0[0]), .O (who[0]));
OA112RLX1 g170(.A1 (n_5), .B1 (n_4), .C1 (n_1), .C2 (pos2[0]), .O
(winner));
MAOI1RLX1 g171(.A1 (n_3), .A2 (pos2[0]), .B1 (pos2[1]), .B2 (n_2),
.O
(n_5));
MXL2RLXLP g172(.S (pos0[1]), .A (pos2[1]), .B (n_0), .OB (n_4));
ND2RLX1 g173(.I1 (pos0[0]), .I2 (pos1[0]), .O (n_3));
AN2B1RLXLP g174(.I1 (pos0[0]), .B1 (pos1[1]), .O (n_2));
NR2RLXLP g175(.I1 (pos1[0]), .I2 (pos0[0]), .O (n_1));
INVRLX1 g176(.I (pos1[1]), .O (n_0));
endmodule

module winner_detect_3_126(pos0, pos1, pos2, winner, who);

module winner_detect_3_131(pos0, pos1, pos2, winner, who);

module winner_detector(pos1, pos2, pos3, pos4, pos5, pos6, pos7,

pos8,
pos9, winner, who);
input [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
output winner;
output [1:0] who;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire winner;
wire [1:0] who;
wire n_0, n_1, n_2, n_3, n_4, n_5, \who1[0] , \who1[1] ;
wire \who2[0] , \who2[1] , \who3[0] , \who3[1] , \who4[0] ,
\who4[1]
, \who5[0] , \who5[1] ;
wire \who6[0] , \who6[1] , \who7[0] , \who7[1] , \who8[0] ,
\who8[1]
, win1, win2;
wire win3, win4, win5, win6, win7, win8;
winner_detect_3 u1(.pos0 (pos1), .pos1 (pos2), .pos2 (pos3),
.winner
(win1), .who ({\who1[1] , \who1[0] }));
winner_detect_3_101 u2(.pos0 (pos4), .pos1 (pos5), .pos2 (pos6),
.winner (win2), .who ({\who2[1] , \who2[0] }));
winner_detect_3_106 u3(.pos0 (pos7), .pos1 (pos8), .pos2 (pos9),
.winner (win3), .who ({\who3[1] , \who3[0] }));
winner_detect_3_111 u4(.pos0 (pos1), .pos1 (pos4), .pos2 (pos7),
.winner (win4), .who ({\who4[1] , \who4[0] }));
winner_detect_3_116 u5(.pos0 (pos2), .pos1 (pos5), .pos2 (pos8),
.winner (win5), .who ({\who5[1] , \who5[0] }));
winner_detect_3_121 u6(.pos0 (pos3), .pos1 (pos6), .pos2 (pos9),
.winner (win6), .who ({\who6[1] , \who6[0] }));
winner_detect_3_126 u7(.pos0 (pos1), .pos1 (pos5), .pos2 (pos9),
.winner (win7), .who ({\who7[1] , \who7[0] }));
winner_detect_3_131 u8(.pos0 (pos3), .pos1 (pos5), .pos2 (pos6),
.winner (win8), .who ({\who8[1] , \who8[0] }));
OR4B1RLX1 g86(.I1 (win3), .I2 (n_5), .I3 (win1), .B1 (n_4), .O
(winner));
OR4RLX1 g87(.I1 (win4), .I2 (win5), .I3 (win2), .I4 (win8), .O
(n_5));
NR2RLX1 g88(.I1 (win6), .I2 (win7), .O (n_4));
OR4B1RLXLP g92(.I1 (\who8[1] ), .I2 (n_3), .I3 (\who5[1] ), .B1
(n_2), .O (who[1]));
OR4RLXLP g93(.I1 (\who2[1] ), .I2 (\who1[1] ), .I3 (\who7[1] ),
.I4
(\who3[1] ), .O (n_3));
NR2RLXLP g94(.I1 (\who4[1] ), .I2 (\who6[1] ), .O (n_2));
OR4B1RLXLP g95(.I1 (\who8[0] ), .I2 (n_1), .I3 (\who5[0] ), .B1
(n_0), .O (who[0]));
OR4RLXLP g96(.I1 (\who2[0] ), .I2 (\who1[0] ), .I3 (\who7[0] ),
.I4
(\who3[0] ), .O (n_1));
NR2RLXLP g97(.I1 (\who4[0] ), .I2 (\who6[0] ), .O (n_0));
endmodule

module tic_tac_toe_game(clock, reset, play, pc, computer_position,

player_position, pos1, pos2, pos3, pos4, pos5, pos6, pos7,
pos8,
pos9, who);
input clock, reset, play, pc;
input [3:0] computer_position, player_position;
output [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9,
who;
wire clock, reset, play, pc;
wire [3:0] computer_position, player_position;
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9,
who;
wire \PC_en[0] , \PC_en[1] , \PC_en[2] , \PC_en[3] , \PC_en[4] ,
\PC_en[5] , \PC_en[6] , \PC_en[7] ;
wire \PC_en[8] , \PL_en[0] , \PL_en[1] , \PL_en[2] , \PL_en[3] ,
\PL_en[4] , \PL_en[5] , \PL_en[6] ;
wire \PL_en[7] , \PL_en[8] , UNCONNECTED, UNCONNECTED0,
UNCONNECTED1,
UNCONNECTED2, UNCONNECTED3, UNCONNECTED4;
wire UNCONNECTED5, UNCONNECTED6, UNCONNECTED7, UNCONNECTED8,
UNCONNECTED9, UNCONNECTED10, UNCONNECTED11, UNCONNECTED12;
wire computer_play, illegal_move, no_space, player_play, win;
illegal_move_detector imd_unit(.pos1 (pos1), .pos2 (pos2), .pos3
(pos3), .pos4 (pos4), .pos5 (pos5), .pos6 (pos6), .pos7
(pos7),
.pos8 (pos8), .pos9 (pos9), .PC_en ({\PC_en[8] , \PC_en[7] ,
\PC_en[6] , \PC_en[5] , \PC_en[4] , \PC_en[3] , \PC_en[2] ,
\PC_en[1] , \PC_en[0] }), .PL_en ({\PL_en[8] , \PL_en[7] ,
\PL_en[6] , \PL_en[5] , \PL_en[4] , \PL_en[3] , \PL_en[2] ,
\PL_en[1] , \PL_en[0] }), .illegal_move (illegal_move));
nospace_detector nsd_unit(.pos1 (pos1), .pos2 (pos2), .pos3
(pos3),
.pos4 (pos4), .pos5 (pos5), .pos6 (pos6), .pos7 (pos7), .pos8
(pos8), .pos9 (pos9), .no_space (no_space));
position_decoder pd1(.in (computer_position), .enable
(computer_play), .out_en ({UNCONNECTED, UNCONNECTED0,
UNCONNECTED1, UNCONNECTED2, UNCONNECTED3, UNCONNECTED4,
UNCONNECTED5, \PC_en[8] , \PC_en[7] , \PC_en[6] , \PC_en[5] ,
\PC_en[4] , \PC_en[3] , \PC_en[2] , \PC_en[1] , \PC_en[0]
}));
position_decoder_169 pd2(.in (player_position), .enable
(player_play), .out_en ({UNCONNECTED6, UNCONNECTED7,
UNCONNECTED8, UNCONNECTED9, UNCONNECTED10, UNCONNECTED11,
UNCONNECTED12, \PL_en[8] , \PL_en[7] , \PL_en[6] , \PL_en[5]
,
\PL_en[4] , \PL_en[3] , \PL_en[2] , \PL_en[1] , \PL_en[0]
}));
position_registers position_reg_unit(.clock (clock), .reset
(reset),
.illegal_move (illegal_move), .PC_en ({\PC_en[8] , \PC_en[7]
,
\PC_en[6] , \PC_en[5] , \PC_en[4] , \PC_en[3] , \PC_en[2] ,
\PC_en[1] , \PC_en[0] }), .PL_en ({\PL_en[8] , \PL_en[7] ,
\PL_en[6] , \PL_en[5] , \PL_en[4] , \PL_en[3] , \PL_en[2] ,
\PL_en[1] , \PL_en[0] }), .pos1 (pos1), .pos2 (pos2), .pos3
(pos3), .pos4 (pos4), .pos5 (pos5), .pos6 (pos6), .pos7
(pos7),
.pos8 (pos8), .pos9 (pos9));
fsm_controller tic_tac_toe_controller(.clock (clock), .reset
(reset),
.play (play), .pc (pc), .illegal_move (illegal_move),
.no_space
(no_space), .win (win), .computer_play (computer_play),
.player_play (player_play));
winner_detector win_detect_unit(.pos1 (pos1), .pos2 (pos2), .pos3
(pos3), .pos4 (pos4), .pos5 (pos5), .pos6 (pos6), .pos7
(pos7),
.pos8 (pos8), .pos9 (pos9), .winner (win), .who (who));
endmodule

(iii) Slack Report ( AFTER ROUTE):

path 1:

Pin Type Fanout Load Slew Delay

Arrival
(fF) (ps) (ps)
(ps)
--------------------------------------------------------------------
-----
(clock clock) launch
0 R
tic_tac_toe_controller
current_state_reg[0]/CK 0
0 R
current_state_reg[0]/Q QDFFRBRLX1 3 9.5 44 +340
340 F
g115/I +0
340
g115/O INVRLX1 5 17.8 113 +165
505 R
g114/I2 +0
505
g114/O NR2RLX1 4 13.5 58 +140
645 F
tic_tac_toe_controller/player_play
pd2/enable
g254/I1 +0
645
g254/O ND2RLX1 4 13.7 97 +154
798 R
g253/B1 +0
798
g253/O AN2B1RLXLP 2 6.6 53 +130
928 F
pd2/out_en[0]
imd_unit/PL_en[0]
g637/B2 +0
928
g637/O AOI222RLX1 1 3.0 159 +311
1240 R
g634/I3 +0
1240
g634/O AN4B1RLX1 1 3.1 67 +267
1506 R
g633/I1 +0
1506
g633/O ND2RLX1 2 6.4 47 +104
1611 F
imd_unit/illegal_move
position_reg_unit/illegal_move
g1023/I +0
1611
g1023/O INVRLX1 18 64.4 383 +465
2076 R
g1005/I1 +0
2076
g1005/O ND2RLX1 2 5.9 103 +232
2308 F
g995/B2 +0
2308
g995/O AO12RLX1 1 2.2 29 +249
2557 F
pos9_reg[1]/D QDFFRBRLX1 +0
2557
pos9_reg[1]/CK setup 0 +233
2789 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
(clock clock) capture
3500 R
--------------------------------------------------------------------
-----
Timing slack : 711ps
Start-point : tic_tac_toe_controller/current_state_reg[0]/CK
End-point : position_reg_unit/pos9_reg[1]/D

path 2:

Pin Type Fanout Load Slew Delay

Arrival
(fF) (ps) (ps)
(ps)
--------------------------------------------------------------------
-----
(clock clock) launch
0 R
tic_tac_toe_controller
current_state_reg[0]/CK 0
0 R
current_state_reg[0]/Q QDFFRBRLX1 3 9.5 44 +340
340 F
g115/I +0
340
g115/O INVRLX1 5 17.8 113 +165
505 R
g114/I2 +0
505
g114/O NR2RLX1 4 13.5 58 +140
645 F
tic_tac_toe_controller/player_play
pd2/enable
g254/I1 +0
645
g254/O ND2RLX1 4 13.7 97 +154
798 R
g253/B1 +0
798
g253/O AN2B1RLXLP 2 6.6 53 +130
928 F
pd2/out_en[0]
imd_unit/PL_en[0]
g637/B2 +0
928
g637/O AOI222RLX1 1 3.0 159 +311
1240 R
g634/I3 +0
1240
g634/O AN4B1RLX1 1 3.1 67 +267
1506 R
g633/I1 +0
1506
g633/O ND2RLX1 2 6.4 47 +104
1611 F
imd_unit/illegal_move
position_reg_unit/illegal_move
g1023/I +0
1611
g1023/O INVRLX1 18 64.4 383 +465
2076 R
g1019/I1 +0
2076
g1019/O ND2RLX1 2 5.9 103 +232
2308 F
g993/B2 +0
2308
g993/O AO12RLX1 1 2.2 29 +249
2557 F
pos8_reg[1]/D QDFFRBRLX1 +0
2557
pos8_reg[1]/CK setup 0 +233
2789 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
(clock clock) capture
3500 R
--------------------------------------------------------------------
-----
Timing slack : 711ps
Start-point : tic_tac_toe_controller/current_state_reg[0]/CK
End-point : position_reg_unit/pos8_reg[1]/D

path 3:

Pin Type Fanout Load Slew Delay

Arrival
(fF) (ps) (ps)
(ps)
--------------------------------------------------------------------
-----
(clock clock) launch
0 R
tic_tac_toe_controller
current_state_reg[0]/CK 0
0 R
current_state_reg[0]/Q QDFFRBRLX1 3 9.5 44 +340
340 F
g115/I +0
340
g115/O INVRLX1 5 17.8 113 +165
505 R
g114/I2 +0
505
g114/O NR2RLX1 4 13.5 58 +140
645 F
tic_tac_toe_controller/player_play
pd2/enable
g254/I1 +0
645
g254/O ND2RLX1 4 13.7 97 +154
798 R
g253/B1 +0
798
g253/O AN2B1RLXLP 2 6.6 53 +130
928 F
pd2/out_en[0]
imd_unit/PL_en[0]
g637/B2 +0
928
g637/O AOI222RLX1 1 3.0 159 +311
1240 R
g634/I3 +0
1240
g634/O AN4B1RLX1 1 3.1 67 +267
1506 R
g633/I1 +0
1506
g633/O ND2RLX1 2 6.4 47 +104
1611 F
imd_unit/illegal_move
position_reg_unit/illegal_move
g1023/I +0
1611
g1023/O INVRLX1 18 64.4 383 +465
2076 R
g1017/I1 +0
2076
g1017/O ND2RLX1 2 5.9 103 +232
2308 F
g992/B2 +0
2308
g992/O AO12RLX1 1 2.2 29 +249
2557 F
pos7_reg[1]/D QDFFRBRLX1 +0
2557
pos7_reg[1]/CK setup 0 +233
2789 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
(clock clock) capture
3500 R
--------------------------------------------------------------------
-----
Timing slack : 711ps
Start-point : tic_tac_toe_controller/current_state_reg[0]/CK
End-point : position_reg_unit/pos7_reg[1]/D

path 4:

Pin Type Fanout Load Slew Delay

Arrival
(fF) (ps) (ps)
(ps)
--------------------------------------------------------------------
-----
(clock clock) launch
0 R
tic_tac_toe_controller
current_state_reg[0]/CK 0
0 R
current_state_reg[0]/Q QDFFRBRLX1 3 9.5 44 +340
340 F
g115/I +0
340
g115/O INVRLX1 5 17.8 113 +165
505 R
g114/I2 +0
505
g114/O NR2RLX1 4 13.5 58 +140
645 F
tic_tac_toe_controller/player_play
pd2/enable
g254/I1 +0
645
g254/O ND2RLX1 4 13.7 97 +154
798 R
g253/B1 +0
798
g253/O AN2B1RLXLP 2 6.6 53 +130
928 F
pd2/out_en[0]
imd_unit/PL_en[0]
g637/B2 +0
928
g637/O AOI222RLX1 1 3.0 159 +311
1240 R
g634/I3 +0
1240
g634/O AN4B1RLX1 1 3.1 67 +267
1506 R
g633/I1 +0
1506
g633/O ND2RLX1 2 6.4 47 +104
1611 F
imd_unit/illegal_move
position_reg_unit/illegal_move
g1023/I +0
1611
g1023/O INVRLX1 18 64.4 383 +465
2076 R
g1006/I1 +0
2076
g1006/O ND2RLX1 2 5.9 103 +232
2308 F
g994/B2 +0
2308
g994/O AO12RLX1 1 2.2 29 +249
2557 F
pos2_reg[1]/D QDFFRBRLX1 +0
2557
pos2_reg[1]/CK setup 0 +233
2789 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
(clock clock) capture
3500 R
--------------------------------------------------------------------
-----
Timing slack : 711ps
Start-point : tic_tac_toe_controller/current_state_reg[0]/CK
End-point : position_reg_unit/pos2_reg[1]/D

(iii) DRC ( AFTER ROUTE):

Slack Endpoint Cost Group

--------------------------------------------------------
+711ps position_reg_unit/pos9_reg[1]/D default

Area
----

Instance Cells Cell Area Net Area Wireload

------------------------------------------------------------
tic_tac_toe_game 216 1445 0 enG5K (S)

(S) = wireload was automatically selected

Design Rule Check
-----------------
Initializing DRC engine.

Max_transition design rule: no violations.

Max_capacitance design rule: no violations.

Max_fanout design rule: no violations.

4: Comparison of the results (Before and After Routing)

i) BEFORE:

Parameter SOC Encounter

No. Of Cells 211
Area 1418
Total Power(nW) 69988.931
Slack (Worst Case Delay)(ps) 535

i) AFTER:
Parameter SOC Encounter
No. Of Cells 216
Area 1445
Total Power(nW) 69955.607
Slack (Worst Case Delay)(ps) 711
APPENDIX

Code with explaination through detailed comments

// Verilog code for TIC TAC TOE GAME

// Top level module

module tic_tac_toe_game(

input clock, // clock of the game

input reset, // reset button to reset the game

input play, // play button to enable player to play

input pc, // pc button to enable computer to play

input [3:0] computer_position,player_position,

// positions to play

output wire [1:0] pos1,pos2,pos3,

pos4,pos5,pos6,pos7,pos8,pos9,

// LED display for positions

// 01: Player

// 10: Computer

output wire[1:0]who

// who the winner is

);

wire [15:0] PC_en;// Computer enable signals

wire [15:0] PL_en; // Player enable signals

wire illegal_move; // disable writing when an illegal move is detected

//wire [1:0] pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9;// positions stored

wire win; // win signal

wire computer_play; // computer enabling signal

wire player_play; // player enabling signal

wire no_space; // no space signal

// position registers
position_registers position_reg_unit(

clock, // clock of the game

reset, // reset the game

illegal_move, // disable writing when an illegal move is detected

PC_en[8:0], // Computer enable signals

PL_en[8:0], // Player enable signals

pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9// positions stored

);

// winner detector

winner_detector win_detect_unit(pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,win,who);

// position decoder for computer

position_decoder pd1(computer_position,computer_play,PC_en);

// position decoder for player

position_decoder pd2(player_position,player_play,PL_en);

// illegal move detector

illegal_move_detector imd_unit(

pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,

PC_en[8:0], PL_en[8:0],

illegal_move

);

// no space detector

nospace_detector nsd_unit(

pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,

no_space

);

fsm_controller tic_tac_toe_controller(

clock,// clock of the circuit

reset,// reset

play, // player plays

pc,// computer plays

illegal_move,// illegal move detected

no_space, // no_space detected

win, // winner detected

computer_play, // enable computer to play

player_play // enable player to play

);

endmodule

// Position registers

// to store player or computer positions

// when enabling by the FSM controller

module position_registers(

input clock, // clock of the game

input reset, // reset the game

input illegal_move, // disable writing when an illegal move is detected

input [8:0] PC_en, // Computer enable signals

input [8:0] PL_en, // Player enable signals

output reg[1:0] pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9// positions stored

);

// Position 1

always @(posedge clock or posedge reset)

begin

if(reset)

pos1 <= 2'b00;

else begin

if(illegal_move==1'b1)

pos1 <= pos1;// keep previous position

else if(PC_en[0]==1'b1)

pos1 <= 2'b10; // store computer data

else if (PL_en[0]==1'b1)

pos1 <= 2'b01;// store player data

else

pos1 <= pos1;// keep previous position

end

// Position 2

always @(posedge clock or posedge reset)

begin

if(reset)

pos2 <= 2'b00;

else begin

if(illegal_move==1'b1)

pos2 <= pos2;// keep previous position

else if(PC_en[1]==1'b1)

pos2 <= 2'b10; // store computer data

else if (PL_en[1]==1'b1)

pos2 <= 2'b01;// store player data

else

pos2 <= pos2;// keep previous position

end

// Position 3

always @(posedge clock or posedge reset)

begin

if(reset)

pos3 <= 2'b00;

else begin

if(illegal_move==1'b1)
pos3 <= pos3;// keep previous position

else if(PC_en[2]==1'b1)

pos3 <= 2'b10; // store computer data

else if (PL_en[2]==1'b1)

pos3 <= 2'b01;// store player data

else

pos3 <= pos3;// keep previous position

end

// Position 4

always @(posedge clock or posedge reset)

begin

if(reset)

pos4 <= 2'b00;

else begin

if(illegal_move==1'b1)

pos4 <= pos4;// keep previous position

else if(PC_en[3]==1'b1)

pos4 <= 2'b10; // store computer data

else if (PL_en[3]==1'b1)

pos4 <= 2'b01;// store player data

else

pos4 <= pos4;// keep previous position

end

// Position 5

always @(posedge clock or posedge reset)

begin

if(reset)
pos5 <= 2'b00;

else begin

if(illegal_move==1'b1)

pos5 <= pos5;// keep previous position

else if(PC_en[4]==1'b1)

pos5 <= 2'b10; // store computer data

else if (PL_en[4]==1'b1)

pos5 <= 2'b01;// store player data

else

pos5 <= pos5;// keep previous position

end

// Position 6

always @(posedge clock or posedge reset)

begin

if(reset)

pos6 <= 2'b00;

else begin

if(illegal_move==1'b1)

pos6 <= pos6;// keep previous position

else if(PC_en[5]==1'b1)

pos6 <= 2'b10; // store computer data

else if (PL_en[5]==1'b1)

pos6 <= 2'b01;// store player data

else

pos6 <= pos6;// keep previous position

end

// Position 7
always @(posedge clock or posedge reset)

begin

if(reset)

pos7 <= 2'b00;

else begin

if(illegal_move==1'b1)

pos7 <= pos7;// keep previous position

else if(PC_en[6]==1'b1)

pos7 <= 2'b10; // store computer data

else if (PL_en[6]==1'b1)

pos7 <= 2'b01;// store player data

else

pos7 <= pos7;// keep previous position

end

// Position 8

always @(posedge clock or posedge reset)

begin

if(reset)

pos8 <= 2'b00;

else begin

if(illegal_move==1'b1)

pos8 <= pos8;// keep previous position

else if(PC_en[7]==1'b1)

pos8 <= 2'b10; // store computer data

else if (PL_en[7]==1'b1)

pos8 <= 2'b01;// store player data

else

pos8 <= pos8;// keep previous position

end

// Position 9

always @(posedge clock or posedge reset)

begin

if(reset)

pos9 <= 2'b00;

else begin

if(illegal_move==1'b1)

pos9 <= pos9;// keep previous position

else if(PC_en[8]==1'b1)

pos9 <= 2'b10; // store computer data

else if (PL_en[8]==1'b1)

pos9 <= 2'b01;// store player data

else

pos9 <= pos9;// keep previous position

end

endmodule

// FSM controller to control how player and computer play the TIC TAC TOE GAME

// The FSM is implemented based on the designed state diagram

module fsm_controller(

input clock,// clock of the circuit

input reset,// reset

play, // player plays

pc,// computer plays

illegal_move,// illegal move detected

no_space, // no_space detected

win, // winner detected

output reg computer_play, // enable computer to play

player_play // enable player to play

);

// FSM States ( 4 fsm states means 4 parameter blocks will be there each will have

//its own begin-end blocks

parameter IDLE=2'b00;

parameter PLAYER=2'b01;

parameter COMPUTER=2'b10;

parameter GAME_DONE=2'b11;

reg[1:0] current_state, next_state;

// current state registers

always @(posedge clock or posedge reset)

begin

if(reset)

current_state <= IDLE;

else

current_state <= next_state;

end

// next state

// well it will depend on the current state so we now from cases on

//the current state to justify next state, because cases will be on the current state to

//justify what the next state will be..

always @(*)

begin

case(current_state)

IDLE: begin // first begin end block will be of the first parameter i.e. IDLE

if(reset==1'b0 && play == 1'b1)

next_state <= PLAYER; // player to play and next state will be "PLAYER "

else
next_state <= IDLE; // else player not to play and next state will be "IDLE"

player_play <= 1'b0; // and the output of FSM will be 0 and 0

computer_play <= 1'b0; //there by disabling the blocks pd1 and pd2

end

PLAYER:begin

player_play <= 1'b1; //enable pd2

computer_play <= 1'b0; // disable pd1

if(illegal_move==1'b0)

next_state <= COMPUTER; // computer to play and the next state will be " COMPUTER"

else

next_state <= IDLE; //if there is an illegal move by player then next state will be "IDLE"

end

COMPUTER:begin

player_play <= 1'b0; //disable pd2 but there will more than one condition on weather we can or

//cannot enable pd1 ie 3 conditions 1 for-disable & 2 for- enable

if(pc==1'b0)

begin

next_state <= COMPUTER;

computer_play <= 1'b0;

end

else if

(win==1'b0 && no_space == 1'b0) //if,(untill now),nobody has won AND && there is still space

begin

next_state <= IDLE; //it will not go straight to PLAYER coz someone can push reset

computer_play <= 1'b1;// computer to play when PC=1

end
else if(no_space == 1 || win ==1'b1) //two cases OR'ED 1. nospace left or 2. someone may have won

begin

next_state <= GAME_DONE; // game done

computer_play <= 1'b1;// computer to play when PC=1

end

GAME_DONE:begin // game done

player_play <= 1'b0;

computer_play <= 1'b0;

if(reset==1'b1)

next_state <= IDLE;// reset the game to IDLE when reset is one

else

next_state <= GAME_DONE; // reset the game to GAME DONE or GAME_OVER when reset is zero

end

default: next_state <= IDLE; //default is the IDLE state

endcase

end

endmodule // end of the FSM module

// NO SPACE detector

// to detect if no more spaces to play

//here all the inputs are the output from the position register unit

//Its a simple OR-AND type of combinational network

module nospace_detector(

input [1:0] pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,

output wire no_space

);

wire temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp9;

// detect no more space

assign temp1 = pos1[1] | pos1[0];//simple OR logic to detect either of the two bits are one 10 or 01

assign temp2 = pos2[1] | pos2[0];

assign temp3 = pos3[1] | pos3[0];

assign temp4 = pos4[1] | pos4[0];

assign temp5 = pos5[1] | pos5[0];

assign temp6 = pos6[1] | pos6[0];

assign temp7 = pos7[1] | pos7[0];

assign temp8 = pos8[1] | pos8[0];

assign temp9 = pos9[1] | pos9[0];

// output

assign no_space =((((((((temp1 & temp2) & temp3) & temp4) & temp5) & temp6) & temp7) & temp8) &
temp9);

endmodule

// Illegal move detector

// to detect if a player plays on an already occupied position

module illegal_move_detector(

input [1:0] pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,

input [8:0] PC_en, PL_en,

output wire illegal_move

);

wire temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp9;

wire temp11,temp12,temp13,temp14,temp15,temp16,temp17,temp18,temp19;

wire temp21,temp22;

// illegal moving in case of player : scenario 1

assign temp1 = (pos1[1] | pos1[0]) & PL_en[0]; //0th bit of pl_en will be high for pos1 only

// (if player is attempting pos1) AND ( OR function is 1)

assign temp2 = (pos2[1] | pos2[0]) & PL_en[1]; //1st bit of pl_en will be high for pos2 only

assign temp3 = (pos3[1] | pos3[0]) & PL_en[2]; //2nd bit of pl_en will be high for pos3 only
assign temp4 = (pos4[1] | pos4[0]) & PL_en[3]; //3rd bit of pl_en will be high for pos4 only

assign temp5 = (pos5[1] | pos5[0]) & PL_en[4]; //4th bit of pl_en will be high for pos5 only

assign temp6 = (pos6[1] | pos6[0]) & PL_en[5]; //5th bit of pl_en will be high for pos6 only

assign temp7 = (pos7[1] | pos7[0]) & PL_en[6]; //6th bit of pl_en will be high for pos7 only

assign temp8 = (pos8[1] | pos8[0]) & PL_en[7]; //7th bit of pl_en will be high for pos8 only

assign temp9 = (pos9[1] | pos9[0]) & PL_en[8]; //8th bit of pl_en will be high for pos9 only

// illegal moving in case of computer :scenario 2

assign temp11 = (pos1[1] | pos1[0]) & PC_en[0];//0th bit of pc_en will be high for pos1 only

// (if COMPUTR is attempting pos1) AND ( OR function is 1)

//or funtion 1 means position is already occupied

assign temp12 = (pos2[1] | pos2[0]) & PC_en[1];

assign temp13 = (pos3[1] | pos3[0]) & PC_en[2];

assign temp14 = (pos4[1] | pos4[0]) & PC_en[3];

assign temp15 = (pos5[1] | pos5[0]) & PC_en[4];

assign temp16 = (pos6[1] | pos6[0]) & PC_en[5];

assign temp17 = (pos7[1] | pos7[0]) & PC_en[6];

assign temp18 = (pos8[1] | pos8[0]) & PC_en[7];

assign temp19 = (pos9[1] | pos9[0]) & PC_en[8];

// intermediate signals

// temp 21 = OR OF ALL CASES OF SCENARIO 1

//temp 22 = OR OF ALL CASES OF SCENARIO 2

// output illegal move WILL BE OR OF WHOLE CASES OF illegal moves by both PLAYER as well as COMPUTER

assign illegal_move = temp21 | temp22 ;

endmodule
// To decode the position being played, a 4-to-16 decoder with high active output is needed.

// When a button is pressed, a player will play and the position at IN [3:0] will be decoded

// to enable writing to the corresponding registers

//the positional decoder is the rom followed by a mux switch

module position_decoder(input[3:0] in, input enable, output wire [15:0] out_en);

reg[15:0] temp1;

assign out_en = (enable==1'b1)?temp1:16'd0;// if enable is one bit binary 1 ; the assign 16 bit

//out_en with 16 bit temp1 else if enable is

//one bit binary 0 then assign 16 bit out_en with 16

// bit binary 0

always @(*)

begin

case(in)

4'd0: temp1 <= 16'b0000000000000001;

4'd1: temp1 <= 16'b0000000000000010;

4'd2: temp1 <= 16'b0000000000000100;

4'd3: temp1 <= 16'b0000000000001000;

4'd4: temp1 <= 16'b0000000000010000;

4'd5: temp1 <= 16'b0000000000100000;

4'd6: temp1 <= 16'b0000000001000000;

4'd7: temp1 <= 16'b0000000010000000;

4'd8: temp1 <= 16'b0000000100000000;

4'd9: temp1 <= 16'b0000001000000000;

4'd10: temp1 <= 16'b0000010000000000;

4'd11: temp1 <= 16'b0000100000000000;

4'd12: temp1 <= 16'b0001000000000000;

4'd13: temp1 <= 16'b0010000000000000;

4'd14: temp1 <= 16'b0100000000000000;

4'd15: temp1 <= 16'b1000000000000000;

default: temp1 <= 16'b0000000000000001;

endcase

end

endmodule

// winner detector circuit

// to detect who the winner is

// We will win when we have 3 similar (x) or (O) in the following pairs:

// (1,2,3); (4,5,6);(7,8,9); (1,4,7); (2,5,8);(3,6,9); (1,5,9);(3,5,7);

module winner_detector(input [1:0] pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9, output wire winner,

output wire [1:0]who);

wire win1,win2,win3,win4,win5,win6,win7,win8;

wire [1:0] who1,who2,who3,who4,who5,who6,who7,who8;

winner_detect_3 u1(pos1,pos2,pos3,win1,who1);// (1,2,3);

winner_detect_3 u2(pos4,pos5,pos6,win2,who2);// (4,5,6);

winner_detect_3 u3(pos7,pos8,pos9,win3,who3);// (7,8,9);

winner_detect_3 u4(pos1,pos4,pos7,win4,who4);// (1,4,7);

winner_detect_3 u5(pos2,pos5,pos8,win5,who5);// (2,5,8);

winner_detect_3 u6(pos3,pos6,pos9,win6,who6);// (3,6,9);

winner_detect_3 u7(pos1,pos5,pos9,win7,who7);// (1,5,9);

winner_detect_3 u8(pos3,pos5,pos6,win8,who8);// (3,5,7);

assign winner = (((((((win1 | win2) | win3) | win4) | win5) | win6) | win7) | win8);

assign who = (((((((who1 | who2) | who3) | who4) | who5) | who6) | who7) | who8);

endmodule

// Player: 01

// Computer: 10

module winner_detect_3(input [1:0] pos0,pos1,pos2, output wire winner, output wire [1:0]who);

wire [1:0] temp0,temp1,temp2;

wire temp3;

assign temp0[1] = !(pos0[1]^pos1[1]);

assign temp0[0] = !(pos0[0]^pos1[0]);

assign temp1[1] = !(pos2[1]^pos1[1]);

assign temp1[0] = !(pos2[0]^pos1[0]);

assign temp2[1] = temp0[1] & temp1[1];

assign temp2[0] = temp0[0] & temp1[0];

assign temp3 = pos0[1] | pos0[0];

// winner if 3 positions are similar and should be 01 or 10

assign winner = temp3 & temp2[1] & temp2[0];

// determine who the winner is

assign who[1] = winner & pos0[1];

assign who[0] = winner & pos0[0];

endmodule

//Verilog testbench code for the Tic Tac Toe game:

`timescale 1ns / 1ps

// Verilog testbench code for TIC TAC TOE GAME

module tb_tic_tac_toe;

// Inputs

reg clock;

reg reset;

reg play;

reg pc;

reg [3:0] computer_position;

reg [3:0] player_position;

// Outputs
wire [1:0] pos_led1;

wire [1:0] pos_led2;

wire [1:0] pos_led3;

wire [1:0] pos_led4;

wire [1:0] pos_led5;

wire [1:0] pos_led6;

wire [1:0] pos_led7;

wire [1:0] pos_led8;

wire [1:0] pos_led9;

wire [1:0] who;

// Instantiate the Unit Under Test (UUT)

tic_tac_toe_game uut (

.clock(clock),

.reset(reset),

.play(play),

.pc(pc),

.computer_position(computer_position),

.player_position(player_position),

.pos1(pos_led1),

.pos2(pos_led2),

.pos3(pos_led3),

.pos4(pos_led4),

.pos5(pos_led5),

.pos6(pos_led6),

.pos7(pos_led7),

.pos8(pos_led8),

.pos9(pos_led9),

.who(who)
);

// clock

initial begin

clock = 0;

forever #5 clock = ~clock;

end

initial begin

// Initialize Inputs

play = 0;

reset = 1;

computer_position = 0;

player_position = 0;

pc = 0;

#100;

reset = 0;

#100;

play = 1;

pc = 0;

computer_position = 4;

player_position = 0;

#50;

pc = 1;

play = 0;

#100;

reset = 0;

play = 1;

pc = 0;

computer_position = 8;

player_position = 1;
#50;

pc = 1;

play = 0;

#100;

reset = 0;

play = 1;

pc = 0;

computer_position = 6;

player_position = 2;

#50;

pc = 1;

play = 0;

#50

pc = 0;

play = 0;

end

endmodule

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