Fully-pipelined CORDIC-based FPGA Realization for a 3-DOF

Hexapod-Leg Inverse Kinematics Calculation

Guillermo Evangelista, Member, IEEE, Carlos Olaya, Member, IEEE, Erick Rodríguez, Member, IEEE

performance added are not effective solutions, so it is necessary



Abstract—This paper presents a CORDIC-based FPGA

realization for a 3-DOF hexapod-leg inverse kinematics to find an efficient method to accelerate calculation.
calculation. This architecture design proposal is approached first
by an inverse kinematics equations analysis and how are these TABLE I. HARDWARE SPECIFICATIONS OF HEXAPOD ROBOTS
adapted to design an architecture scheme based on CORDIC
Robot LAURON V CRIXUS - -
operations. After that, a 3-DOF hexapod-leg working area is
analyzed to get the CORDIC convergence requirements. Year 2014 2014 2015 2015
Subsequently, we designed an iterative 32-bit floating point Author A. Roennau G. Evangelista M. Zak A. Cully
CORDIC entity that met the convergence and accuracy LPC1768 Raspberry Intel Xeon
requirements. Moreover, a fully pipelined VLSI architecture is Processor Intel Core i7
(Cortex-M3) Pi E5-260
designed, respective hardware and clock signaling considerations Speed 3 GHz 96 MHz 1.2 GHz 2 GHz
are described in order to achieve high frequency and throughput.
Finally, both results proposed and obtained through the Cores 4 1 4 8
kinematic calculations software, which included the angles MCU 9 1 1 -
equations used to calculate precision, hardware requirements
Power (W) 100-150 60 - -
and processing speed.
MCU means Motor Control Unit.

Keywords— CORDIC, FPGA, kinematics calculation, hexapod-

leg. Table 1 shows an hexapod resources comparison, as main
characteristic, the central processor which is responsible for
I. INTRODUCTION solving the routines required by the robot: control, sensors
Legged robots have many characteristics suitable for readings, trajectories generation and communication with slave
terrestrial and space applications, including omnidirectional units, among others.
motion, variable geometry, discrete contact points, access to The one property shared among all processors is
even or uneven surfaces and unique means of locomotion [1]. sequentiality. The difference lies by increasing the processor
Hexapod robots are kind of legged walking robots that are speed, number of cores and associated actuator controllers
programmable and some cases provided with autonomy. The depending on the complexity of the control. Increasing the
six legs move within workspaces in order to achieve processing speed of sequential processors requires a big effort
translational and rotational displacements. in development since the performance is physically limited by
Hexapod walking robots also have a lower impact on the their architecture. As a solution, this paper adds a parallel
terrain and greater mobility in natural surroundings. This is processing units to increase the speed of complex calculations.
particularly important in dangerous environments such as mine In robotics, parallel processing at the kinematic level has two
fields, or where it is essential to keep the terrain mostly advantages. First, the hardware architecture of the controller
undisturbed for scientific reasons [2]. Hexapod robots have a reflects the robot hardware architecture, making the system
clear advantage over wheeled vehicles, given their versatility easier to develop and debug. Second, these schemes are
to move in irregular surfaces or climb obstacles of complex statically extensible and algorithmically scalable, e.g. another
geometry. robotic joint can be added to a parallel control unit [4].
Some of their current disadvantages include high Efficient and low-cost applications are being developed in
complexity and cost, low energy efficiency, and relatively low parallel architectures using CORDIC algorithms, which
speed [3]. In fact, hexapods are complex machines consisting generate trigonometric, logarithmic and transcendental
of mechanisms, actuators, sensors and support hardware. Their functions, including forward and inverse calculations for robot
slowness refers to how quickly kinematic and locomotion are manipulators [5]. For this reason, this paper is limited to the
calculated, partly because the kinematic equations of an study and design of an embedded architecture to calculate the
hexapod leg involve a large number of trigonometric functions inverse kinematics of an hexapod-leg 3-DOF based on
performed in real time; whereas in a conventional approach CORDIC algorithm.
these are implemented in a processor using Taylor series, look
up tables or other. Either of these or sequential controllers

The authors are with the Professional School of Electronic Engineering,

Antenor Orrego Private University, Trujillo 13008 PERU (phone: 51-
913030332; e-mail: gevangelistaa@[Link], colayar@[Link],
erodriguezd@[Link]).
 II. LEG STRUCTURE III. ARCHITECTURE MODELING
A. Inverse Kinematics A. Fully-Pipelined Architecture Model
Based on Denavit-Hartenberg, the first step was to assign Based on the inverse kinematics model, a CORDIC-based
the reference systems. Figure 1, shows the three rotation angles fully pipelined architecture [9] [10] is proposed in Figure 3.
of the hexapod-leg (1,2,3). This proposal is composed of 9 CORDIC modules, a finite state
machine (FSM), 2 multipliers and 3 adders. This six-stage
proposal is fixed in order to achieve high performance and
throughput.

STAGE 1 STAGE 2 STAGE 3

X Finite D w1
C1:CV State
Machine
l
Y 0 r 1
C2:HV w2
0
l1 iK

X w3
z z z C4:HV 0
0
w4
Figure 1. Hexapod-leg joints and systems.
𝜃1 𝜃1 w5
Equations (1), (2) and (3) provide the joints values
STAGE 4 STAGE 6
according to the end-effector Cartesian position [6] and the STAGE 5
l
length of links: l1 = 0.0275m, l2 = 0.0963m, l3 = 0.1051m [7]. w3
w4 C7:LV C8:HV C9:CV
Eq. (4), (5), (6), (7), (8), (9), (10) and (11) are variables for a 0 0 0
development by segments of the architecture.
F
(1)
𝜃2
𝜃1 = atan (𝑦𝑒 /𝑥𝑒 ) +
(2)
D
𝜃2 = 𝑎𝑡𝑎𝑛 (𝐺 ⁄√1 − 𝐺 2 ) − atan(sin 𝜃3 ⁄(𝐹 + D)) w1 iK
𝜃3 = 𝑎𝑡𝑎𝑛 (√1 − 𝐷2 ⁄𝐷) (3) w2 X C3:CV 0 C5:CR C6:CV
0 0 𝜃3 0
𝑟 = √𝑥𝑒 2 + 𝑦𝑒 2 (4) iKh
𝐴 = 2𝑙1 𝑟 (5) 𝜃3 𝜃3

𝐵 = √(𝑟 − 𝑙1 )2 + 𝑧𝑒 2 (6) w5 𝜃1 𝜃1 𝜃1

𝐶 = 𝑟 2 + 𝑧𝑒 2 + 𝑙1 2 − 𝑙2 2 − 𝑙3 2 − 𝐴 (7)
Figure 3. Fully-pipelined CORDIC-based architecture.
𝐷 = 𝐶 𝐶𝑎 = cos 𝜃3 (8)
𝐺 = 𝑧𝑒 ⁄𝐵 (9) Four types of CORDIC operators were considered: circular
𝐶𝑎 = 1⁄2𝑙2 𝑙3 (10) rotational [11], circular vectorial, hyperbolic vectorial [12] and
𝐹 = 𝑙2 ⁄𝑙3 (11) linear vectorial [13], whose functions and symbology are
represented in Table 2. In addition, circular rotational and
B. End-effector Trajectory circular vectorial can be implemented in the same CORDIC
module by changing the operation mode.
The surface of working area for an end-effector with a crab
angle 𝛼 ∈ [0,90]° for a quadruped walk [8] is showed at Figure TABLE II. CORDIC OPERATION REFERENCE
2. This is necessary because it defines the convergence range
of the CORDIC. Circular Rotational

𝑥 𝐾(𝑥 cos 𝑧 − 𝑦 sin 𝑧)

𝑦 CR 𝐾(𝑦 cos 𝑧 + 𝑥 sin 𝑧)
𝑧 CC 100
0

Circular Vectorial

𝑥 𝐾√𝑥 2 + 𝑦 2
𝑦 CV 0
𝑧 CC 𝑧 + tan −1(𝑦⁄𝑥 )
100
Hyperbolic Vectorial

𝑥 𝐾′√𝑥 2 − 𝑦 2
𝑦 HV 0
𝑧 CC 𝑧 + tanh−1(𝑦⁄𝑥 )
100
Lineal Vectorial
𝑥 𝑥
𝑦 LV 0
Figure 2. Working area for hexapod-leg end-effector. 𝑧 CC 𝑧 + 𝑦⁄𝑥
100
B. Finite State Machine Architecture Figure 6 shows that Hyperbolic C8 and Linear C7 are far
In order to calculate the value of 𝑟 and 𝐷 which are not enough of the limit of their range of convergence in order not
CORDIC-dependent in (4) and (8), a FSM was designed at to be expanded. Hyperbolic C2, on the other hand, is slightly
stage two by using 2 multipliers and one adder as shown in closer to limit of its range of convergence, Hyperbolic basic
Figure 4. This FSM obtains these values in three clock cycles range of convergence is expanded in an interesting adaption
and sets outputs to the pipeline register. approach unlike Linear module which could be replaced by
another division method.
Stage 2 Reg 1

𝐶𝑎
MUX

Stage 1 Reg 0
𝑥 Stage 2 Reg 0
𝑥
MUX

+
Stage 1 Reg 1
MUX

𝑙12 + 𝑙22 + 𝑙32

Figure 4. Finite state machine architecture.

IV. CORDIC DESIGN

A. Convergence Range Analysis
The end-effector can occupy any point within a working
area on Figure 2, hence it is mandatory to determine minimum
convergence requirements. Since CORDIC algorithms have a
well-defined convergence range (Table 3) [14] [15], each
architecture operator in Figure 3 is analyzed based on input
parameters in order to comply with this convergence for each
gait step.
TABLE III. CONVERGENCE RANGE OF CORDIC
Figure 6. Linear and Hyperbolic Range of Convergence Analysis.
Method Rotational Vectorial
Circular |atan2(𝑦𝑖𝑛 ⁄𝑥𝑖𝑛 )| ≤ 1.7433
|𝑧𝑖𝑛 | B. Hyperbolic Convergence Range Expansion
≤ 1.7433 (99.9°)
In order to comply with the minimum working area
Linear |𝑦𝑖𝑛 ⁄𝑥𝑖𝑛 | ≤ 1 |𝑧𝑖𝑛 | ≤ 1
requirement of Figure 2, the basic convergence range of the
Hyperbolic −1
|tanh (𝑦𝑖𝑛 ⁄𝑥𝑖𝑛 )| ≤ 𝜃𝑚𝑎𝑥 ≈ 1.1182 |𝑧𝑖𝑛 | ≤ 1.1182 hyperbolic cordic algorithm was expanded.

In Figure 5, Circular C3 gaits calculations exceeds the basic For 𝑖 ≤ 0:

range of convergence obtained from Table 3, consequently an 𝑥𝑖+1 1 −𝛿𝑖 (1 − 2𝑖−2 ) 𝑥𝑖
expansion is needed. This is achieved by adding two negative [𝑦 ] = [ 𝑖−2
] [𝑦 ] (12)
𝑖+1 𝛿𝑖 (1 − 2 ) 1 𝑖
index terms in the calculation, it is enough to enlarge 𝜃𝑚𝑎𝑥 and 𝑧𝑖+1 = 𝑧𝑖 + 𝛿𝑖 atan−1(1 − 2𝑖−2 )
satisfy the convergence requirements.
For 𝑖 > 0:
𝑥 1 −𝛿𝑖 2−𝑖 𝑥𝑖
[𝑦𝑖+1 ] = [ −𝑖 ] [𝑦 ] (13)
𝑖+1 𝛿𝑖 2 1 𝑖
𝑧𝑖+1 = 𝑧𝑖 + 𝛿𝑖 atan−1(1 − 2−𝑖 )

As only the vectoring mode is used, there is not 𝑧𝑖+1

calculation involved. Moreover, non-positive indexes are
avoided by making 0 ≤ 𝑖 < 𝑀 + 𝑁, where M is the non-
positive iteration and N the positive iteration amount. As a
result, (12) and (13) can be rewritten as follows:

For 𝑖 ≤ 𝑀:
𝑥𝑖+1 1 −𝛿𝑖 (1 − 2𝑖−𝑀−2 ) 𝑥𝑖
[𝑦 ] = [ ] [𝑦 ] (14)
𝑖+1 −𝛿𝑖 (1 − 2𝑖−𝑀−2 ) 1 𝑖

For 𝑖 > 𝑀:
𝑥𝑖+1 1 −𝛿𝑖 2𝑀−𝑖 𝑥𝑖
[𝑦 ] = [ ] [𝑦 ] (15)
Figure 5. Circular C3 CV Range of Convergence Analysis. 𝑖+1 −𝛿 2𝑀−𝑖
𝑖 1 𝑖
 The implementation of bit-parallel iterative architecture is convergence 𝑎𝑡𝑎𝑛 parameters starting from the third
shown in Figure 7. position in memory. Since pipeline architecture makes
CORDIC modules start with the pipeline clock, all
instantiations are synchronized. As a result, all Circular
CORDIC modules shares the same look-up ROM
MUX

MUX
10
memory, thereby reducing hardware cost.
Y
0
sgn(Y) ADDR_A [4: 0] Dout_A [31: 0]
>>(i-M) 100 100 [4: 0]
ADDR_B 100 [31: 0]
Dout_B

MUX
IP CORE
100 100 ROM 100
>>(2+M-i) 𝑎𝑡𝑎𝑛
10 0 XOR
ENA
>>(i-M)
10
MUX
100

sgn(Y)
100 i<=M
100

100
>>(2+M+i)
Figure 10. RTL level for IP CORE ROM 𝑎𝑡𝑎𝑛. Total port read latency
from rising edge of read clock: 1 clock cycle.
100 XOR
sgn(Y)
100 10  Linear cordic: This is shown in Figure 11 (basic
X convergence) and requires 16 iterations/cycles for processing
MUX

MUX

0 time (Figure 12).

10

Xin [31: 0] Xout [31: 0]

Figure 7. Bit-parallel iterative architecture.
100[31: 0]
Yin 100
C. CORDIC Design 100 LINEAR
For CORDIC modules implementation, three IEEE 754
floating point CORDIC bit-parallel architecture modules were Start Data Ready
implemented. Since only the vectoring mode is used for both 100 100
Figure 11. RTL level for Linear CORDIC.
Linear and Hyperbolic CORDIC modules, one ROM memory
is instantiated for Circular CORDIC look-up table:

 Circular cordic: This is shown in Figure 8 (basic

convergence) and requires 16 iterations/cycles for
processing time and 18 cycles for expanded processing Figure 12. Test bench for Linear CORDIC.
time (Figure 9).
 Hyperbolic cordic: This is shown in Figure 13 (expanded
Xin[31: 0] Xout[31: 0] convergence) and requires 18 iterations [−1: 16] and 20 cycles
100
Yin[31: 0] 100 0]
Yout[31: for processing time (Figure 14).
100 0]
Zin[31: 100
Zout[31: 0]
100 0]
ROM Out[31: CIRCULAR 100 Xin [31: 0] Xout [31: 0]
100 100 100
Yin [31: 0] 100
Mode Data ready 100 HYPERBOLIC
100
Start 100 Address[4: 0]
ROM
100 100
Figure 8. RTL level for Circular CORDIC.
Start Data Ready
100 100
Figure 13. RTL level for Hyperbolic CORDIC.

Figure 14. Test bench level for Hyperbolic CORDIC.

Figure 9. Test bench for Circular CORDIC.
V. FULLY-PIPELINED DESIGN IMPLEMENTATION
 Look-up table sharing: For storing Circular CORDIC A. Module Design
𝑎𝑡𝑎𝑛 parameters, a dual port Xilinx ROM Memory IP
The pipeline architecture module instantiation proposed in
Core resource is used (Figure 10). This LUT module
Figure 15 is required at least for the Inverse Kinematics
stores both Circular basic and Circular expanded range of calculation. Therefore, some modules are implemented to
generate a VLSI architecture which is explained further. This approaches were taken. The first one is clock period based on
module outs joints values in Floating Point IEEE 754 format, synthesis tool analysis, which considers minimum time for
this can be feedback to processor unit or be decode in a next input setup signals and maximum path from input to output.
stage in order to get output signals for robot actuators. The timing summary from ISE Design is shown in Figure 16.

B. VLSI Architecture Timing Summary:

---------------
This paper is intended to be part of a SoC architecture, and Speed Grade: -3
some factors need to be taken into some consideration. First,
inverse kinematics input parameters should be provided by an Minimum period: 33.586ns (Maximum Frequency: 29.774MHz)
asynchronous Trajectory Generator module. This may or may Minimum input arrival time before clock: 1.406ns
not be on the same clock domain, causing sync issues due to Maximum output required time after clock: 1.063ns
Maximum combinational path delay: No path found
different data rates. In most cases, using FIFO memories is a Figure 16. Timing Summary from ISE Design.
good approach to solve this issue, even though the FIFO size is
a limiting factor. Thus, three single clock domain FIFOs were On the other hand, since the period of pipeline clock should
implemented, as shown in Figure 15, assuming that Trajectory be large enough to provide sufficient time for slower stage
and Inverse Kinematics modules are under the same clock signals to pass through, Pipeline Architecture frequency is
domain and making FIFOs large enough to store Inverse limited by the slowest stage. As presented in the CORDIC
Kinematics input parameters for all hexapod legs. A FSM is in Design section, Circular C3 and Hyperbolic C2 modules are
charge of control signaling for data writing and reading in the bottleneck in the design, given that these modules have the
FIFOs, as we will explain in detail later on. As a result, the largest processing time of 20 clock cycles.
kinematics parameters are written in the architecture
synchronously. Consequently, pipeline clock signals must be fit in order to
get the minimum period for pipeline stages and handle FIFO
Write Data [31:0] Read Data [31:0] read signaling. Afterwards, the pipeline period is calculated
Wire 1
1
based on the pipeline bottleneck period, the pipeline recording
Read Enbl FIFO Full period and FIFO reading period. As a result, 21 clock cycles
Wire 2
X period is used as pipeline clock.
Write Enbl Empty

Write Data [31:0] Read Data [31:0]

MUX

iKinematics
[31:0] Wire 3

Read Enbl FIFO Full Figure 17. Test bench for timing.
Y Wire 4
Write Enbl Empty Figure 17 shows the clock signaling, described as follows:
 Read_fifo: Sends the clock signal for FIFO modules to
Write Data [31:0] Read Data [31:0] read the next Inverse Parameters input data.
Wire 5
 Stage_clock: Pipeline clock signal.
Read Enbl FIFO Full
Z
Wire 6  Read_clock: Clock signal reads FIFO output and records it
Write Enbl Empty in the first stage of pipeline input.
 Start_clock: Cordic module starts signal clock.
Wire 7

Zin [31:0] VI. RESULTS

Wire 1 𝜃1[31:0]
Yin [31:0] Table 4 shows an error in Inverse Kinematics calculation.
Wire 3 𝜃2[31:0]
Zin [31:0] The main percentage error presented in 𝜃2 is greater than 5%,
Wire 5 𝜃3[31:0]
iKinematics this is because 𝜃2 takes values close to zero at determined gait
Start Pipeline Data Ready
iterations, even though this error is high, the deviation is close
Read FIFO
to zero.

Start
TABLE IV. IK ANGLES ERROR CALCULATION
AND

Wire 2
Wire 4 ROM Type 𝜽𝟏 𝜽𝟐 𝜽𝟑
Wire 6
ROM
LUT Percent Error (%) 0.004888 5.272004 0.001002
ROM
Data [31:0] Address [4:0] Deviation (Rads) 2.6451x10−7 3.9705x10−7 2.6451𝑥10−7
Wire 7
Figure 15. VLSI Architecture for Trajectories and IK.
A good approach to measure effective error in robot motion
is by using direct kinematics. Table 5 shows a Direct
C. Timing Analysis Kinematics parameters mean percentage error based on each
Another factor took into consideration was the clock hexapod robot gait. The architecture calculation gets great
generation. Regarding the architecture proposed, two timing accuracy on both Tripod and Pentapod gaits. On the other hand,
it gets slightly more errors in Quadruped gaits with a maximum APPENDIX
of 2.43%, which this represents a deviation of around 7 mm.
Algorithms and simulations:
TABLE V. EQUATIONS FOR OPERATOR ’S EXPANSION [Link]
nFU24oTn9zw3128cL
𝑷𝒆𝒓𝒄𝒆𝒏𝒕 𝑬𝒓𝒓𝒐𝒓 (%)
Gait
𝒙 𝒚 𝒛
Tripod 8.06451x10−4 4.62962x10−4 14.7633x10−4 ACKNOWLEDGMENT
Quadruped* 0.583768 0.583333 0.80507 This research work was supported by the Professional
−3 −3
School of Electronic Engineering of the Faculty of
Pentapod 2.98408x10 2.20439x10 3.41625x10−3
Engineering, Antenor Orrego Private University. The work
*The results for Quadruped 4+2 are the same. was performed at CIIE and was supported by rectoral
resolution N°009-2014-VIN-UPAO.
Figure 18 shows gaits accuracy, mentioned that Quadruped
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