Birla Institute of Technology and Science, Pilani
EEE F244 / INSTR F244 Microelectronic Circuits
Mid semester Test, II Semester 2017-2018
CLOSED BOOK
Time: 90 min. Max. Marks=75 Date: 7-3-2018 (2-3.30 pm)
Unless given specifically
Take -- VDD = 3.3V,
For NMOS device μnCox = 140 μA/V2, VT = 0.7 V , λ= 0.1 V-1 , γ= 0.45 √V , Cox= 0.38pF/um2
For PMOS device μpCox = 40 μA/V2, VT = - 0.8 V , λ= 0.1 V-1 , γ= 0.4 √V , Cox =0.38 pF/um2
NOTE:
If not specified in question,------
• Ignore γ, λ in drain current equation. Assume matched components wherever required
• Bulk of nmos connected to ground and bulk of pmos connected to Vdd. Specify your assumptions. Justify your answers.
• Unless specified, assume all MOSFET are biased in saturation region
• Label your sketches properly. All symbols have usual meaning
Q1 For the circuit shown in the Fig. Q1, V1, V2, Kn = uncox W/L, VT are the input
parameters which can change independently . I1, I2, gm, ro are the output parameters.
Table 1 shows the variation (using symbols ↑ = increase, ↓ = decrease, -- = no change.) in each
output parameter with increase in each of the input parameters. Assume that the transistor is in
saturation.
Identify the cells (using numbers) with wrong entries and justify it with proper reason. [Note:
marks will be awarded only if the proper reasoning is given].
(10 M)
output
Parameter I1 I2 gm ro
input
Parameter
V1 ↑ 1 ↑ ↑ ↑
2 3 4
V2 -- 5 ↑ ↓ ↓ Table 1
6 7 8
Kn -- 9 ↑ ↓ ↓
10 11 12
Fig. Q1
VT -- 13 ↓ ↓ ↑
14 15 16
Q2 For the circuit shown in Fig.Q2, I1=I2= 200 µA, (W/L)p= 250,
(W/L)n=71.5. Include channel length modulation and body bias
effect in small signal model and calculation, take χ=0.2. The
capacitor C behaves as short circuit for the signal frequencies of
interests.
(Given: Assume I1 and I2 as basic current mirror which have
Fig. Q2
overdrive voltage of 0.1 V, and λ=0. )
i. Identify the type of amplifier stages. Draw complete small
signal model. Calculate and show all value of small signal model parameters.
ii. Calculate the low frequency small signal voltage gain approximately. Calculate the output signal
swing at Vout.
(16 M)
Q3 (i) For the current mirror as shown in Fig.Q3, assume all the transistors
are perfectly matched and biased in saturation region. Given (W/L)1 =
(W/L)3 = 10/1, (W/L)2 = (W/L)4 = 50/1 and R = 15 kΩ , ignore substrate bias
effect.
i. What is the minimum output voltage {VMIN(out)} needed at the drain
of transistor M4 to have a perfect current mirroring action.
ii. Compute value of output resistance (Rout), if λ= 0.1 V-1.
iii. Compute value of input resistance (Rin), if ro1 and ro3 is assumed to be
infinite. Fig.Q3
(16 M)
Q4 For the circuit shown in Fig.Q4. , a small signal current
source is having an internal resistance RS=20kΩ has to
deliver an output voltage to a large load resistance Rload
=100kΩ. An amplifier stage is introduced between the
source and load to increase vout.
Fig. Q4
i. Can we use a voltage amplifier for this purpose? Justify?
ii. If the amplifier is modeled as a trans-resistance amplifier derive an expression for iout/iin in terms
of RLoad and other amplifier parameters.
iii. If the voltage gain (vout/vin) is 40 dB, (iout/is) is 0.95 and (iout/iin)=1, sketch and label (numerical
values with proper units) the equivalent model of trans-resistance amplifier. Assume input and
output resistance of trans-resistance amplifier are equal
(17 M)
Q5 For the circuit in Fig. Q5, the dimensions of all the transistors are equal to W/L=20µm/2µm.
Assume, Rs=80K,
Vbias
i. Calculate the low frequency voltage gain of this amplifier.
Express it in dB.
ii. Draw the complete labeled high frequency small signal model of
this circuit. Determine the number of poles in the circuit.
iii. Estimate -3dB frequency of the amplifier. Take CL=0.3pF,
Cgs1=0.2pF, Iref= 100µA. Ignore other capacitances like Cgd1,
Cgd2, Cdb1, Cdb2.
Fig. Q5
[16 M]
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