PD - 95483C

IRF1010EZPbF
IRF1010EZSPbF
Features
IRF1010EZLPbF
l Advanced Process Technology HEXFET® Power MOSFET
l Ultra Low On-Resistance
l Dynamic dv/dt Rating D
l 175°C Operating Temperature VDSS = 60V
l Fast Switching
l Repetitive Avalanche Allowed up to Tjmax RDS(on) = 8.5mΩ
l Lead-Free G

Description ID = 75A
S
This HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche [Link] features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of TO-220AB D2Pak TO-262
applications. IRF1010EZPbF IRF1010EZSPbF IRF1010EZLPbF

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 84 A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig. 9) 60
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 75
IDM Pulsed Drain Current c 340
PD @TC = 25°C Maximum Power Dissipation 140 W
Linear Derating Factor 0.90 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy (Thermally Limited) d 99 mJ
EAS (tested) Single Pulse Avalanche Energy Tested Value i 180
IAR Avalanche Current c See Fig.12a,12b,15,16 A
EAR Repetitive Avalanche Energy h mJ
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.11 °C/W
RθCS Case-to-Sink, Flat, Greased Surface 0.50 –––
RθJA Junction-to-Ambient ––– 62
RθJA Junction-to-Ambient (PCB Mount, steady state) j ––– 40

HEXFET® is a registered trademark of International Rectifier.

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Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.058 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 6.8 8.5 mΩ VGS = 10V, ID = 51A f
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 100µA
gfs Forward Transconductance 200 ––– ––– S VDS = 25V, ID = 51A
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 60V, VGS = 0V
––– ––– 250 VDS = 60V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 58 86 nC ID = 51A
Qgs Gate-to-Source Charge ––– 19 28 VDS = 48V
Qgd Gate-to-Drain ("Miller") Charge ––– 21 32 VGS = 10V f
td(on) Turn-On Delay Time ––– 19 ––– ns VDD = 30V
tr Rise Time ––– 90 ––– ID = 51A
td(off) Turn-Off Delay Time ––– 38 ––– RG = 7.95Ω
tf Fall Time ––– 54 ––– VGS = 10V f
LD Internal Drain Inductance ––– 4.5 ––– nH Between lead, D

6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package G

and center of die contact S

Ciss Input Capacitance ––– 2810 ––– pF VGS = 0V

Coss Output Capacitance ––– 420 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 200 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 1440 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 320 ––– VGS = 0V, VDS = 48V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 510 ––– VGS = 0V, VDS = 0V to 48V

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 84 MOSFET symbol D

(Body Diode) A showing the

ISM Pulsed Source Current ––– ––– 340 integral reverse G

(Body Diode) c p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 51A, VGS = 0V f
trr Reverse Recovery Time ––– 41 62 ns TJ = 25°C, IF = 51A, VDD = 30V
Qrr Reverse Recovery Charge ––– 54 81 nC di/dt = 100A/µs f
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by … Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature. (See fig. 11). as Coss while VDS is rising from 0 to 80% VDSS .
‚ Limited by TJmax, starting TJ = 25°C, L = 0.077mH, † Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 51A, VGS =10V. Part not avalanche performance.
recommended for use above this value. ‡ This value determined from sample failure population. 100%
ƒ ISD ≤ 51A, di/dt ≤ 260A/µs, VDD ≤ V(BR)DSS, tested to this value in production.
TJ ≤ 175°C. ˆ This is applied to D2Pak, when mounted on 1" square PCB
„ Pulse width ≤ 1.0ms; duty cycle ≤ 2%. ( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.

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10000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
7.0V 7.0V
1000
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

6.0V 6.0V
5.5V
5.0V
100 5.5V
5.0V
BOTTOM 4.5V BOTTOM 4.5V

100

10 4.5V
10

1
1
4.5V 20µs PULSE WIDTH
20µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
0.1 0.1
0.1 1 10 100 0.01 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 100

90
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)

80 T J = 25°C
100 T J = 175°C
70

60

10 50
T J = 175°C
40

T J = 25°C 30
1
20
VDS = 25V
≤60µs PULSE WIDTH 10

0.1 0
4 5 6 7 8 9 10 0 20 40 60 80 100 120 140
ID,Drain-to-Source Current (A)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

vs. Drain Current
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100000 12.0
VGS = 0V, f = 1 MHZ
ID= 51A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd 10.0 VDS= 48V

VGS, Gate-to-Source Voltage (V)

C oss = C ds + C gd VDS= 30V
VDS= 12V
C, Capacitance(pF)

10000 8.0

Ciss 6.0

1000 4.0

Coss
2.0
Crss

100 0.0
1 10 100 0 10 20 30 40 50 60
VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.00 10000

OPERATION IN THIS AREA

ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

1000 LIMITED BY R DS(on)

100.00

100 100µsec
T J = 175°C
10.00
1msec
10

T J = 25°C
1.00
1 10msec
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
0.10 0.1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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100 2.5
ID = 84A

RDS(on) , Drain-to-Source On Resistance

90
Limited By Package VGS = 10V
80
2.0
70
ID, Drain Current (A)

60

(Normalized)
50 1.5

40

30
1.0
20

10

0 0.5
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

T C , Case Temperature (°C) T J , Junction Temperature (°C)

Fig 9. Maximum Drain Current vs. Fig 10. Normalized On-Resistance

Case Temperature vs. Temperature

10
Thermal Response ( Z thJC )

1
D = 0.50

0.20
R1 R2 R3
0.1 0.10 R1 R2 R3 Ri (°C/W) τi (sec)
τJ
0.05 τJ
τC 0.415 0.000246
τ
τ1 τ2 τ3
0.02 τ1 τ2 τ3 0.410 0.000898
0.01
Ci= τi/Ri 0.285 0.009546
0.01 Ci i/Ri

SINGLE PULSE Notes:

( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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15V 400

EAS , Single Pulse Avalanche Energy (mJ)

ID
350 TOP 5.7A
L DRIVER
VDS 9.1A
300
BOTTOM 51A
RG D.U.T + 250
V
- DD
IAS A
VGS
20V 200
tp 0.01Ω

150

Fig 12a. Unclamped Inductive Test Circuit 100

V(BR)DSS
50
tp
0
25 50 75 100 125 150 175

Starting T J , Junction Temperature (°C)

I AS

Fig 12c. Maximum Avalanche Energy

Fig 12b. Unclamped Inductive Waveforms
vs. Drain Current
QG
10 V
QGS QGD
4.5

VG
VGS(th) Gate threshold Voltage (V)

4.0

3.5
Charge
ID = 250µA
3.0
Fig 13a. Basic Gate Charge Waveform
2.5
Current Regulator
Same Type as D.U.T.
2.0
50KΩ

12V .2µF
.3µF
1.5

+
V
D.U.T. - DS 1.0
-75 -50 -25 0 25 50 75 100 125 150 175
VGS
T J , Temperature ( °C )
3mA

IG ID
Current Sampling Resistors

Fig 14. Threshold Voltage vs. Temperature

Fig 13b. Gate Charge Test Circuit
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1000

Duty Cycle = Single Pulse

100 Allowed avalanche Current vs
Avalanche Current (A)

avalanche pulsewidth, tav

0.01
assuming ∆ Tj = 25°C due to
avalanche losses
10 0.05
0.10

0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current [Link]

100 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at [Link])
BOTTOM 1% Duty Cycle 1. Avalanche failures assumption:
ID = 51A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

75 temperature far in excess of T jmax. This is validated for

every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
50 3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
25
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav ) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy
vs. Temperature
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IRF1010EZ/S/LPbF

Driver Gate Drive

P.W.
D.U.T P.W.
Period D=
Period
+

ƒ
*
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG V DD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

RD
V DS

VGS
D.U.T.
RG
+
-VDD

10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

VDS
90%

10%
VGS
td(on) tr t d(off) tf

Fig 18b. Switching Time Waveforms

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TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

EXAMPLE: THIS IS AN IRF1010

LOT CODE 1789 INTERNAT IONAL PART NUMBER
AS SEMBLED ON WW 19, 2000 RECT IFIER
IN T HE AS S EMBLY LINE "C" LOGO
DAT E CODE
Note: "P" in assembly line position YEAR 0 = 2000
AS S EMBLY
indicates "Lead - Free" LOT CODE WEEK 19
LINE C

Notes:
1. For an Automotive Qualified version of this part please see [Link]
2. For the most current drawing please refer to IR website at [Link]
[Link] 9
IRF1010EZ/S/LPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)

D2Pak (TO-263AB) Part Marking Information

THIS IS AN IRF530S WITH PART NUMBER

LOT CODE 8024 INTERNAT IONAL
ASSEMBLED ON WW 02, 2000 RECT IFIER F530S
IN THE ASS EMBLY LINE "L" LOGO
DATE CODE
YEAR 0 = 2000
ASSEMBLY
LOT CODE WEEK 02
LINE L

OR
PART NUMBER
INT ERNAT IONAL
RECT IFIER F530S
LOGO DATE CODE
P = DESIGNATES LEAD - FREE
PRODUCT (OPTIONAL)
ASSEMBLY
YEAR 0 = 2000
LOT CODE
WEEK 02
A = ASS EMB LY SITE CODE

Notes:
1. For an Automotive Qualified version of this part please see [Link]
2. For the most current drawing please refer to IR website at [Link]
10 [Link]
 IRF1010EZ/S/LPbF

TO-262 Package Outline

Dimensions are shown in millimeters (inches)

TO-262 Part Marking Information

EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789 PART NUMBE R
INTERNATIONAL
AS S EMBLE D ON WW 19, 1997
RECTIFIER
IN THE AS S E MBLY LINE "C" LOGO
DATE CODE
YEAR 7 = 1997
AS S EMBLY
LOT CODE WEE K 19
LINE C

OR

PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DES IGNATES LEAD-FREE
AS S EMBLY
LOT CODE PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEE K 19
A = AS S EMBLY S ITE CODE

Notes:
1. For an Automotive Qualified version of this part please see [Link]
2. For the most current drawing please refer to IR website at [Link]
[Link] 11
IRF1010EZ/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)

TRR

1.60 (.063)
1.50 (.059)
1.60 (.063)
4.10 (.161) 1.50 (.059)
3.90 (.153) 0.368 (.0145)
0.342 (.0135)

FEED DIRECTION 1.85 (.073) 11.60 (.457)

1.65 (.065) 11.40 (.449) 24.30 (.957)
15.42 (.609)
23.90 (.941)
15.22 (.601)
TRL
1.75 (.069)
10.90 (.429) 1.25 (.049)
10.70 (.421) 4.72 (.136)
16.10 (.634) 4.52 (.178)
15.90 (.626)

FEED DIRECTION

13.50 (.532) 27.40 (1.079)

12.80 (.504) 23.90 (.941)

330.00 60.00 (2.362)

(14.173) MIN.
MAX.

30.40 (1.197)
NOTES : MAX.
1. COMFORMS TO EIA-418. 26.40 (1.039) 4
2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)
3. DIMENSION MEASURED @ HUB.
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

TO-220AB package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at [Link] for sales contact information. 07/2010
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