Study on Latchup Path between HV-LDMOS and LV-

CMOS in a 0.16-μm 30-V/1.8-V BCD Technology

Chia-Tsen Dai (1,3), Ming-Dou Ker (1), Yeh-Ning Jou (2), Shao-Chang Huang (2),
Geeng-Lih Lin (2), and Jian-Hsing Lee (2)
(1) Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
(2) Vanguard International Semiconductor Corporation, Hsinchu, Taiwan
(3) Amazing Microelectronic Corporation, Hsinchu, Taiwan

Abstract - The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30-
V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this
path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout
rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.

I. Introduction the multi-layer structures of HV devices in [13], such

latchup or latchup-like issue may still possibly happen
When more complicated implementations of CMOS when a process with simplified HV device structures
integrated circuits (ICs), such as mixed-signal, is used.
multiple power supplies, RF, system-on-chip, are In this work, the cross-domain latchup path between
integrated together, those CMOS devices will suffer HV and LV transistors has been investigated in a
considerable noises coming from both internal and 0.16-μm 30-V/1.8-V bipolar-CMOS-DMOS (BCD)
external of CMOS ICs. Robust reliability design is technology. In order to verify the holding voltage of
strongly needed for CMOS ICs used in the harsh latchup path, the dc curve tracer (Tek370B) and 1000-
operating environments. Latchup is one of the ns transmission-line-pulsing (TLP) system are used
important reliability issue in CMOS IC products, [14]. The characteristics of latchup path between the
especially in the high-voltage (HV) applications [1], HV and LV devices are further verified through the
[2]. Because of the high circuit-operating voltage and current-trigger latchup test. A silicon chip with split
structure complexity of HV devices, HV CMOS ICs device conditions and the trigger node was drawn and
would be seriously damaged by the latchup-generated fabricated.
heat if latchup is induced by the external glitches or
inductive load. To eliminate the occurrence of II. Test Structures
latchup, many techniques had been reported,
including process optimization, modified layout Latchup path traditionally exists between the PMOS
structure, or even circuit design of active guard ring (connected to VDD or VCC) and the NMOS (connected
[3]–[8]. to VSS or GND), when these two devices are close
The methods and test procedures to investigate the together to each other in the chip, as illustrated in Fig.
latchup immunity of IC product had been specified in 1. Therefore, some layout rules to prevent latchup
the Joint Electron Device Engineering Council between PMOS and NMOS had been specified and
(JEDEC) standards [9]. The latchup immunity level provided by foundry for a given CMOS process.
for the current-trigger latchup test in the up-to-dated
standard (JESD78E) has been specified to be greater
than 100 mA.
With the integration of both HV and low-voltage (LV)
devices in the same chip, the voltage levels of HV
domain are often significantly greater than the voltage
levels of LV domain. Some unpredictable latchup
failures or ESD protection issues would happen
around the interfaces between different power Figure 1: Traditional latchup path between PMOS and NMOS
domains, as those reported in [10]–[13]. Though transistors in a CMOS technology.
cross-domain latchup issue did not occur because of
 Figure 2: Test structure A with 30-V asymmetric pLDMOS and 1.8-V pMOS in the HV BCD technology, where the possible latchup
path exists from the source of HV pLDMOS (connected to VDDH) to the n-well of LV pMOS (connected to VDDL).

HV pLDMOS (Symmetric Type) LV pMOS

VSS VDDH VOut,H VDDH VDDH VSS VDDL VDDL VOut,L VDDL VSS VTrigger

Poly Poly

P+ N+ P+ P+ N+ P+ N+ N+ P+ P+ N+ N+ P+ P+

N-Well
Possible Latchup Path
HV HV HV HV HV HV HV HV HV
P-Well N-Well P-Well P-Well N-Well P-Well N-Well N-Well P-Well

N-Buried Layer (NBL) N-Buried Layer (NBL)

P-Substrate

Figure 3: Test structure B with 30-V symmetric pLDMOS and 1.8-V pMOS in the HV BCD technology, where the possible latchup
path exists from the source of HV pLDMOS (connected to VDDH) to the n-well of LV pMOS (connected to VDDL).

Figure 4: Simplified layout top view to show the possible latchup Figure 5: Simplified circuit scheme to show the possible latchup
path between HV pLDMOS and LV pMOS. path between HV pLDMOS and LV pMOS.

However, there was no design rule specified for the The cross-domain latchup path may possibly exist
possible latchup path that parasitically exists between from the VDDH-connected source of HV pLDMOS,
the HV PMOS (connected to VDDH or VCC) and the N- through HV n-body, HVNW, HV p-well (HVPW),
Well of LV PMOS (connected to VDDL). The test and p-substrate, to the VDDL-connected n-well (NW)
structures studied in this work are fabricated in a 0.16- pickup of LV pMOS. Test structure B is implemented
μm 30-V/1.8-V BCD technology with two different with 30-V symmetric pLDMOS and 1.8-V pMOS
HV device structures, including the asymmetric and transistors, as drawn in Fig. 3. Compared with the
symmetric 30-V pLDMOS transistors. Fig. 2 shows asymmetric pLDMOS, the source side of symmetric
the test structure A implemented with 30-V one is composed of p-type diffusion (p+) and HVPW.
asymmetric pLDMOS and 1.8-V pMOS transistors. The simplified layout top view of the test structure
According to the foundry-provided layout rules, the with HV pLDMOS and LV pMOS is drawn in Fig. 4,
LV pMOS is surrounded by HV n-well (HVNW) and where the VTrigger node with additional p+ diffusion
N-buried layer (NBL) for the isolation, which can added in p-substrate region will be used in the current-
reduce the substrate noise and separate the p-well trigger latchup test. The distance (S) of the possible
(PW) bias of LV domain from the common p- latchup path is 20 μm in the silicon chip.
substrate.
The simplified circuit scheme to show the possible 35
latchup path in these test structures is illustrated in 30
Fig. 5, where the channels of both devices are kept in

Holding Voltage (V)

25
off state by gate-source short circuit to study the effect
of layout structure on latchup. The HV and LV 20
devices are drawn with channel widths of 400 μm and 15
30 μm, respectively.
10
Test Structure A
III. Experimental Results 5 Test Structure B

0
A. DC I–V Characteristics 100 200 500 1000
To investigate the latchup characteristics of the test TLP Pulse Width (ns)
Figure 7: TLP-measured holding voltages of test structures with
structures, the latchup dc I–V curves are measured by
different pulse widths of 100, 200, 500, and 1000 ns, respectively.
dc curve tracer (Tek370B) at room temperature (25
°C). Unfortunately, all the test structures were directly The measured holding voltages gradually decreased as
burned out before entering their snapback state in this the pulse width increased from 100 to 1000 ns. It
dc measurement. The curve tracer might damage the implies that the holding voltage of these test structures
device under test (DUT) because of the high electric would be much lower under dc measurement, whereas
power generated during the long measurement latchup is a reliability issue with the time duration
duration. longer than milliseconds. With a lower holding
B. 1000-ns TLP I–V Characteristics voltage, the latchup path would be easily triggered on
by the external injected noise pulses.
To avoid electrical overstress (EOS) events and to
successfully detect the fired latchup state of the test C. Current-Trigger Latchup Test
structures, long-pulse TLP system is exploited. As Since latchup state of these test structures can be
reported in [14], TLP system with long pulse width detected from the 1000-ns TLP measurement results,
can help to judge the holding voltage of DUT, which current-trigger latchup test specified in the JEDEC
is sometimes regarded as reference data to latchup standard (JESD78E) is used to further verify their
sensitivity. Accordingly, the latchup I–V curves of the latchup immunity. Fig. 8 shows the measurement
test structures are measured by TLP system with setup of JEDEC latchup test applied to the test
different pulse widths. Fig. 6 shows the 1000-ns TLP- structures, with a HV dc supply at VDDH, a LV dc
measured I–V curves of test structures from VDDH to supply at VDDL, a current pulse generator applied to
VDDL, with VSS grounded. The test structures A and B the VTrigger node, and an oscilloscope to monitor the
both entered their own snapback state with holding waveforms at VDDH, VDDL, and VTrigger nodes. The
voltage of ~15 V. Furthermore, Fig. 7 shows the TLP- trigger current pulse with a pulse width of 10 ms
measured holding voltages of test structures with injected at VTrigger node is to simulate a transient noise
different pulse widths of 100, 200, 500, and 1000 ns, penetrating into the p-substrate around the HV and
respectively. LV devices to induce latchup.

2.0

1000-ns TLP
Test Structure A
TLP_Current (A)

1.5
Test Structure B
P+ in P-sub.

1.0

0.5

0.0
0 10 20 30 40 50 60 70 80 90
TLP_Voltage (V) Figure 8: Latchup measurement with the positive current pulse
Figure 6: I–V characteristics of test structures A and B, measured applied at VTrigger node.
by 1000-ns TLP system.
 VDDH (30V) Before Trigger DUT: Test Structure A VDDH (30V) Before Trigger DUT: Test Structure B

Current (50mA/div.)

Current (50mA/div.)
Voltage (10V/div.)

Voltage (10V/div.)
VDDL (1.8V) Before Trigger VDDH (~5V) After Trigger VDDL (1.8V) Before Trigger VDDH (~2V) After Trigger

VDDL (1.8V) After Trigger VDDL (1.8V) After Trigger

+100mA +100mA
Injected Current Pulse Injected Current Pulse

Time (10ms/div.) Time (10ms/div.)

Figure 9: Measured time-domain voltage and current waveforms Figure 12: Measured time-domain voltage and current waveforms
on the test structure A, with VDDH of 30 V and VDDL of 1.8 V. on the test structure B, with VDDH of 30 V and VDDL of 1.8 V.

VDDH (30V) Before Trigger DUT: Test Structure A VDDH (30V) Before Trigger DUT: Test Structure B

Current (50mA/div.)

Current (50mA/div.)
Voltage (10V/div.)

Voltage (10V/div.)
VDDH (~5V) After Trigger VDDH (~2V) After Trigger
VDDL (0V) Before Trigger VDDL (0V) Before Trigger

VDDL (0V) After Trigger VDDL (0V) After Trigger

+100mA +100mA
Injected Current Pulse Injected Current Pulse

Time (10ms/div.) Time (10ms/div.)

Figure 10: Measured time-domain voltage and current waveforms Figure 13: Measured time-domain voltage and current waveforms
on the test structure A, with VDDH of 30 V and VDDL of 0 V. on the test structure B, with VDDH of 30 V and VDDL of 0 V.

VDDH (30V) Before Trigger DUT: Test Structure A VDDH (30V) Before Trigger DUT: Test Structure B
Current (50mA/div.)

Current (50mA/div.)
Voltage (10V/div.)

Voltage (10V/div.)

VDDH (30V) After Trigger VDDH (30V) After Trigger

VDDL (Floating) VDDL (Floating)

+100mA +100mA
Injected Current Pulse Injected Current Pulse

Time (10ms/div.) Time (10ms/div.)

Figure 11: Measured time-domain voltage and current waveforms Figure 14: Measured time-domain voltage and current waveforms
on the test structure A, with VDDH of 30 V and VDDL floating. on the test structure B, with VDDH of 30 V and VDDL floating.

In Fig. 9, test structure A is given with initial bias Fig. 10 shows the measured waveform with VDDL of 0
voltages of 30 V at VDDH, 1.8 V at VDDL, and 0 V at V, which is similar to the test result in Fig. 9. In Fig.
VSS. After the injection of 100-mA current pulse at 11, the measured waveform with VDDL floating does
VTrigger node, VDDH of test structure A is clamped not show any voltage roll-off at VDDH node after the
down to ~5 V and then burned out. Some transient same injection of 100-mA current pulse. From these
glitches are induced on the current pulse. Afterwards, measurement results, the latchup path between VDDH
a large leakage current is detected from VDDH to and VDDL nodes in Figs. 9 and 10 are exactly fired,
grounded VSS. However, there is no leakage current and then directly burned out at VDDH node with a
found between VDDH and VDDL nodes. It was leakage path induced between VDDH and grounded
suspected that the injected current pulse may directly VSS.
damage the test structure without inducing latchup. In As shown in Figs. 12, 13, and 14, the latchup path of
order to verify whether such latchup path is fired or test structure B is also fired and burned out with 100-
not, it is measured once again by changing VDDL to 0 mA current pulse. In addition, the voltage level of
V or to be floating. VDDH is pulled down to only ~2 V on the test structure
B after the current pulse trigger.
 P-sub Ring P-sub Ring
HVNW Ring HVNW Ring

HV pLDMOS HV pLDMOS
(Asymmetric) (Symmetric)

Trigger Node

Trigger Node
Failure Site Failure Site

S S

LV pMOS LV pMOS

(a) (b)
Figure 15: SEM photographs of (a) test structure A and (b) test structure B to show the latchup-induced damage after the injection of
latchup trigger current at trigger node, with a distance (S) of 20 μm in the latchup path.

Figure 16: Double guard rings inserted within the parasitic latchup path between HV pLDMOS and LV pMOS.

In consequence, the current-trigger latchup test has trigger node was unable to sustain the joule heating
verified that the cross-domain latchup path in both test induced by the injected current pulse of +100 mA.
structures can occur and induce the unexpected
failures.
D. Failure Analysis IV. Discussion
From the 1000-ns TLP measurement results, it is
Figs. 15(a) and 15(b) show the SEM photographs of
likely that the holding voltage of parasitic latchup
the test structures A and B, respectively, with the
path could be much lower under the dc power-on
latchup-induced damage after the injection of positive
condition, and even become more serious at the high
latchup trigger current at trigger node. It is clearly
ambient temperature (e.g., 125°C). To prevent such
found that the test structures A and B were damaged
unexpected latchup failure between different power
with some burn-out traces within the adjacent region
domains, the suggested solutions are (1) to extend the
between HV pLDMOS and LV pMOS. The failure
layout spacing between HV and LV parts and then to
sites shown in the SEM pictures are mainly located at
increase the holding voltage of the parasitic path, or
the interface of HVNW and P-sub rings. It can explain
(2) to add double guard rings to surround the HV
why there is no leakage current detected at VDDL node
pLDMOS for reducing the current gains of the
of LV pMOS. Though the expected burn-out trace
parasitic BJTs, as illustrated in Fig. 16. Based on the
from p+ source side of HV pLDMOS to VDDL-
previous study [4], different guard ring structures with
connected NW of LV pMOS was not observed, the
different spacing between HV and LV domains can be
parasitic path between HV pLDMOS and LV pMOS
studied to extract the design rules. Furthermore, it is
indeed occurred and caused the unpredictable
recommended to develop the design rules for latchup
damages. In addition, some burn-out trace near trigger
prevention by double guard ring structure with
node is found, because the narrow diffusion region of
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layout area efficiency in such a HV-to-LV boundary. compact layout rules for latchup prevention in deep-
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Acknowledgment Association, JEDEC Standard JESD78E, 2016.
This work was supported in part by the “Center for [10] C.-N. Wu, H.-M. Chou, and M. Chang, “Latch-up
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[11] Y. Huh et al., “Chip level layout and bias
by the Ministry of Education (MOE) in Taiwan. This
considerations for preventing neighboring I/O cell
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Contract of MOST 106-2622-8-009-007-TE1. The EOS/ESD Symp., 2005, pp. 1-8.
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Taiwan. development in BCD process technologies,” in Proc.
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