PTW40N50

500V N-Channel MOSFET

General Features BVDSS RDS(ON),typ. ID
 Advanced Planar Process
 RDS(ON),typ.=85 mΩ@VGS=10V 500V 85mΩ 46A
 Low Gate Charge Minimize Switching Loss
 Rugged Poly silicon Gate Structure

Applications
 BLDC Motor Driver
 Electric Welder
 High Efficiency SMPS

Ordering Information
Part Number Package Brand
PTW40N50 TO-3P

Absolute Maximum Ratings TC=25℃ unless otherwise specified

Symbol Parameter PTW40N50 Unit

VDSS Drain-to-Source Voltage 500
V
VGSS Gate-to-Source Voltage ±30
Continuous Drain Current 46
ID
Continuous Drain Current @ Tc=100℃ 30 A
IDM Pulsed Drain Current at VGS=10V[2,4] 180
EAS Single Pulse Avalanche Energy 5000 mJ
[3]
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
Power Dissipation 540 W
PD
Derating Factor above 25℃ 4.32 W/℃
Maximum Temperature for Soldering
TL 300
Leads at 0.063in (1.6mm) from Case for 10
TPAK 260
seconds, Package Body for 10 seconds ℃
TJ& TSTG Operating and Storage Temperature Range -55 to 150
Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device.

Thermal Characteristics
Symbol Parameter PTW40N50 Unit

RθJC Thermal Resistance, Junction-to-Case 0.23

℃/W
RθJA Thermal Resistance, Junction-to-Ambient 50

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017
 PTW40N50

Electrical Characteristics
OFF Characteristics TJ =25℃ unless otherwise specified
Symbol Parameter Min. Typ. Max. Unit Test Conditions

BVDSS Drain-to-Source Breakdown Voltage 500 -- -- V VGS=0V, ID=250uA

-- -- 5 VDS=500V, VGS=0V
IDSS Drain-to-Source Leakage Current uA
VDS=400V, VGS=0V,
-- -- 500
TJ =125℃

-- -- +100 VGS=+30V, VDS=0V

IGSS Gate-to-Source Leakage Current nA
-- -- -100 VGS=-30V, VDS=0V

ON Characteristics TJ =25℃ unless otherwise specified

Symbol Parameter Min. Typ. Max. Unit Test Conditions
Static Drain-to-Source
RDS(ON) -- 85 100 mΩ VGS=10V, ID=23A
On-Resistance
VGS(TH) Gate Threshold Voltage 2.0 -- 4.0 V VDS=VGS, ID=250uA

gFS Forward Transconductance -- 32 -- S VDS =25V, ID=23A

Dynamic Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Unit Test Conditions

Ciss Input Capacitance -- 1.0 --

VGS=0V,
Crss Reverse Transfer Capacitance -- 0.1 -- nF VDS=25V,
f=1.0MHZ
Coss Output Capacitance -- 0.7 --
Qg Total Gate Charge -- 138 --
VDD=250V,
Qgs Gate-to-Source Charge -- 38 -- nC
ID=23A, VGS=0 to 10V
Qgd Gate-to-Drain (Miller) Charge -- 27 --

Resistive Switching Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Unit Test Conditions

td(ON) Turn-on Delay Time -- 25 --

VDD=250V,
trise Rise Time -- 39 -- ID=23A,
nS
VGS= 10V
td(OFF) Turn-Off Delay Time -- 100 --
RG=10Ω
tfall Fall Time -- 36 --

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017
 PTW40N50
Source-Drain Body Diode Characteristics TJ=25℃ unless otherwise specified

Symbol Parameter Min Typ. Max. Unit Test Conditions

[2]
ISD Continuous Source Current -- -- 46 Integral PN-diode in
A
ISM Pulsed Source Current [2]
-- -- 180 MOSFET
VSD Diode Forward Voltage -- -- 1.5 V IS=46A, VGS=0V
trr Reverse recovery time -- 730 -- ns VGS=0V ,IF=46A,
Qrr Reverse recovery charge -- 3.0 -- uC diF/dt=100A/μs

Note:

[1] TJ=+25℃ to +150℃ .

[2] Silicon limited current only.
[3] Package limited current.
[4] Repetitive rating; pulse width limited by maximum junction temperature.
[5] Pulse width≤380µs; duty cycle≤2%.

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017
 PTW40N50

Typical Characteristics

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017
 PTW40N50

Typical Characteristics(Cont.)

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017
 PTW40N50

Typical Characteristics(Cont.)

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017
 PTW40N50

Test Circuits and Waveforms

Fig. 1.1 Peak Diode Recovery dv/dt Test Circuit

Fig. 1.2 Peak Diode Recovery dv/dt Waveforms

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017
 PTW40N50

Test Circuits and Waveforms (Cont.)

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017
 PTW40N50

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PIP. Rev. A.2017