Printed circuit board layout for switched-

mode power supply

High Voltage Seminar 2021
Ben Genereaux

1
What will I get out of this session?
• The purpose of this session is to • Part numbers mentioned:
introduce the concepts needed to – UCC28180
successfully layout a printed circuit – UCC28742
board (PCB) for a switched-mode – UCC28710
power supply (SMPS) – UCC24612
– UCC24610
• This presentation is relevant to all
SMPS PCB layouts, from 1 W to 10 kW • Reference designs mentioned:
– TIDA- 00443
Why is layout important?
• The best controller in the world cannot work
well if embedded in a poor layout
• PCB layout for SMPS is extremely
complicated!
• Same principles govern low and high power How to translate a
layouts schematic into working
– The difficulty is how to apply the principles in hardware
practice
• The PCB is often the most complex
component in a design
Agenda
• The schematic
• Parasitics
– Resistance
– Inductance
– Capacitance
• EMI & safety
• Grounding & signal routing
• Thermal management
• PCB layout example
• Summary
What are concerns for a power supply PCB
layout?
• Safety • Thermal performance
• EMI • High dv/dt
• Parasitic inductance • High di/dt
• Parasitic capacitance • Grounding
• Parasitic resistance • Noise
The schematic TIDA-00443 using UCC28180 PFC
controller

High current
Safety EMI dv/dt

di/dt

Grounding

Thermal

Understand the circuit, including the parasitic components!

Parasitic resistance
You mean copper is not a perfect conductor?

w
𝑙

Flo
Material m Ω-cm m Ω-in 𝜌∙𝑙

nt
rre
Copper 1.70 0.67 𝑅=
𝐴

Cu
Gold 2.2 0.87
Lead 22.0 8.66 A
𝜌 = 𝑟𝑒𝑠𝑖𝑠𝑡𝑖𝑣𝑖𝑡𝑦
Silver 1.5 0.59
Silver (plated) 1.8 0.71
Impacts?
Tin -lead 15 5.91
Tin (plated) 11 4.33 • Regulation
• Efficiency
ρ(Cu) = 0.67 mΩ-in at 25°C
• Temperature rise
𝑝𝑝𝑚
𝑇𝐶𝑅𝐶𝑢 ≈ 4000 ൗ℃ +40% 𝑓𝑜𝑟 100℃ 𝑟𝑖𝑠𝑒
Parasitic resistance
Assume 1 oz. Cu
Counting squares

Current Flow
𝑙
𝜌∙𝑙 𝜌
𝑅= = 2 𝑠𝑒𝑟𝑖𝑒𝑠 𝑠𝑞𝑢𝑎𝑟𝑒𝑠 = ~1.0 𝑚Ω
𝑇∙𝑙 𝑇
𝑇
t 2 𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝑠𝑞𝑢𝑎𝑟𝑒𝑠 = ~0.25 𝑚Ω
𝑙
Copper Weight (Oz.) Thickness (m/mils) m per square (25°C) m per square (125°C)

1/2 17.5/0.7 1 1.4

1 35/1.4 0.5 0.7
2 70/2.8 0.25 0.35
Parasitic resistance
Vias have resistance too
Current
Flow Typical rule of thumb is 1 A to 3 A per via
A

𝜌∙𝑙
𝑅=
𝐴
𝑙
1.5 mm
(60 mils) 𝜌∙𝑙
𝑅=
𝜋 ∙ 𝑟𝑜 2 − 𝑟𝑖 2

4.5 mm 0.67 𝜇Ω ∙ 𝑖𝑛 ∙ 0.06 𝑖𝑛

(18 mils) 𝑅= = 0.67 mΩ
𝜋 ∙ 0.01 𝑖𝑛 2 − 0.009 𝑖𝑛 2
5 mm
(20 mils)
Parasitic resistance
Poor sense location Sensing at output connector

How many mΩ between L2 and J3?

Identifying high di/dt
Switched current loops
I/P loop (green) Low di/dt High di/dt

• di/dt rates much lower

• Stray inductance is less critical Inductor MOSFET Diode current
current current
• CIN provides local low impedance
source
O/P loop (blue/red)
• Inductor current alternates between
MOSFET and diode paths
I/P loop O/P loop
• Pulsating currents
• Stray inductance will cause voltage Simplified PFC boost
spikes schematic
Identifying high di/dt
Reverse recovery
Occurs when:
• MOSFET turns ON during CCM
operation (nearly every topology)
• Stray inductance will cause voltage
spikes
Mitigation:
• Minimize loop inductance
• Use low QRR rectifiers –
− SiC for high VOUT
− Schottky or ultra-fast diodes Simplified PFC boost
− Sync rectifiers with low Q RR schematic
Identifying high di/dt
Gate drives
High di/dt in loop (yellow)
• Stray inductance: IGATE VGATE
– Limits drive current
– Can cause ringing
• Minimize loop inductance
High dv/dt on gate (blue)
• Can couple to noise-sensitive
nodes
• Minimize capacitance
Simplified PFC boost
schematic
 Parasitic inductance
Self inductance of PWB traces
• Due to the natural logarithmic relationship, large changes in conductor width have
minimal impact on inductance
𝑙 1
𝐿 = 2 ∙ 𝑙 ∙ 𝑙𝑛 + 𝑛𝐻ൗ𝑐𝑚
𝑇+𝑊 2
𝑙 1
𝑙 𝐿 = 5 ∙ 𝑙 ∙ 𝑙𝑛 + 𝑛𝐻ൗ𝑖𝑛
w
lo
tF 𝑇+𝑊 2
n
re
ur

Inductance
C

w W (mm/in) T(mm/in)
(nH/cm or nH/in)
t𝑇
0.25/0.01 0.07/0.0028 10/24
2.5/0.1 0.07/0.0028 6/14
12.5/0.5 0.07/0.0028 2/6
Parasitic inductance
PWB traces over ground planes
• Substantial inductance reduction w Current
Flow
• Inductance inversely proportional to width h

2 ∙ ℎ ∙ 𝑙 𝑛𝐻 5 ∙ ℎ ∙ 𝑙 𝑛𝐻
𝐿= ൗ𝑐𝑚 𝐿= ൗ𝑖𝑛
𝑤 𝑤
Metric English
Inductance Inductance
h (cm) w (cm) h (in) w (in)
(nH/cm) (nH/in)
0.25 2.5 0.2 0.01 0.1 0.5
1.5 2.5 1.2 0.06 0.1 3.0
Parasitic inductance
Low series inductance
High series inductance

How much inductance in series with C39? (total length ~ 2 cm)

Identifying high dv/dt
Switched nodes The switched node paradox
High dv/dt at switched node Lower resistance
(blue): Increased surface area Lower inductance
Better cooling
• Switched between 0V and VOUT
• Stray capacitance can cause: Decreased surface area Lower capacitance
– EMI problems
VSW
– Noise injected to internal circuits
– Reduced efficiency
Mitigation:
• Minimize VSW surface area
• Keep sensitive etch and
components away from VSW
Simplified PFC boost
• Ground the heatsink! schematic
Parasitic capacitance
Sample capacitance calculation

Consider two 10 mil traces crossing with 10 mil PWB thickness

A = 0.00025 m x 0.00025 m
𝜀𝑟 ∙ 𝜀0 ∙ 𝐴
𝐶=
𝑡
5 ∙ 8.85 × 10−12 𝐹ൗ𝑚 ∙ 0.25 𝑚𝑚 2
𝐶=
2.5 𝑚𝑚
t

𝐶 = 0.01 𝑝𝐹
Note: 10 mils = 0.00025 m

Not much capacitance but consider the area of all components connected to the feedback
network
Parasitic capacitance

Chaos created by
noise injection
VSW

Ten 0.05 x 0.02 in2 pads

can increase parasitic
capacitance to 2 pF Cparasitic

Noise sensitive
 Parasitic capacitance
At high frequency inductors turn into capacitors

Don’t route planes under common mode inductors!

CIND_PARASITIC
23 pF 3 cm 2 (0.5 in2) area with
100 0.25 mm (0.01 in) thickness or
1 Layer of PWB
C = 23 pF
Impedance - k

10 L1
L = 28 mH
28 mH

CPWB_A CPWB_B
50 pF 50 pF
1k 10 k 100 k 1M
Frequency - Hz
Ground Plane
EMI considerations
Magnetic coupling

• External fields couple between inductors

• Can cause EMI issues
• Consider alternate orientation of second
inductor to minimize coupling
• Use core shapes that provide better
shielding
EMI considerations
Input filter layout
• Place components away from noise
sources
• Common mode inductor T2 input pins
do not cross output pins
• No GND plane under EMI filter
• Wide, short etch used to minimize
losses
• Wide spacing between etches meets
high-voltage requirements and
minimizes coupling capacitance
Safety
Separate hazardous voltages from user accessible points
• Consult your safety expert!
• Create a very clear channel
between primary and secondary
• Spacing depends on:
– Type of insulation
– Pollution degree
– AC mains voltage
– Working voltage
• Types of insulation:
– Functional
– Basic/supplementary
– Reinforced Partial Clearance Dimensions (mm) from UL60950-1, Section 2.10.3,
Table 2H
Ground planes
Ground planes provide:
• Low resistance return paths
• Low inductance return paths
• Lateral heat spreading across board
General ground plane tips:
• Consider flooding empty areas with ground
☺
• Avoid putting slots in GND planes
• Use jumpers on single layer boards to
improve GND planes
• Place as much GND under the IC as
possible
Signal routing/placement
Avoid coupling noise to sensitive nodes
VSW VSW

• Maximize the separation

– Move the source, reduce Cstray
Good
Bad • Place capacitors and resistors near pins
• Place GND vias near caps, resistors,
and IC
• Minimize the unfiltered track length
Signal routing/placement
Data sheets normally contain
PCB layout guidelines
Thermal management
PCB cooling strategy
• Have solid ground planes to better • Maximize the thermal paths with
spread heat across the layer partial pours wherever practical
• Avoid breaks in planes as they • DO NOT use switched node for
substantially degrade lateral heat cooling
flow
• Use thermal vias to spread heat to
other layers
• Thermal pads help to get the heat
out of the IC into the PCB
• Use both sides of the board to cool
Thermal management
Board A Board B
Why is Board A
hotter than Board

BOTTOM
B?
• Traces on the bottom
layer prevent heat from
spreading effectively

• Removing horizontal
trace for a more solid
bottom layer reduces IC

TOP
temp on board B

• Hottest component on B
is the catch diode
PCB layout example
Gather information and place large
components
DC out
Useful information:
– PCB size and (layers, layer spacing, material)
– Position of inlet and outlet connections
– Mechanical restraints (keep outs and height restrictions)
– Manufacturing process constraints

AC in
– Know the creepage and clearance requirements
Understand the circuit:
– High current paths
– High di/dt paths
– High dv/dt nodes
– Hot parts
UCC28710/UCC24610 PSR flyback
Imagine a general ‘flow’
with SR
– Trunk packing algorithm
PCB layout example UCC28710/UCC24610 PSR flyback
with SR
Place remaining components SR controller
• Place the large parts in the power path
first
• Reserve a ‘quiet’ location for the
controller
– NOT under transformer or node with high
dv/dt
– Place its associated parts nearby
• Reserve an area for the input filter
– Keep filter input away from output
– Rotate, reposition, reassign pins, repeat
PWM controller
PCB layout example
Route power and signal etch
Two layers:
– Bottom layer (red)
– Top layer (blue)
Route power path first
– Use wide etch and polygon Output loop
pours
– Minimize high di/dt loop area
– Minimize high dv/dt surface
area
Route signal etch last
− Keep away from high dv/dt
nodes
− Keep noise sensitive etch short Input loop
UCC28710/UCC24610 PSR flyback
− Shorten return paths with SR
PCB layout example
Pour ground planes
Flood empty areas:
– Primary GND
– Secondary GND
Use vias to connect to GND
planes Flood highlighted
areas with GND
– Near caps/resistors
– Near GND pins of ICs
Check for blocked GND
connections
– Move parts/etch as necessary
– Be mindful of parasitic
resistance and inductance
UCC28710/UCC24610 PSR flyback
with SR
Summary: keys to a successful SMPS layout
• Understand your circuit: high current and di/dt paths, high dv/dt nodes

• Understand how parasitic resistance, inductance, and capacitance are manifested

• Understand how layout can significantly affect EMI

• Understand the safety requirements for your product

• Understand how heat is transferred through the PCB

• Follow a logical procedure:

– Place large parts, place small parts, power routing, signal routing, pour planes

• Have someone review your layout!

Summary: references
• Constructing Your Power Supply - Layout Considerations; R. Kollman; 2004 TI
Power Supply Design Seminar; www.ti.com/seclit/ml/slup230/slup230.pdf
• Safety Considerations in Power Supply Design; B. Mammano and L. Bahra; 2004 TI
Power Supply Design Seminar; www.ti.com/seclit/ml/slup227/slup227.pdf
• Common Mistakes in DC/DC Converters and How to Fix Them; P. Shenoy and A.
Fagnani; 2018 TI Power Supply Design Seminar; www.ti.com/seclit/ml/slup384/slup384.pdf
• Grounding in Mixed-Signal Systems Demystified, Part 1 & Part 2; S. Pithadia and
S. More; 1Q 2013, TI Analog Applications Journal; www.ti.com/lit/an/slyt499/slyt499.pdf;
www.ti.com/lit/an/slyt512/slyt512.pdf
• Why Should You Count Squares; Brigitte; 2016 TI Power House Blog;
http://e2e.ti.com/blogs_/b/powerhouse/archive/2016/10/03/why-should-i-count-squares
Thank you
HVS content available for download at: www.ti.com/highvolt

35
 SLYP762

©2021 Texas Instruments Incorporated. All rights reserved.

 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated