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Assignment 5

This document contains the module details for the VLSI Design course with code 18EC72 taught in the 7th semester. It lists the 7 topics to be covered in Module 4, including explaining logic '1' transfer in dynamic NMOS logic, discussing the dynamic bootstrapping technique, designing a three stage enhancement load dynamic shift register, explaining a 3-bit dynamic shift register with depletion load, and more. It also provides the relevant slide numbers and page references for the module PPT.

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Phanindra Reddy
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78 views1 page

Assignment 5

This document contains the module details for the VLSI Design course with code 18EC72 taught in the 7th semester. It lists the 7 topics to be covered in Module 4, including explaining logic '1' transfer in dynamic NMOS logic, discussing the dynamic bootstrapping technique, designing a three stage enhancement load dynamic shift register, explaining a 3-bit dynamic shift register with depletion load, and more. It also provides the relevant slide numbers and page references for the module PPT.

Uploaded by

Phanindra Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Department of Electronics & Communication Engineering

Name of the Course :VLSI Design Course Code: 18EC72

Sem/Sec: VII ‘A&B’ Faculty Name: Jayalakshmi N

MODULE-4
1. Briefly explain logic ‘1’ transfer in dynamic NMOS logic.[K3] MODULE 4 PPT
SLIDE 24, PG 224
2. Discuss dynamic bootstrapping technique with neat diagram and waveform.[K3]
MODULE 4 PPT SLIDE 27, PG 231
3. Design a three stage enhancement load dynamic shift register with ratioed logic.[K4]
MODULE 4 PPT SLIDE 37,PG 236
4. With necessary circuit diagram explain 3-bit dynamic shift register with depletion
load.[K4] MODULE 4 PPT SLIDE 32,PG 243
5. Explain dynamic CMOS logic gate with an example.[K2] MODULE 4 PPT SLIDE
38,PG 238
6. Explain cascading problem in dynamic CMOS logic with neat figure.[K2]
MODULE 4 PPT SLIDE 40,PG 239
7. Explain the General structure of Ratioless synchronous dynamic logic with relevant
diagram.[K2] MODULE 4 PPT SLIDE 36,PG 237

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