LMC6484 CMOS Quad Rail-to-Rail Input and Output Operational Amplifier

May 1999

LMC6484
CMOS Quad Rail-to-Rail Input and Output Operational
Amplifier
General Description Features
The LMC6484 provides a common-mode range that extends (Typical unless otherwise noted)
to both supply rails. This rail-to-rail performance combined n Rail-to-Rail Input Common-Mode Voltage Range
with excellent accuracy, due to a high CMRR, makes it (Guaranteed Over Temperature)
unique among rail-to-rail input amplifiers. n Rail-to-Rail Output Swing (within 20 mV of supply rail,
It is ideal for systems, such as data acquisition, that require 100 kΩ load)
a large input signal range. The LMC6484 is also an excellent n Guaranteed 3V, 5V and 15V Performance
upgrade for circuits using limited common-mode range am- n Excellent CMRR and PSRR: 82 dB
plifiers such as the TLC274 and TLC279. n Ultra Low Input Current: 20 fA
Maximum dynamic signal range is assured in low voltage n High Voltage Gain (RL = 500 kΩ): 130 dB
and single supply systems by the LMC6484’s rail-to-rail out- n Specified for 2 kΩ and 600Ω loads
put swing. The LMC6484’s rail-to-rail output swing is guaran-
teed for loads down to 600Ω.
Guaranteed low voltage characteristics and low power dissi-
Applications
pation make the LMC6484 especially well-suited for n Data Acquisition Systems
battery-operated systems. n Transducer Amplifiers
See the LMC6482 data sheet for a Dual CMOS operational n Hand-held Analytic Instruments
amplifier with these same features. n Medical Instrumentation
n Active Filter, Peak Detector, Sample and Hold, pH
Meter, Current Source
n Improved Replacement for TLC274, TLC279

3V Single Supply Buffer Circuit

Rail-to-Rail Input Rail-to-Rail Output

DS011714-3
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© 1999 National Semiconductor Corporation DS011714 [Link]

 Connection Diagram

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Ordering Information
Package Temperature Range NSC Transport
Military Industrial Drawing Media
−55˚C to +125˚C −40˚C to +85˚C
14-pin LMC6484MN LMC6484AIN N14A Rail
Molded DIP LMC6484IN
14-pin LMC6484AIM M14A Rail
Small Outline LMC6484IM Tape and
Reel
14-pin Ceramic LMC6484AMJ/883 J14A Rail
DIP
14-pin LMC6484AMWG/883 WG14A Tray
Ceramic SOIC

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 Absolute Maximum Ratings (Note 1) Storage Temperature Range −65˚C to +150˚C
If Military/Aerospace specified devices are required, Junction Temperature (Note 4) 150˚C
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications. Operating Ratings (Note 1)
ESD Tolerance (Note 2) 2.0 kV Supply Voltage 3.0V ≤ V+ ≤ 15.5V
Differential Input Voltage ± Supply Voltage Junction Temperature Range
Voltage at Input/Output Pin (V+) + 0.3V, (V−) − 0.3V LMC6484AM −55˚C ≤ TJ ≤ +125˚C
Supply Voltage (V+ − V−) 16V LMC6484AI, LMC6484I −40˚C ≤ TJ ≤ +85˚C
Current at Input Pin (Note 12) ± 5 mA Thermal Resistance (θJA)
Current at Output Pin N Package, 14-Pin Molded DIP 70˚C/W
(Notes 3, 8) ± 30 mA M Package, 14-Pin
Current at Power Supply Pin 40 mA Surface Mount 110˚C/W
Lead Temp. (Soldering, 10 sec.) 260˚C

DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface
limits apply at the temperature extremes.
Typ LMC6484AI LMC6484I LMC6484M
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
VOS Input Offset Voltage 0.110 0.750 3.0 3.0 mV
1.35 3.7 3.8 max
TCVOS Input Offset Voltage 1.0 µV/˚C
Average Drift
IB Input Current (Note 13) 0.02 4.0 4.0 100 pA max
IOS Input Offset Current (Note 13) 0.01 2.0 2.0 50 pA max
CIN Common-Mode 3 pF
Input Capacitance
RIN Input Resistance > 10 Tera Ω
CMRR Common Mode 0V ≤ VCM ≤ 15.0V, 82 70 65 65 dB
Rejection Ratio V+ = 15V 67 62 60 min
0V ≤ VCM ≤ 5.0V 82 70 65 65
V+ = 5V 67 62 60
+PSRR Positive Power Supply 5V ≤ V+ ≤ 15V, 82 70 65 65 dB
Rejection Ratio V− = 0V, VO = 2.5V 67 62 60 min
−PSRR Negative Power Supply −5V ≤ V− ≤ −15V, 82 70 65 65 dB
Rejection Ratio V+ = 0V, VO = −2.5V 67 62 60 min
VCM Input Common-Mode V+ = 5V and 15V V− − 0.3 −0.25 −0.25 −0.25 V
Voltage Range For CMRR ≥ 50 dB 0 0 0 max
V+ + 0.3 V+ + 0.25 V+ + 0.25 V+ + 0.25 V
V+ V+ V+ min
AV Large Signal RL = 2kΩ Sourcing 666 140 120 120 V/mV
Voltage Gain (Notes 7, 13) 84 72 60 min
Sinking 75 35 35 35 V/mV
20 20 18 min
RL = 600Ω Sourcing 300 80 50 50 V/mV
(Notes 7, 13) 48 30 25 min
Sinking 35 20 15 15 V/mV
13 10 8 min

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 DC Electrical Characteristics (Continued)

Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface
limits apply at the temperature extremes.
Typ LMC6484AI LMC6484I LMC6484M
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
VO Output Swing V+ = 5V 4.9 4.8 4.8 4.8 V
RL = 2 kΩ to V+/2 4.7 4.7 4.7 min
0.1 0.18 0.18 0.18 V
0.24 0.24 0.24 max
V+ = 5V 4.7 4.5 4.5 4.5 V
RL = 600Ω to V+/2 4.24 4.24 4.24 min
0.3 0.5 0.5 0.5 V
0.65 0.65 0.65 max
V+ = 15V 14.7 14.4 14.4 14.4 V
RL = 2 kΩ to V+/2 14.2 14.2 14.2 min
0.16 0.32 0.32 0.32 V
0.45 0.45 0.45 max
V+ = 15V 14.1 13.4 13.4 13.4 V
RL = 600Ω to V+/2 13.0 13.0 13.0 min
0.5 1.0 1.0 1.0 V
1.3 1.3 1.3 max
ISC Output Short Circuit Sourcing, VO = 0V 20 16 16 16 mA
Current 12 12 10 min
V+ = 5V Sinking, VO = 5V 15 11 11 11 mA
9.5 9.5 8.0 min
ISC Output Short Circuit Sourcing, VO = 0V 30 28 28 28 mA
Current 22 22 20 min
V+ = 15V Sinking, VO = 12V 30 30 30 30 mA
(Note 8) 24 24 22 min
IS Supply Current All Four Amplifiers 2.0 2.8 2.8 2.8 mA
V+ = +5V, VO = V+/2 3.6 3.6 3.8 max
All Four Amplifiers 2.6 3.0 3.0 3.0 mA
V+ = +15V, VO = V+/2 3.8 3.8 4.0 max

AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface
limits apply at the temperature extremes.
Typ LMC6484A LMC6484I LMC6484M
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
SR Slew Rate (Note 9) 1.3 1.0 0.9 0.9 V/µs
0.7 0.63 0.54 min
GBW Gain-Bandwidth Product V+ = 15V 1.5 MHz
φm Phase Margin 50 Deg
Gm Gain Margin 15 dB
Amp-to-Amp Isolation (Note 10) 150 dB
en Input-Referred f = 1 kHz 37
Voltage Noise VCM = 1V
in Input-Referred f = 1 kHz 0.03
Current Noise

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 AC Electrical Characteristics (Continued)

Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface
limits apply at the temperature extremes.
Typ LMC6484A LMC6484I LMC6484M
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
T.H.D. Total Harmonic Distortion f = 1 kHz, AV = −2 0.01 %
RL = 10 kΩ, VO = 4.1 VPP
f = 10 kHz, AV = −2
RL = 10 kΩ, VO = 8.5 VPP 0.01 %
V+ = 10V

DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 3V, V− = 0V, VCM = VO = V+/2 and RL > 1M
Typ LMC6484AI LMC6484I LMC6484M
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
VOS Input Offset Voltage 0.9 2.0 3.0 3.0 mV
2.7 3.7 3.8 max
TCVOS Input Offset Voltage 2.0 µV/˚C
Average Drift
IB Input Bias Current 0.02 pA
IOS Input Offset Current 0.01 pA
CMRR Common Mode 0V ≤ VCM ≤ 3V 74 64 60 60 dB
Rejection Ratio min
PSRR Power Supply 3V ≤ V+ ≤ 15V, V− = 0V 80 68 60 60 dB
Rejection Ratio min
VCM Input Common-Mode For CMRR ≥ 50 dB V− − 0.25 0 0 0 V
Voltage Range max
V+ + 0.25 V+ V+ V+ V
min
VO Output Swing RL = 2 kΩ to V+/2 2.8 V
0.2 V
RL = 600Ω to V+/2 2.7 2.5 2.5 2.5 V
min
0.37 0.6 0.6 0.6 V
max
IS Supply Current All Four Amplifiers 1.65 2.5 2.5 2.5 mA
3.0 3.0 3.2 max

AC Electrical Characteristics
Unless otherwise specified, V+ = 3V, V− = 0V, VCM = VO = V+/2 and RL > 1M
Typ LMC6484AI LMC6484I LMC6484M
Symbol Parameter Conditions (Note 5) Limit Limit Limit Units
(Note 6) (Note 6) (Note 6)
SR Slew Rate (Note 11) 0.9 V/µs
GBW Gain-Bandwidth Product 1.0 MHz
T.H.D. Total Harmonic Distortion f = 10 kHz, AV = −2 0.01 %
RL = 10 kΩ, VO = 2 VPP
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5 kΩ in series with 100 pF. All pins rated per method 3015.6 of MIL-STD-883. This is a class 2 device rating.

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 AC Electrical Characteristics (Continued)
Note 3: Applies to both single supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maxi-
mum allowed junction temperature of 150˚C. Output currents in excess of ± 30 mA over long term may adversely affect reliability.
Note 4: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max)
− TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 5: Typical Values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 3.5V ≤ VO ≤ 7.5V.
Note 8: Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected.
Note 9: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of either the positive or negative slew rates.
Note 10: Input referred, V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP.
Note 11: Connected as Voltage Follower with 2V step input. Number specified is the slower of either the positive or negative slew rates.
Note 12: Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
Note 13: Guaranteed limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
Note 14: For guaranteed Military Temperature Range parameters see RETSMC6484X.

Typical Performance Characteristics VS = +15V, Single Supply, TA = 25˚C unless otherwise

specified

Supply Current vs Input Current vs Sourcing Current vs

Supply Voltage Temperature Output Voltage

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Sourcing Current vs Sourcing Current vs Sinking Current vs

Output Voltage Output Voltage Output Voltage

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Typical Performance Characteristics VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)

Sinking Current vs Sinking Current vs Output Voltage Swing

Output Voltage Output Voltage vs Supply Voltage

DS011714-45 DS011714-46
DS011714-47

Input Voltage Noise Input Voltage Noise

vs Frequency vs Input Voltage

DS011714-48 DS011714-49

Input Voltage Noise Input Voltage Noise Crosstalk Rejection

vs Input Voltage vs Input Voltage vs Frequency

DS011714-50 DS011714-51
DS011714-52

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 Typical Performance Characteristics VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)

Crosstalk Rejection Positive PSRR Negative PSRR

vs Frequency vs Frequency vs Frequency

DS011714-53 DS011714-54 DS011714-55

CMRR vs Frequency CMRR vs Input Voltage CMRR vs Input Voltage

DS011714-56 DS011714-57 DS011714-58

CMRR vs Input Voltage ∆VOS vs CMR ∆ VOS vs CMR

DS011714-59 DS011714-60 DS011714-61

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Typical Performance Characteristics VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)

Input Voltage Input Voltage Open Loop

vs Output Voltage vs Output Voltage Frequency Response

DS011714-62 DS011714-63
DS011714-64

Open Loop Frequency Open Loop Frequency Maximum Output Swing

Response Response vs Temperature vs Frequency

DS011714-65 DS011714-66 DS011714-67

Gain and Phase Gain and Phase Open Loop Output

vs Capacitive Load vs Capacitive Load Impedance vs Frequency

DS011714-68 DS011714-69 DS011714-70

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 Typical Performance Characteristics VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)

Open Loop Output Slew Rate vs Non-Inverting Large Signal

Impedance vs Frequency Supply Voltage Pulse Response

DS011714-71 DS011714-72 DS011714-73

Non-Inverting Large Signal Non-Inverting Large Signal Non-Inverting Small Signal

Pulse Response Pulse Response Pulse Response

DS011714-74 DS011714-75 DS011714-76

Non-Inverting Small Signal Non-Inverting Small Signal Inverting Large Signal

Pulse Response Pulse Response Pulse Response

DS011714-77 DS011714-78 DS011714-79

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Typical Performance Characteristics VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)

Inverting Large Signal Inverting Large Signal Inverting Small Signal

Pulse Response Pulse Response Pulse Response

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Inverting Small Signal Inverting Small Signal Stability vs

Pulse Response Pulse Response Capacitive Load

DS011714-83 DS011714-84
DS011714-85

Stability vs Stability vs Stability vs

Capacitive Load Capacitive Load Capacitive Load

DS011714-86 DS011714-87 DS011714-88

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 Typical Performance Characteristics VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)

Stability vs Stability vs
Capacitive Load Capacitive Load

DS011714-89 DS011714-90

Application Information ceeding this absolute maximum rating, as in Figure 2, can

cause excessive current to flow in or out of the input pins
possibly affecting reliability.
1.0 Amplifier Topology
The LMC6484 incorporates specially designed
wide-compliance range current mirrors and the body effect to
extend input common mode range to each supply rail.
Complementary paralleled differential input stages, like the
type used in other CMOS and bipolar rail-to-rail input ampli-
fiers, were not used because of their inherent accuracy prob-
lems due to CMRR, cross-over distortion, and open-loop
gain variation.
The LMC6484’s input stage design is complemented by an
output stage capable of rail-to-rail output swing even when
driving a large load. Rail-to-rail output swing is obtained by
taking the output directly from the internal integrator instead
of an output buffer stage.
DS011714-12
2.0 Input Common-Mode Voltage Range
FIGURE 2. A ± 7.5V Input Signal Greatly
Unlike Bi-FET amplifier designs, the LMC6484 does not ex- Exceeds the 3V Supply in Figure 3 Causing
hibit phase inversion when an input voltage exceeds the No Phase Inversion Due to RI
negative supply voltage. Figure 1 shows an input voltage ex-
ceeding both supplies with no resulting phase inversion on Applications that exceed this rating must externally limit the
the output. maximum input current to ± 5 mA with an input resistor as
shown in Figure 3.

DS011714-11

FIGURE 3. RI Input Current Protection for

Voltages Exceeding the Supply Voltage

3.0 Rail-To-Rail Output

The approximated output resistance of the LMC6484 is
DS011714-10
180Ω sourcing and 130Ω sinking at VS = 3V and 110Ω
FIGURE 1. An Input Voltage Signal Exceeds the sourcing and 83Ω sinking at VS = 5V. Using the calculated
LMC6484 Power Supply Voltages with output resistance, maximum output voltage swing can be es-
No Output Phase Inversion timated as a function of load.
The absolute maximum input voltage is 300 mV beyond ei-
4.0 Capacitive Load Tolerance
ther supply rail at room temperature. Voltages greatly ex-
The LMC6484 can typically directly drive a 100 pF load with
VS = 15V at unity gain without oscillating. The unity gain fol-
lower is the most sensitive configuration. Direct capacitive

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Application Information (Continued)

loading reduces the phase margin of op-amps. The combi-

nation of the op-amp’s output impedance and the capacitive
load induces phase lag. This results in either an under-
damped pulse response or oscillation.
Capacitive load compensation can be accomplished using
resistive isolation as shown in Figure 4. This simple tech-
nique is useful for isolating the capacitive input of multiplex-
ers and A/D converters.

DS011714-17
DS011714-16

FIGURE 4. Resistive Isolation FIGURE 7. Pulse Response of

of a 330 pF Capacitive Load LMC6484 Circuit in Figure 6

5.0 Compensating for Input Capacitance

It is quite common to use large values of feedback resis-
tance with amplifiers that have ultra-low input current, like
the LMC6484. Large feedback resistors can react with small
values of input capacitance due to transducers, photo-
diodes, and circuit board parasitics to reduce phase
margins.

DS011714-18

FIGURE 5. Pulse Response of

the LMC6484 Circuit in Figure 4 DS011714-19

Improved frequency response is achieved by indirectly driv- FIGURE 8. Canceling the Effect of Input Capacitance
ing capacitive loads as shown in Figure 6.
The effect of input capacitance can be compensated for by
adding a feedback capacitor. The feedback capacitor (as in
Figure 8 ), Cf, is first estimated by:

or
R1 CIN ≤ R2 Cf
which typically provides significant overcompensation.
DS011714-15 Printed circuit board stray capacitance may be larger or
smaller than that of a breadboard, so the actual optimum
FIGURE 6. LMC6484 Non-Inverting Amplifier,
value for Cf may be different. The values of Cf should be
Compensated to Handle a 330 pF Capacitive Load
checked on the actual circuit. (Refer to the LMC660 quad
R1 and C1 serve to counteract the loss of phase margin by CMOS amplifier data sheet for a more detailed discussion.)
feeding forward the high frequency component of the output
signal back to the amplifier’s inverting input, thereby preserv- 6.0 Printed-Circuit-Board Layout for High-Impedance
ing phase margin in the overall feedback loop. The values of Work
R1 and C1 are experimentally determined for the desired It is generally recognized that any circuit which must operate
pulse response. The resulting pulse response can be seen in with less than 1000 pA of leakage current requires special
Figure 7. layout of the PC board. when one wishes to take advantage

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 Application Information (Continued)

of the ultra-low input current of the LMC6484, typically less

than 20 fA, it is essential to have an excellent layout. Fortu-
nately, the techniques of obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear accept-
ably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6484’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs, as in Fig-
DS011714-21
ure 9. To have a significant effect, guard rings should be
placed in both the top and bottom of the PC board. This PC Inverting Amplifier
foil must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 1012Ω, which is nor-
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This
would cause a 250 times degradation from the LMC6484’s
actual performance. However, if a guard ring is held within 5
mV of the inputs, then even a resistance of 1011Ω would DS011714-22

cause only 0.05 pA of leakage current. See Figure 10 for Non-Inverting Amplifier
typical connections of guard rings for standard op-amp
configurations.

DS011714-23

Follower
FIGURE 10. Typical Connections of Guard Rings

The designer should be aware that when it is inappropriate

to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an in-
sulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board con-
struction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring.
See Figure 11.

DS011714-20

FIGURE 9. Example of Guard Ring in P.C. Board

Layout

DS011714-24

(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
FIGURE 11. Air Wiring

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Application Information (Continued)

7.0 Offset Voltage Adjustment

Offset voltage adjustment circuits are illustrated in Figures
13, 14. Large value resistances and potentiometers are used
to reduce power consumption while providing typically ± 2.5
mV of adjustment range, referred to the input, for both con-
figurations with VS = ± 5V.

DS011714-26

FIGURE 13. Non-Inverting Configuration

Offset Voltage Adjustment

8.0 Upgrading Applications

The LMC6484 quads and LMC6482 duals have industry
standard pin outs to retrofit existing applications. System
performance can be greatly increased by the LMC6484’s
features. The key benefit of designing in the LMC6484 is in-
DS011714-25 creased linear signal range. Most op-amps have limited in-
FIGURE 12. Inverting Configuration put common mode ranges. Signals that exceed this range
Offset Voltage Adjustment generate a non-linear output response that persists long af-
ter the input signal returns to the common mode range.
Linear signal range is vital in applications such as filters
where signal peaking can exceed input common mode
ranges resulting in output phase inversion or severe distor-
tion.

9.0 Data Acquisition Systems

Low power, single supply data acquisition system solutions
are provided by buffering the ADC12038 with the LMC6484
(Figure 14). Capable of using the full supply range, the
LMC6484 does not require input signals to be scaled down
to meet limited common mode voltage ranges. The
LMC6484 CMRR of 82 dB maintains integral linearity of a
12-bit data acquisition system to ± 0.325 LSB. Other
rail-to-rail input amplifiers with only 50 dB of CMRR will de-
grade the accuracy of the data acquisition system to only 8
bits.

15 [Link]
 Application Information (Continued)

DS011714-28

FIGURE 14. Operating from the same

Supply Voltage, the LMC6484 buffers the
ADC12038 maintaining excellent accuracy
10.0 Instrumentation Circuits cations that benefit from these features include analytic
The LMC6484 has the high input impedance, large medical instruments, magnetic field detectors, gas detectors,
common-mode range and high CMRR needed for designing and silicon-based transducers.
instrumentation circuits. Instrumentation circuits designed A small valued potentiometer is used in series with Rg to set
with the LMC6484 can reject a larger range of the differential gain of the 3 op-amp instrumentation circuit in
common-mode signals than most in-amps. This makes in- Figure 15. This combination is used instead of one large val-
strumentation circuits designed with the LMC6484 an excel- ued potentiometer to increase gain trim accuracy and reduce
lent choice for noisy or industrial environments. Other appli- error due to vibration.

DS011714-29

FIGURE 15. Low Power 3 Op-Amp Instrumentation Amplifier

A 2 op-amp instrumentation amplifier designed for a gain of

100 is shown in Figure 16. Low sensitivity trimming is made

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Application Information (Continued) Higher frequency and larger common-mode range applica-
tions are best facilitated by a three op-amp instrumentation
for offset voltage, CMRR and gain. Low cost and low power amplifier.
consumption are the main advantages of this two op-amp
circuit.

DS011714-30

FIGURE 16. Low-Power Two-Op-Amp Instrumentation Amplifier

11.0 Spice Macromodel

A spice macromodel is available for the LMC6484. This
model includes accurate simulation of:
• input common-mode voltage range
• frequency and transient response
• GBW dependence on loading conditions
• quiescent and dynamic supply current
• output swing dependence on loading conditions
and many more characteristics as listed on the macromodel
disk.
Contact your local National Semiconductor sales office to
obtain an operational amplifier spice model library disk.

Typical Single-Supply Applications

DS011714-32

FIGURE 18. Half-Wave Rectifier Waveform

The circuit in Figure 17 use a single supply to half wave rec-

tify a sinusoid centered about ground. RI limits current into
the amplifier caused by the input voltage exceeding the sup-
ply voltage. Full wave rectification is provided by the circuit in
Figure 19.

DS011714-31

FIGURE 17. Half-Wave Rectifier with

Input Current Protection (RI)

DS011714-33

FIGURE 19. Full Wave Rectifier

with Input Current Protection (RI)

17 [Link]
 Typical Single-Supply Applications (Continued)

DS011714-34

FIGURE 20. Full Wave Rectifier Waveform

DS011714-35

FIGURE 21. Large Compliance Range Current Source

DS011714-36

FIGURE 22. Positive Supply Current Sense

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Typical Single-Supply Applications (Continued)

DS011714-37

FIGURE 23. Low Voltage Peak Detector with Rail-to-Rail Peak Capture Range

In Figure 23 dielectric absorption and leakage is minimized by using a polystyrene or polyethylene hold capacitor. The droop rate
is primarily determined by the value of CH and diode leakage current. The ultra-low input current of the LMC6484 has a negligible
effect on droop.

DS011714-38

FIGURE 24. Rail-to-Rail Sample and Hold

The LMC6484’s high CMRR (85 dB) allows excellent accuracy throughout the circuit’s rail-to-rail dynamic capture range.

DS011714-27

FIGURE 25. Rail-to-Rail Single Supply Low Pass Filter

The low pass filter circuit in Figure 25 can be used as an anti-aliasing filter with the same voltage supply as the A/D converter.
Filter designs can also take advantage of the LMC6484 ultra-low input current. The ultra-low input current yields negligible offset
error even when large value resistors are used. This in turn allows the use of smaller valued capacitors which take less board
space and cost less.

19 [Link]
 Physical Dimensions inches (millimeters) unless otherwise noted

14-Pin Ceramic Dual-In-Line Package

Order Number LMC6484AMJ/883, LMC6484AMWG/883
NS Package Number J14A, WG14A

[Link] 20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Pin Small Outline

Order Package Number LMC6484AIM or LMC6484IM
NS Package Number M14A

21 [Link]
LMC6484 CMOS Quad Rail-to-Rail Input and Output Operational Amplifier
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Pin Molded DIP

Order Package Number LMC6484AIN, LMC6484IN or LMC6484MN
NS Package Number N14A

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accordance with instructions for use provided in the safety or effectiveness.
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