CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 9, NO.

1, JANUARY 2023 365

Isolated Bipolar Modular Multilevel DC-DC

Converter with Self-balancing Capability for
Interconnection of MVDC and LVDC Grids
Jinmu Lai, Member, IEEE, Xin Yin , Member, IEEE, Yaoqiang Wang, Senior Member, IEEE, Lin Jiang,
Member, IEEE, Zia Ullah, Member, IEEE, and Xianggen Yin, Senior Member, IEEE

Abstract—Bipolar medium-voltage DC (MVDC) and low- equipment often require a bipolar voltage supply rather than a
voltage DC (LVDC) grids have the advantages of flexible inte- monopolar one, as shown in Fig. 1. For example, 1500 V DC
gration of distributed renewable-energy generation and reliable for photo-voltaic and energy storage solutions are becoming
power supply. In order to achieve voltage conversion, power
transfer, and electrical isolation for bipolar MVDC and LVDC available voltage level [6], [7]; 750 V DC is suitable for
grids, a high-power DC-DC converter is essential. Therefore, an electric vehicle charger and industry users [8], [9]. IEC
this paper proposes an isolated bipolar modular multilevel DC- 60038, IEEE standard 1709–2010 and CIGRE SC6.31 specify
DC converter (BiMMDC) with power self-balancing capability a reasonable range of voltage levels for DC distribution grids
for interconnection of MVDC and LVDC grids. The proposed
and ships’ power supply. Therefore, a bipolar DC distribution
BiMMDC consists of two series connected MMCs in the MV
stage to configure a bipolar MVDC interface, and interleaved grid can provide more flexibility and resilience for loads and
converters combined with a dual-transformer are designed in distributed generation (DG) due to the two different voltage
the LV stage to configure the bipolar LVDC interface and to levels and maintain operation under a line fault [1]. A high-
provide a self-balancing capability. Equivalent circuits of two power DC-DC converter is a key equipment to realize voltage
series-connected MMCs and a dual-transformer with interleaved
converters are derived. After that, operation principles of the
conversion, power transfer and electrical isolation for MVDC
proposed BiMMDC are introduced, considering balanced/ unbal- and LVDC distribution systems [2].
anced power transfer of bipolar LVDC grid and monopolar short-
circuit or open-circuit faults at MVDC grid. The control scheme Voltage
is also presented for the proposed BiMMDC under different balancer Wind Electric vehicle
DC AC DC
operating conditions. Finally, a Matlab simulation and controller
hardware-in-the-loop (CHIL) evaluation results are provided to DC DC DC
validate the feasibility and effectiveness of the proposed typology P p
DC +750V
and its operating performance. ±10kV g 0
MVDC −750V
Index Terms—Bipolar, DC-DC converter, equivalent circuit, N DC n LVDC
modular, monopolar operation, multilevel, self-balancing. DC DC DC
DC DC DC
PV DC load Energy storage

Fig. 1. Architecture of the bipolar MVDC and LVDC grids with DC-DC
I. I NTRODUCTION converter.

M EDIUM voltage DC (MVDC) and low-voltage DC

(LVDC) distribution grids provide promising solutions
for the integration of distributed renewable-energy generation
For an isolated bipolar DC-DC converter, a dual-active-
bridge (DAB) DC-DC converter with a series connection of the
and reliable power supply. Similar to a three-phase AC distri- so-called voltage balancer (VB) VB-DAB was proposed in [3].
bution grid, a DC distribution grid with a bipolar configuration This VB-DAB structure consists of two power conversion
is preferred [1]–[5], because many end-users and industrial stages. The authors in [5] proposed a triple-active-bridge
(TAB) DC-DC converter to configure a bipolar system with
Manuscript received August 8, 2022; revised October 13, 2022; accepted two H-bridges. The TAB approach realizes the desired bipolar
October 24, 2022. Date of online publication December 9, 2022; date of
current version December 13, 2022. This work was supported in part by the
system without a VB. However, it raises concerns about the
National Natural Science Foundation of China (No. 51877089). coupling effect among three H-bridges and control complexity.
J. M. Lai, and Y. Q. Wang are with the School of Electrical, and Information Besides, a simple and popular way for a bipolar DC system
Engineering, Zhengzhou University, Zhengzhou 450001, China.
X. Yin (corresponding author, email: [email protected]; ORCID:
is to connect a buck-boost based VB to the output of the
0000-0001-6637-0643) and L. Jiang are with the Department of Electrical isolated bipolar DC-DC converter [10]–[12]. However, the
Engineering, and Electronics, University of Liverpool, Liverpool, UK. aforementioned approaches in [3]–[5], [10]–[12] are incapable
X. G. Yin, and Z. Ullah are with the State Key Laboratory of Advanced
Electromagnetic Engineering, and Technology, Huazhong University of Sci- of transferring large power and realizing high voltage ratio
ence, and Technology, Wuhan 430074, China. for the interconnection of MVDC and LVDC grids, such as
DOI: 10.17775/CSEEJPES.2022.05460 ±10 kV MVDC and ±750 V LVDC grids, which is only
2096-0042 © 2022 CSEE
366 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 9, NO. 1, JANUARY 2023

suitable for LVDC grid scenario. In addition, these approaches poles caused by an asymmetric load or DG uncertainties,
are not able to handle line disconnection and pole-to-ground which may result in an insulation issue at the LVDC
short-circuit faults at the MVDC grid, as shown in Fig. 1. side and a DC saturation problem of AC line-frequency
At present, there are two types of DC-DC converters transformer at AC side of the MVDC station.
which are suitable for interconnection of MVDC and LVDC • Monopolar operation of conventional MMDC and ISOP-
grids, i.e., input series output parallel dual active bridge DAB cannot ensure an uninterrupted power supply for
(ISOP-DAB) [13] and modular multilevel DC-DC converter LVDC loads when a single line disconnection or pole-to-
(MMDC) [14]. ISOP-DAB topology has the advantages of ground short-circuit fault occurs at the MVDC grid.
bidirectional power transmission, high efficiency and high- Until now, there has been no solution to configure a bipolar
power density [15]. However, there are problems such as MMDC with self-balancing and fault ride-through capability.
centralized capacitors at MVDC bus, difficulty in fault-tolerant To fill this gap, we contribute to overcoming these research
control and insulation design of DAB modules [16]. For challenges discussed previously with purposes to 1) obtain
this reason, references [17] and [18] proposed an improved bipolar MVDC and LVDC ports; 2) achieve self-balancing
switched-capacitor-based ISOP-DAB topology, which over- capability; 3) secure LVDC loads when MVDC grid has a
comes the disadvantage of a centralized DC capacitor in the pole-to-ground short-circuit fault. Therefore, the main contri-
middle voltage side and achieves matched phase shifting. butions are summarized as follows.
This topology raises additional hardware circuits and control • A novel isolated bipolar modular multilevel DC-DC
complexity. The MMDC topology combines the advantages converter (BiMMDC) is proposed for supporting the
of modular multilevel converter (MMC) and DAB, which interconnection of MVDC and LVDC grids. Compared
eliminates the centralized capacitor on the MVDC bus, with with conventional MMDC and ISOP-DAB, our proposed
the advantages of modular design, easy voltage expansion, BiMMDC with the design of bipolar MVDC and LVDC
fault isolation, and so on [14], [19]–[21]. However, rare ports can achieve self-balancing capability and fault ride-
work has been carried out to configure an inherent bipolar through ability.
operation and fault ride-through capability for MMDC or • The operation principle of the proposed BiMMDC is
ISOP-DAB typologies. A conventional MMDC is only capable analyzed by considering the balanced and unbalanced
of monopolar operation. For this purpose, the authors in [22], power transfer of the bipolar LVDC, as well as the
[23] presented two series-connected MMC converters in the monopolar short-circuit fault at the MVDC grid. Besides,
MV stage to configure a bipolar MVDC interface. A Scott with a developed operation principle, two feedback loops
transformer connection is used in a medium-frequency stage control strategy for the proposed BiMMDC is designed to
to achieve galvanic isolation and voltage matching. In [24], enhance operating performance under unbalanced loads
a six-step MMC-based DC-DC converter was proposed. The and grid fault conditions.
MMDC is extended to a three-phase structure, where two • Simulation and CHIL evaluation results are carried out
MMCs are connected in series to configure a bipolar MVDC to verify the feasibility and effectiveness of the proposed
interface in the MV stage. However, the bipolar structure typology and its self-balancing and fault ride-through
on the LVDC side was not considered in [22]–[24]. As an operating performance.
alternative solution, a modified MMDC in [25] designed for
bipolar operation capability provided a simplified structure
II. T HE P ROPOSED T YPOLOGY AND M ODELING
with a center-tap transformer. Two concentrated capacitors
are used to construct a neutral point at the MVDC side. A. The Proposed Typology
In this case, the MMDC cannot fully disconnect from the Figure 2 shows the proposed isolated bipolar modular
MVDC grid. Therefore, this type of MMDC converter lacks multilevel DC-DC converter. The proposed BiMMDC consists
DC FRT capability and injects uncontrollable fault current due of two series connected MMCs in the MV stage to configure
to the terminal capacitors when a monopolar DC fault occurs. a bipolar MVDC interface, i.e., positive pole (p) and negative
Similarly, the bipolar structure on the LVDC side was also not pole (n). The interleaved converters are designed in the LV
considered in [25]. stage to configure a bipolar LVDC interface and to provide
In summary, it is important to mention that several chal- a self-balancing capability. The MV and LV positive/negative
lenges for conventional MMDC or ISOP-DAB typologies are poles of the proposed BiMMDC are coupled with two series-
needed to be solved as follows: connected medium-frequency transformers to realize a decou-
• A conventional MMDC is hard to configure as a bipolar pling power control. The positive (negative) pole converters
LVDC port due to its symmetric structure and operation and the interleaved converters are designed in series with
principle. two series transformers. In the MVDC application scenario,
• A conventional ISOP-DAB needs a concentrated capac- two series connected MMCs are used on the MV stage, and
itor at the MVDC side, which is hard to configure as four full-bridge converters are used on the LV stage of the
a bipolar MVDC port. Besides, the insulation level of BiMMDC. In order to access the MVDC grid, both MMCs of
all transformers of ISOP-DAB submodules should be positive and negative poles can use half-bridge (HB) or full-
designed considering the worst case. bridge (FB) sub-modules (SMs). The number of SMs in each
• Bipolar MVDC/LVDC interfaces need to overcome the arm depends on the voltage level of the MVDC grid and the
voltage/power imbalance between positive and negative capacitor rated voltage of the SM. The coupled arm inductor is
LAI et al.: ISOLATED BIPOLAR MODULAR MULTILEVEL DC-DC CONVERTER WITH SELF-BALANCING CAPABILITY FOR INTERCONNECTION OF MVDC AND LVDC GRIDS 367

P Positive Pole B. Modeling of the Proposed BiMMDC

IMVp FB1 ILVp
+ SM1 + SM1 p
+ In Fig. 2, VMV is the voltage of MVDC grid; IMVp and
IMVn are the positive and negative pole currents of the
Ă
vpau vpbu

Ă
n :1
+ T
SMN SMN vsp1* * VLVp BiMMDC at MVDC port, respectively; VLVp and VLVn are
− −
* Larm * L iLp − is the positive and negative pole voltages of LVDC grid; ILVp
arm
M ipau ipa M ipbu vLp and ILVn are the positive and negative pole currents of the
VMV + −
a b ipb L vpcd BiMMDC at LVDC port, respectively; vpau , vpal , vpbu , vpbl
2 ipal vpab ipbl − and vnau , vnal , vnbu , vnbl are the output voltages of the a-
*L *
arm L arm phase and b-phase upper and lower arm at MMC positive and
+ +
SM1 + SM1 vsp2* * negative poles, respectively; ipau , ipal , ipbu , ipbl and inau ,
− n :1
v v T inal , inbu , inbl are the arm currents of the a-phase and b-
Ă

pal pbl

SMN SMN
phase upper and lower arm at MMC positive and negative
− − FB2 poles, respectively; vpab and vnab are the differential voltages
G Interleaved converter produced by upper and lower arms at positive and negative
g
+ +
FB3 poles, respectively; vpcd and vncd are the total secondary-
SM1 SM1
side voltages produced by two series transformers at positive
vnau vnbu
Ă

+ nT :1
and negative poles, respectively; Larm and M are the self-
SMN SMN * *
vsn1 inductance and mutual inductance of the coupled inductors; L
− − −
* Larm * L iLn is the lump inductance of the series inductor and the leakage
arm
M inau i Mi v inductance of two transformers; nT : 1 is the turn ratio of
na nbu + Ln−
VMV +
a v b inb L vncd medium-frequency transformer. Four FB converters at the LV
inal nab − +
2 inbl stage are marked as FB1 , FB2 , FB3 and FB4 , respectively.
*L *L
arm arm
+ Reference directions of the corresponding terminals and vari-
+ + vsn2* * VLVn
SM1 SM1 ables are shown in Fig. 2.
−
vnal vnbl nT:1
Due to the symmetry of the proposed BiMMDC typology,
Ă

ILVn
IMVn − SMN SMN − the modeling of the BiMMDC is investigated at the positive
−
FB4 n pole. The same modeling technique can be applied to the
Negative Pole
N
negative pole of the BiMMDC converter.
Fig. 2. The proposed isolated, bipolar, modular, multilevel DC-DC converter Figure 3(a) provides the equivalent circuit of the proposed
with self-balancing capability. BiMMDC at the positive pole where the arms were replaced
with the ideal voltage source. According to the MMC oper-
ation principles, each arm voltage contains a common-mode
used to balance the AC component in the upper and lower arm
DC component and a differential-mode AC component, for
currents. It is noted that single-phase or three-phase topology
example, vpau = vpau,ac +vpau,dc . Besides, the MVDC current
can be used for the MMC at the MV stage. In terms of power
IMVp is equally distributed between a-leg and b-leg, and the
transfer features, single-phase and three-phase configurations
AC current ipa and ipb are also equally distributed between
of the proposed BiMMDC have similar operating principles.
upper and lower arms at the positive pole. Therefore, the arm
Therefore, a single-phase BiMMDC is studied in this paper.
current of j-phase leg (j = a, b) can be expressed as follows.
Features of the proposed BiMMDC are presented as follows.
(
1) Under unbalanced power at a bipolar LVDC port, power ipju = ipcomj + pj
i IMVp i
+ pj
2 = 2 2 leads to:
sharing between a positive and negative pole on the MV stage ipj IMVp ipj
ipjl = ipcomj − 2 = 2 − 2
can be auto-balanced with interleaved converters and self- (
ipju +ipjl
balancing capability, which guarantees balanced positive and 2 = ipcomj
(1)
negative pole currents of the BiMMDC at the MVDC port, ipju − ipjl = ipj
i.e., IMVp = IMVn .
2) Uninterrupted power supply to the bipolar LVDC can be where ipcomj and ipj are the common mode current and the
achieved under monopolar fault at the MVDC grid. Converters differential mode current of j-phase leg at the positive pole.
at the MV and LV stages connected to the faulty pole gets Applying Kirchhoff’s voltage law (KVL) to the MV stage
isolated from the BiMMDC; therefore, the proposed BiMMDC of the BiMMDC positive pole, one can attain
operates with half the rated power. V dipau dipal
2 = vpau + Larm dt + M dt + vpal
MV
3) Compared to a multi-winding transformer scheme, power 

 dipal dipau
transfer between MV and LV stages is decoupled by using
 + Larm dt + M dt
VMV dipbu dipbl (2)
two series transformers with small computational efforts. Be- 
 2 = vpbu + Larm dt + M dt + vpbl
dipbl dipbu

sides, the insulation voltage and power capacity of the se- 
+ Larm dt + M dt
ries medium-frequency transformers are significantly reduced,
which is only one-quarter of a multi-winding transformer. Applying the KVL to the upper and lower loops of the
Therefore, it simplifies transformer design. BiMMDC positive pole at the MV stage, one can attain
368 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 9, NO. 1, JANUARY 2023

IMVp IMVp IMVp IMVp

vpau,ac vpau,ac vpbu,ac
vpau vpbu 2 2
nT:1 nT:1
vpau,dc vpau,dc vpbu,dc
* * vLVp * * vLVp
* Larm * Larm iLp Larm+M Larm+M Larm−M
VMV M ipau ipa M ipbu vLp + VMV
ipa vLp iLp
+
2 a v b ipb L vpcd 2 L vpcd
ipal pab i − −
* * pbl
Larm Larm Larm+M Larm+M Larm−M
* * vLVn * * vLVn
nT:1 v pal,ac v pbl,ac nT:1
vpal vpbl vpal,dc vpbl,dc

(a) (b) (c)

Fig. 3. Equivalent circuits of the proposed BiMMDC at positive pole: (a) Total equivalent circuit; (b) Common-mode equivalent circuit; (c) Differential-mode
equivalent circuit.

dipbu dipbl dipa



 vpab = vpbu + Larm dt + M dt − vpau = Leq + nT (vLVp + vLVn ) (7)

 dipau
− Larm dt − M dt
dipal dt
(3) The equivalent circuit of the AC stage can be derived
 vpab = vpal + Larm didtpal + M didtpau
− vpbl
according to (7), as shown in Fig. 4. Magnitude and direction

dipbl dipbu

− Larm dt − M dt

of the transfer power can be regulated by controlling the
Substituting (1) into (2) and (3), yields (4) and (5). magnitude and phase shift angle between the AC component of
the injected arm voltage and the secondary-side square voltage
(
VMV dipcoma di
2 = vpau + vpal + 2Larm dt + 2M pcoma
dt
VMV dipcomb dipcomb (4) vpcd . Besides, by using two series transformers, BiMMDC can
2 = vpbu + vpbl + 2L arm dt + 2M dt eliminate magnetic coupling between two primary windings.
vpbu − vpau vpal − vpbl dipa Since there is no magnetic coupling, useless circulating power
vpab = + − (Larm − M ) (5)
2 2 | {z } dt between two primary windings can be avoided.
Lδ
Equation (5) can be further simplified in case the adjacent iLp Leq
MMC legs work in a complementary manner, i.e., vpau = vpbl ,
ğφ1
vpal = vpbu . Eq. (5) can be rewritten as in (6). nTvLVp
dipa dipa vpal−vpau ğφ2 + vpcd
vpab = vpal − vpau − Lδ = vpbu − vpbl − Lδ (6) nTvLVn
dt dt
It is noted that the leakage inductance of the coupled
inductor (Lδ = Larm − M ) can be treated as an inductor in
Fig. 4. Equivalent circuits of the AC stage for the BiMMDC at positive
series with the leakage inductance L of the transformer at the pole.
primary side, and the sum of leakage inductance of the coupled
inductor and the transformer is denoted as Leq = Lδ + L. On summary, (4), (6) and (7) are the general mathematical
According to (4) and (6), the common-mode and model for the proposed BiMMDC at the positive pole. This
differential-mode equivalent circuits of the proposed BiM- model is independent of the modulation strategy. In other
MDC for the positive pole are depicted in Fig. 3(b) and (c). words, it applies to all modulations, such as square wave,
Under steady operation of the primary side of BiMMDC, quasi-square wave, and sinusoidal wave modulations.
the MVDC grid charges the SMs cluster through a common-
mode circuit. Because the upper and lower arms are com-
plementary, the SMs in the upper and lower arm absorb the III. O PERATION P RINCIPLES
same power from the MVDC grid in each switching cycle. Considering power transfer capacity, efficiency and current
A differential-mode circuit provides energy from the SMs stress performance, quasi-square wave modulation [26] is
cluster to the LVDC grid. Power exchange between the SMs utilized in the following analysis. Besides, a single-phase shift
cluster and the LVDC side is realized through the interaction (SPS) is employed in this paper for simplification.
of the AC component of the injected quasi-square arm voltage Figure 5 shows the MV stage quasi-square wave modulation
vpab , the differential-mode current ipa and the secondary diagram of the proposed BiMMDC at the positive pole. Taking
side square voltage vpcd . Owing to series connection, the the upper and lower arms of a-leg as an example, Spauk
total secondary-side AC voltage vpcd can be expressed as represents the driving signal of the k-th SM in the upper arm
vpcd = nT (vLVp + vLVn ). Consequently, seen from the AC of a-leg, k = 1, 2, · · · , N . Without considering dead time,
stage, the following equation can be obtained based on Eq. the driving signals of the upper and lower arms are com-
(6) and Fig. 2. plementary, and the duty cycle is 50%. Spauk = 1 indicates
dipa the k-th SM of the arm on a-leg is inserted, and Spauk = 0
vpal − vpau = vpbu − vpbl = Leq + vpcd indicates that the k-th SM is bypassed. A small phase delay
dt
LAI et al.: ISOLATED BIPOLAR MODULAR MULTILEVEL DC-DC CONVERTER WITH SELF-BALANCING CAPABILITY FOR INTERCONNECTION OF MVDC AND LVDC GRIDS 369

dθThf AC p
Spau1 1 P DC PLVp1
θ 0 PMVp DC
Spau2 1 PLVp
0 AC
Ă PLVp2

Ă
1 AC
SpauN 0 DC
g
t AC
(N−1)dθThf G DC PLVn1
Spal1 0 1 DC
PMVn PLVn
Spal2 0 1 AC
PLVn2

Ă
1
Ă

0 AC DC n
SpalN N
t MV stage LV stage
0.5VMV upal (upau)
Fig. 6. Power transfer under balanced power operation of bipolar LVDC
0 (PLVp = PLVn > 0).
t
0.5VMV
vpau (vpbl) vpab vpcd
0.5VMV
0
Thf =Ts/2 t 0
0.5VMV dφThf t
−0.5VMV
nTvLVp
0 0.25VMV
t
0
vpab=vpal − vpau −0.25VMV t
−0.5VMV nTvLVn
0.25VMV
0
Fig. 5. Quasi-square Modulation of BiMMDC at positive pole. −0.25VMV t

vLp=vpab−vpcd
θ between the driving signals of adjacent SMs of the same
arm is added to change the rate (dv/dt) of output voltage of 0
t
each arm; besides, SMs voltage balance control in the same
arm can be realized by a sorting method. Therefore, the ratio iLp
of this phase delay θ to π is defined as dθ (0 < dθ < 1/N ).
According to the MMC principle, the upper and lower arms 0
t
work complementarily in each phase. The upper arm inserts
q (q = 0, 1, · · · , N ) SMs, and the lower arm will bypass t1 t2tm−1 tm tN−1 tN tN+1 tN+2 t2N+1 t2N+2 t2N+3
(N − q) SMs to ensure the sum of the inserted SMs of the
Fig. 7. Waveforms of BiMMDC at operation Mode 1 under balanced power
upper and lower arms in one leg is N at any time. As shown in transfer condition (PLVp = PLVn > 0).
Fig. 5, it can be observed that output voltages of the upper and
lower arms vpau and vpal are quasi-square waves with (N +1)
level. It should be noted the number k represents the driving shown in Fig. 7. The phase shift angle φ is defined in Fig. 7,
signal of the k-th SM after the voltage balance algorithm. and the ratio of the phase shift angle φ to π is dφ (−1+dθ /2 ≤
Magnitude and direction of the transfer power between the dφ ≤ 1 + dθ /2). In addition, the voltage matching ratio of the
MVDC and LVDC sides are adjusted by controlling the phase converter is defined as K = (VMV /2)/(nT VLVp + nT VLVn ) =
shift angles φ1 and φ2 between the primary side AC voltage (VMV /2)/(nT VLV ). Normally, the transformer turns ratio nT
vpab and the secondary side voltage vLVp1 and vLVp2 . The is designed to satisfy K = 1.
phase shift angles φ1 and φ2 are determined by the transfer According to the phase shift angles φ and θ, working modes
power of the LVDC positive- and negative-polar (PLVp and of the proposed BiMMDC in one cycle can be divided into
PLVn ). Here, discussions on the operation principle under following four modes: Mode 1 (N dθ /2 ≤ dφ ≤ 1 − (N/2
balanced (PLVp = PLVn ) and unbalanced (PLVp ̸= PLVn ) −1)dθ ), Mode 2 (−(N/2 − 1)dθ < dφ < N dθ /2), Mode 3
power transfer of bipolar LVDC are given with an assumption (−1+N dθ /2 ≤ dφ < −(N/2−1)dθ ), Mode 4 (−1−(N/2−1)
that the positive and negative pole voltages of LVDC are well dθ ≤ dφ < −1 + N dθ /2). Transfer power at Mode 1 flows
balanced, i.e., VLVp = VLVn = 0.5VLV . from the MVDC side to the LVDC side (forward direction),
and transfer power at Mode 3 flows from the LVDC side to
A. Balanced Power Transfer of Bipolar LVDC the MVDC side (reverse direction). Mode 2 can be divided
Figure 6 shows the power transfer of BiMMDC under into two types of transfer power, which are light-load forward
balanced power operation of bipolar LVDC, i.e., PLVp = transfer (dθ /2 < dφ < N dθ /2) and light-load reverse transfer
PLVn . With a balanced power operation of bipolar LVDC, (−(N/2−1) dθ < dφ < dθ /2), respectively. Mode 4 is similar
the phase shift angles φ1 and φ2 will be identical. Then, to Mode 2. Each mode has N + 1 switching states in half
the secondary-side AC voltage vpcd is a two-level square switching cycle.
waveform. Therefore, the theoretical waveform of vpab , vpcd , Taking Mode 1 (N dθ /2 ≤ dφ ≤ 1 − (N/2 − 1)dθ ) as an
nT vLVp1 , nT vLVp2 and primary side inductor current iLp is example, as shown in Fig. 7, primary side inductor current
370 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 9, NO. 1, JANUARY 2023

iLp can be obtained by the voltage drop on the equivalent is zero when dφ = 0.5dθ and the characteristics of forward and
inductor Leq between vpab and vpcd . Then, the transfer power reverse transfer power are symmetrical about dφ = 0.5+0.5dθ
at MVDC positive pole PMVp can be obtained by piecewise and dφ = −0.5 + 0.5dθ . Moreover, with an increase of SM
linear calculation [27]. Define the transfer power base value phase shift ratio dθ , the maximum transfer power Pmax of
as Pb = (VMV /2)2 /(8f Leq ). Using a piecewise calculation the BiMMDC converter will decrease. The power transfer
∗
method, transfer power PMVp of the BiIMMDC positive pole characteristic of the BiMMDC is similar to the operation of
in Mode 1–3 can be expressed as (8). DAB. Therefore, considering the transfer power capacity of the
 h 
N2
 i BiMMDC and the voltage change rate dv/dt at the primary
2 2 1 1


 4K −d φ − d θ 6 + 12 + dφ − 2 d θ + dφ d θ , side of the transformer, the dθ should not be set too large.

N N


2 dθ ≤ dφ ≤ 1 − 2 − 1 dθ Finally, under balanced power transfer of bipolar LVDC,




the transfer power in four H-bridges at the LV stage can be


2l
dφ − 12 d2θ

2



 4K dφ + 1 − N derived as follows.
 h

 2

2l2 i



 − 1 + l 2 − N − N dφ dθ PLVp1 = PLVp2 = PLVn1 = PLVn2 = 0.5PMVp = 0.5PMVn
 
∗
PMVp = +d2θ 61 + l2 1 − N1 + l 1 − 3N

1
− N2

(10)


B. Unbalanced Power Transfer of Bipolar LVDC (PLVp >

 
 2l3 N2



 − 3N + 12 , l = 1, 2, · · · , N − 1, PLVn )


(l −h1)dθ ≤ dφ + N2 −


1 dθ ≤ ldθ



  i Under unbalanced bipolar loads at the LVDC port, phase
N2


 4K d 2
+ d 2 1
+ + d φ − 1
d θ − dφ d θ , shift angles φ1 and φ2 are no longer identical. Then, the

 φ θ 6 12 2

N
 N

secondary-side AC voltage vpcd is a three-level square wave-
2 dθ − 1 ≤ dφ ≤ − 2 − 1 dθ form. According to phase shift angles φ1 , φ2 and θ, the
(8) working modes of the proposed BiMMDC in one cycle are
From (8), it can be seen the transfer power of BiMMDC more complicated than of balanced load operating conditions.
is related to the voltage matching ratio K, the phase shift In order to simplify the analysis process, it is reasonable
ratio dφ , the SM phase shift ratio dθ , and the number SMs to neglect phase shift angle θ, because the power transfer
N in one arm. For BiMMDC applied in ±10 kV MVDC characteristic of BiMMDC is similar to DAB [19] when the
grid, if the capacitor voltage of each SM is designed to be dθ is chosen as a small one, for example, dθ = 0.02 as shown
1 kV, each arm requires ten SMs, namely N = 10. Maximum in Fig. 8.
forward transfer power of BiMMDC is in Mode 1, and the
corresponding phase shift ratio is (dφ )F,Pmax . Similarly, the AC p
P DC PLVp1
maximum reverse transfer power of BiMMDC is in Mode 3, DC
PMVp PLVp
and the corresponding phase shift ratio is (dφ )B,Pmax . The AC
PLVp2
maximum phase shift ratio dφ can be obtained in (9). AC DC
g
AC
 1 dθ G DC PLVn1
 (dφ )F,Pmax = +
 DC
2 2 PMVn PLVn
(9) AC
PLVn2
 1 dθ AC n
 (d )
φ B,Pmax = − + N
DC
2 2 MV stage LV stage
Figure 8 shows the power transfer characteristic of the
Fig. 9. Power transfer under unbalanced power operation of bipolar LVDC
BiMMDC positive pole when the submodule N = 10 is in one (PLVp > PLVn > 0).
arm. It is observed that, when dφ ∈ [−0.5+0.5dθ , 0.5+0.5dθ ],
the transfer power PMVp of the BiMMDC converter has a
When the unbalanced bipolar load (PLVp > PLVn > 0)
monotonic relationship with dφ . Besides, the transfer power
occurs at the LVDC port, a phase shift angle should satisfy
φ1 > 0 > φ2 . Since the secondary side voltage vpcd is
1.5
dθ=0,0.02,0.06,0.1 synthesized by nT vLVp1 and nT vLVn1 , the phase shift angle
1 φ between vpab and vpcd can be expressed as (11).
0.5 1
φ= (φ1 + φ2 ) (11)
P*MVp

0 2
−0.5 Transfer powers at MVDC positive pole (PMVp ) and two
−1 FBs (PLVp1 and PLVn1 ) can be obtained by piecewise linear
calculation with
−1.5
−1.5 −1 −0.5 0 0.5 1 
1
R t4
dφ  PMVp = Thf Rt1 vpab iLp (t)dt

t
PLVp1 = T1hf t14 nT vLVp iLp (t)dt (12)
Fig. 8. Power transfer characteristic of the BiMMDC positive pole under  1
R t4
PLVn1 = Thf t1 nT vLVn iLp (t)dt

different dθ value with N = 10 and K = 1.
LAI et al.: ISOLATED BIPOLAR MODULAR MULTILEVEL DC-DC CONVERTER WITH SELF-BALANCING CAPABILITY FOR INTERCONNECTION OF MVDC AND LVDC GRIDS 371

vpab P
0.5VMV AC p
vpcd DC
DC
0
dφThf t AC
0.5(dφ1+dφ2)Thf PLVp2=PLVp
−0.5VMV AC DC
(dφ1−dφ2)Thf nTvLVp g
0.25VMV AC
dφ1Thf G DC
0 DC
−0.25VMV t PMVn
dφ2Thf nTvLVn
0.25VMV AC PLVn2=PLVn
0 t AC DC n
−0.25VMV N
MV stage LV stage
0.5VMV
vLp =vpab−vpcd
0 Fig. 11. Power transfer under monopolar short-circuit fault at MVDC grid.
t
−0.5VMV
iLp blocking the gate signal to avoid an overcurrent effect, and
the DC current at the fault pole decreases to zero quickly,
0
t as seen in the solid red line in Fig. 11. Due to interleaved
t1 t2 t3 t4 t5 t6 t7 converters, the positive pole load at LVDC grid can transfer
to the non-fault pole MV stage, as seen in the solid blue line in
Fig. 10. Waveforms of BiMMDC under unbalanced power transfer condition Fig. 11. Therefore, the non-fault pole converter is not affected
(PLVp > PLVn > 0). by the faulted pole and can still maintain and balance bipolar
voltage at LVDC side by power supplied through the blue
where iLp can be obtained by the voltage drop on the equiva- solid line loop using phase shift control. Once the DC voltage
lent inductor Leq between vpab and vpcd . Here, PMVp , PLVp1 has been restored at MVDC, the blocked pole can be easily
and PLVn1 can be deduced as follows. switched back to normal operation state because the voltage at
2 LVDC always operates in nominal value. Besides, transformers
VMV
PMVp = (1 − dφ1 + dφ2 ) (dφ1 + dφ2 ) (13) at the non-fault pole are not saturated by the short-circuit fault
16Leq f pole because asymmetrical operation at the MV stage does not
2
 
VMV 1 induce saturation of the transformer since there is no DC offset
PLVp1 = −dφ1 dφ2 + (1 − dφ1 + dφ2 ) (dφ1 + dφ2 )
16Leq f 2 current flowing through the transformer.
(14)
2
 
VMV 1 IV. C ONTROL S CHEME
PLVn1 = dφ1 dφ2 + (1 − dφ1 + dφ2 ) (dφ1 + dφ2 )
16Leq f 2 As discussed in the previous section, power flow character-
(15)
ization can be summarized as follows:
From (13)–(15), the relationship among PMVp , PLVp1 and 1) Interleaved converters (FB2 and FB3 ) always transfer
PLVn1 can be confirmed as half power of the corresponding poles at the LVDC grid
under non-fault operation conditions. The power distribution
PMVp = PLVp1 + PLVn1 (16)
relationship for the four FB converters at the LV stage can be
Therefore, it is concluded that power distribution between obtained as
PLVp1 and PLVn1 is determined by the phase shift angle ratio 1 1
PLVp1 = PLVp2 = PLVp , PLVn1 = PLVn2 = PLVn (17)
dφ1 and dφ2 , and the sum of PLVp1 and PLVn1 also meets 2 2
power conservation, which proves the validity of the above 2) Two series connected MMCs always transfer half power
analysis. The same analysis can be applied to the negative of the bipolar at the LVDC grid under non-fault operation
pole of the BiMMDC. condition. The power distribution relationship for the two
MMCs at the MV stage can be obtained as
C. Monopolar Short-circuit Fault at MVDC Grid 
When a monopolar short-circuit fault occurs at a MVDC  PMVp = PLVp1 + PLVn1

grid, the conventional monopolar MMDC converter fails to PMVn = PLVp2 + PLVn2 (18)
achieve fault ride-through. Conventional monopolar MMDC 1

PMVp = PMVn = 2 (PLVp + PLVn )

has to be blocked to cut the fault current and isolate the fault,
which results in interrupting the power supply to the LVDC 3) Under monopolar short-circuit fault at the MVDC grid,
grid. This is because conventional MMDCs operate with a fault-pole converters are blocked and all power of the LVDC
single closed circuit, so the entire MMDC circuit is affected grid is transferred by non-fault pole converters. Take positive
by the monopolar fault. In contrast, the proposed BiMMDC pole fault at MVDC as an example; the power distribution re-
has two independent closed circuits at both MV and LV stages lationship for the two MMCs and four FBs can be obtained as

with two series MMCs and interleaved converters.
 PMVp = 0, PLVp1 = 0, PLVn1 = 0

Figure 11 shows a power transfer schematic under monopo- (19)
PLVp2 = PLVp , PLVn2 = PLVn
lar short-circuit fault at the MVDC grid. When a DC fault 
PMVn = PLVp + PLVn

occurs at MVDC, the fault-pole BiMMDC is disabled by
372 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 9, NO. 1, JANUARY 2023

It is observed from (17) and (18) that FB1 and FB3 always TABLE I
S IMULATION PARAMETERS OF B I MMDC
transfer half power of the positive pole load, and FB2 and
FB4 always transfer half power of the negative pole load. In Parameter Value Parameter Value
other words, FB1 and FB3 can be assigned the same phase VMV (kV) ±10 Larm (mH) 1
VLV (V) ±750 M (mH) 0.99
shift angle φ1 ; FB2 and FB4 can be assigned the same phase PLVP , PLVn (MW) 1 L (mH) 0.5
shift angle φ2 . Owing to the nature of the auto-distribution N 5 nT 5000:750
of unbalanced bipolar loads among four FBs at the LV stage, V sm (V) 2000 f (kHz) 10
C sm (µF) 500 CLVp , CLVn (µF) 20000
only two control loops are employed in order to control the
positive and negative pole voltage of the LVDC port, which
can simplify the control scheme.
of the LVDC grid are connected with balanced loads of
Figure 12 presents the control block diagram of the pro-
PLVp = PLVn = 500 kW. At t = 0.3 s, the load at the
posed BiMMDC. Two feedback control loops are formed
positive pole of the LVDC is stepped from PLVp = 500 kW to
namely LVDC positive pole voltage control and negative pole
PLVp = 1000 kW, and it is shown the positive pole current of
voltage control loop. The positive and negative pole voltages
the LVDC port quickly increases to 1333 A, while the negative
at LVDC are measured and compared with the reference
pole current remains unchanged at 667 A. It can be observed
value. After that, each voltage error is regulated by the PI
from Fig. 13 that positive and negative pole currents at MVDC
controller to individually control bipolar voltage, whose output
always are identical under balanced or unbalanced bipolar
represents a desired phase shift angle φ1 and φ2 . Since only
LVDC loads, i.e., IMVp = IMVn . As shown in Fig. 13(b), the
two PI controllers are used without any complicated algo-
phase shift angles φ1 and φ2 are equal under balanced load,
rithms, control for the proposed BiMMDC is simple enough
and the primary side AC voltage vpab and the total secondary-
to be easily implemented in a digital signal processor. Under
side voltage vpcd produced by two series transformers is a
monopolar fault at the MVDC grid, only the corresponding
two-level square wave. As shown in Fig. 13(c), phase shift
fault-pole of the BiMMDC is disabled by blocking the gate
angles φ1 and φ2 are unequal due to unbalanced loads and the
signals, and two feedback control loops for the bipolar voltage
of LVDC remain unchanged. Control of internal quantities of total secondary-side voltage vpcd is a three-level square wave.
the two series connected MMCs at the MV stage, such as Besides, phase shift angle φ1 is larger than φ2 because the
SMs capacitor voltage, can be performed as if a conventional positive pole load is greater than the negative pole load. Fig. 14
MMDC is analyzed [14]. The phase shift angle of each SM shows the dynamic simulation results for the BiMMDC with-
in one arm is changed according to the sorting result of SM out considering interleaved converters at the LV stage under an
capacitor voltage. unbalanced load. Although LVDC voltage can be controlled at
its reference value, i.e., ±750 V, the unbalanced load results
in unequal positive and negative pole currents at MVDC, i.e.,
V. S IMULATION R ESULTS IMVp > IMVn , which may cause DC saturation for an AC line-
To verify the effectiveness of the proposed BiMMDC and frequency transformer at AC/DC MVDC station. Therefore, it
its operation scheme, a simulation evaluation is carried out is concluded the proposed BiMMDC can fully realize bipolar
on Matlab/Simulink. Detailed parameters of a BiMMDC con- MVDC and LVDC operation with a simple control scheme
verter are listed in Table I. Nominal voltage of the MVDC under balanced or unbalanced load conditions.
and LVDC grids for the test system are ±10 kV and ±750 V, Figure 15 shows simulation results when a positive-pole-
respectively. to-ground short circuit fault occurs at the MVDC grid with
Figure 13 presents dynamic simulation results for the pro- balanced LVDC loads of PLVp = PLVn = 500 kW. It is
posed BiMMDC. Initially, the positive and negative poles seen from Fig. 15 that, regardless of the monopolar fault,

quasi-square
50% duty cycle signal modulation and To MMC1 and MMC2
voltage balancing SMs driving signal

VLVp,ref dφ1
PI Phase shift To FB1 and FB3
+ modulation driving signal
−
VLVp
VLVn,ref dφ2
PI Phase shift To FB2 and FB4
+ modulation driving signal
−
VLVn

VMVp MVDC positive pole fault

Fault Blocking MMC1, FB1 and FB2
VMVn detection MVDC negaive pole fault
Blocking MMC2, FB3 and FB4

Fig. 12. Control block diagram of the proposed BiMMDC.

LAI et al.: ISOLATED BIPOLAR MODULAR MULTILEVEL DC-DC CONVERTER WITH SELF-BALANCING CAPABILITY FOR INTERCONNECTION OF MVDC AND LVDC GRIDS 373

IMVp (A) IMVn (A) IMVp (A) IMVn (A)

IMVp, IMVn (A)

VLVp, VLVn (V) IMVp, IMVn (A) 100 150
100
50
50
0 0
VLVp (V) VLVn (V) VLVp (V) VLVn (V)
800

VLVp, VLVn (V)

800

750 750

700 ILVp (A) ILVn (A) 700

ILVp (A) ILVn (A)
PLVp, PLVn (W) ILVp, ILVn (A)

1500

ILVp, ILVn (A)

1500
1000 1000
500 500
0 0
×105 PLVp (W) PLVn (W)
15 ×105 PLVp (W) PLVn (W)

PLVp, PLVn (W)

15
10
10
5
5
0
×104 vpab (V) 0
1.2 0.26 0.28 0.3 0.32 0.34 0.36 0.38
Time (s)
0.6
vpab (V)

0
Fig. 14. Dynamic simulation results for the BiMMDC without configuring
−0.6
the interleaved converters at LV stage.
−1.2
vpcd (V) vsp1 (V) vsp2 (V)
×104
vpcd, vsp1,2 (V)

1.2 VMVp (V) VMVn (V)

VMVp, VMVn (V)

0.6 15000
0 10000
−0.6 5000
−1.2 0
iLp (A)
−5000
240 IMVp (A) IMVn (A)
ILVp, ILVn (A) VLVp, VLVn (V) PMVp, PMVn (W) IMVp, IMVn (A)

150
iLp (A)

120
0 100
−120 50
−240 0
0.26 0.28 0.3 0.32 0.34 0.36 0.38
−50
Time (s) ×105 PMVp (W) PMVn (W)
(a) vpab (V) 15
×104
1.2 10
0.6
vpab (V)

5
0 0
−0.6 −5
−1.2 VLVp (V) VLVn (V)
×104 vpcd (V) vsp1 (V) vsp2 (V) 800
vpcd, vsp1,2 (V)

1.2
0.6 750
0
−0.6 700
−1.2 ILVp (A) ILVn (A)
iLp (A) 1000
240
120
iLp (A)

500
0
−120
0
−240 PLVp (W) PLVn (W)
50us/div 50us/div ×105
PLVp, PLVn (W)

10
(b) (c)
5
Fig. 13. Dynamic simulation results for the proposed BiMMDC under
balanced and unbalanced load conditions. (a) Dynamic performance of the
proposed BiMMDC; (b) Balanced load condition; (c) Unbalanced load con- 0
0.05 0.07 0.09 0.11 0.13 0.15
dition. Time (s)

the proposed BiMMDC converter can maintain the LVDC Fig. 15. Simulation results for the proposed BiMMDC when a positive-pole-
to-ground short circuit fault occurs at MVDC grid.
bipolar voltage at ±750 V due to its interleaved connection and
inherent bipolar feature. During the MVDC monopolar fault
process, the fault-side converter is blocked, and the non-fault- LVDC loads. Therefore, the proposed BiMMDC converter can
side BiMMDC can provide an uninterrupted power supply to guarantee high power supply reliability of the bipolar system.
374 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 9, NO. 1, JANUARY 2023

Negative ×105 PDG1 (W) PDG2 (W) PDG3 (W)

3

PDG1,2,3 (W)
23 24 25 DG2
2
26 27 28 29 30 31 32 33
1
0
Bipolar Positive −1
VLVp (V) VLVn (V)
DG1 DG3

IMVp, IMVn (A) PMVp, PMVn (W) ILVp, ILVn (A) PLVp, PLVn (W) VLVp, VLVn (V)
800
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Proposed
BiMMDC 750

700
19 20 21 22 ×105 PLVp (W) PLVn (W)
12

8
Fig. 16. Modified IEEE 33-bus test system.
4
ILVp (A) ILVn (A)
1500
We also tested the proposed BiMMDC on an IEEE 33-bus
system modified to be meshed bipolar DC microgrid [28], as 1000
shown in Fig. 16. Three 200 kW DGs are connected at buses
500
2, 6 and 30, respectively. The DGs are built based on average ×105 PMVp (W) PMVn (W)
10
models. Such a DGs model does not represent harmonics, but
the dynamics resulting from control system and power system 7.5
interaction are preserved. It is assumed that positive loads are
20% more than negative loads, and 200 kW bipolar loads are 5
IMVp (A) IMVn (A)
connected to buses 15, 22 and 32. Besides, the total load was 100
scaled down to 2 MW from the original value [29].
75
To verify adaptability to the imbalance caused by DG
uncertainties of the proposed solution, we set a power change 50
of three 200 kW DGs according to Table II. Fig. 17 shows 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
Time (s)
dynamic simulation results for the proposed BiMMDC with
a modified IEEE 33-bus test system under DGs uncertain- Fig. 17. Dynamic simulation results for the proposed BiMMDC with
ties conditions. It is seen from Fig. 17 that, regardless of modified IEEE 33-bus test system under DGs uncertainties conditions.
the DGs uncertainties, the proposed BiMMDC converter can
always maintain the LVDC bipolar voltage at ± 750 V due adopted for commissioning and testing of multilevel convert-
to its inherent bipolar feature with self-balancing capability. ers [30]–[34]. The proposed BiMMDC circuit was built in the
As shown in Fig. 17, the uncertainties of three DGs and RT-LAB OP5600 with a step of 20 µs. Control and modulation
unbalanced loads lead to a power imbalance of the positive- were implemented in DSP and FPGA, which are the same
and negative-pole of the LVDC port. It can be observed from as that of the experiment. RT-LAB communicates with DSP
Fig. 17 the proposed BiMMDC can always guarantee the through a fiber-based interface card. A simulation step of
same positive and negative pole currents at the MVDC port 20 µs is close to the operation limit of RT-LAB OP5600 [34].
under DGs uncertainties or unbalanced bipolar LVDC loads. Switching frequency is set to 1 kHz limited by admissible real-
Therefore, the results prove the proposed BiMMDC provides time simulation speed. Besides, RT-LAB has an interpolation
good adaptability to an imbalance caused by DG uncertainties. algorithm, which can improve simulation accuracy. It should
be noted that, due to the limited resources of OP5600 CPU
core (only one authorized CPU) and I/O channels (only 32
VI. CHIL E VALUATION R ESULTS
channels), each arm of the BiMMDC contains 2 SMs in
To further validate the proposed BiMMDC and its theoreti- the testbed. A schematic of the CHIL testbed is shown in
cal analysis, a controller hardware-in-the-loop setup based on Fig. 18(b). Five load resistors and three switches are employed
RT-LAB is conducted as shown in Fig. 18. System parameters to emulate a balanced/unbalanced load step change at the
are presented in Table III. CHIL simulators have been widely LVDC side and the open-circuit grid fault at the MVDC side.

TABLE II
P OWER C HANGE OF T HREE DG S

Power 0–0.1 s 0.1–0.15 s 0.15–0.2 s 0.2–0.25 s 0.25–0.3 s 0.3–0.35 s 0.35–0.4 s 0.4–0.45 s 0.45–0.5 s 0.5–0.55 s 0.55–0.6 s
Ramp up
PDG1 0 200 kW 200 kW 200 kW 200 kW 200 kW 200 kW 200 kW 200 kW 200 kW
to 200 kW
Ramp up Ramp down
PDG2 0 0 0 200 kW 200 kW 200 kW 0 0 0
to 200 kW to 200 kW
Ramp up Ramp down
PDG3 0 0 0 0 0 200 kW 200 kW 200 kW 0
to 200 kW to 0
LAI et al.: ISOLATED BIPOLAR MODULAR MULTILEVEL DC-DC CONVERTER WITH SELF-BALANCING CAPABILITY FOR INTERCONNECTION OF MVDC AND LVDC GRIDS 375

The resistor loads RL1 = RL2 = 40 Ω, and RL3 = 40 Ω.

Three cases are tested in this section. VLVp:100V/div

VLVn:100V/div

OP5600
ILVp:10A/div

DSP+FPGA
ILVn:10A/div

IMVp:5A/div
200 ms
IMVn:5A/div
DL950
vpab:400V/div
(a)
AC
S1 DC S2
DC S3 vpcd:400V/div
AC RL1 RL2
AC DC
RL3 vsp1:200V/div
AC
DC
DC RL1 RL2
AC vsp2:200V/div
AC DC
(b)
iLp:10A/div
Fig. 18. Photograph and schematic of the CHIL setup. (a) Photograph of
the CHIL setup. (b) Schematic diagram of the setup.

TABLE III dθThf

dφThf
CHIL PARAMETERS OF B I MMDC
dφThf
Parameter Value Parameter Value
VMV (kV) ±1.5 Larm (mH) 1
VLV (V) ±750 M (mH) 0.99
PLVP , PLVn (kW) 50 L (mH) 5
N 2 nT 750:750
V sm (V) 750 f (kHz) 1
C sm (µF) 1000 CLVp , CLVn (µF) 10000

1) Case 1: S1 and S2 are closed, then S3 suddenly closes

for varying balanced load with step-up conditions.
2) Case 2: S1, S2 are closed and S3 is opened, then S2
suddenly opens for varying unbalanced load with step-down
conditions. Fig. 19. Waveforms of the proposed BiMMDC for varying balanced load
3) Case3: S2 is closed and S3 is opened, then S1 suddenly conditions.
opens to emulate the open-circuit fault at the MVDC grid.
Figure 19 shows the waveforms of the proposed BiMMDC voltages are well-regulated to maintain voltage balancing.
for varying balanced load conditions. In case I, the BiMMDC Besides, it is seen that phase shift angles φ1 and φ2 are
is connected to a bipolar MVDC grid, and the BiMMDC identical under balanced load condition, and total secondary-
controls positive- and negative-pole LVDC voltages in a closed side voltage vpcd is two-level square wave. Therefore, the
loop manner. Initially, switches S1 and S2 are closed, and the proposed BiMMDC can maintain two pole voltages at their
system operates in a steady state. Then, the bipolar load RL3 is rated value and control two pole currents identically at the
turned on by closing switch S3. The dynamic performance is MVDC port both in steady and dynamic states.
shown in Fig. 19. It is observed that the positive- and negative- Figure 20 shows the waveforms of the proposed BiMMDC
pole output voltages are fixed at 750 V with feedback control, for varying unbalanced load conditions. In case II, S1 and S2
i.e., VLVp = VLVn = 750 V; and the positive- and negative- are closed, and S3 is opened initially, then S2 suddenly opens
pole currents at MVDC port IMVp and IMVn are controlled for varying unbalanced load with step-down conditions. Under
identically, i.e., IMVp = IMVn . When the switch S3 closes step-down positive-pole load changes, positive- and negative-
for varying balanced load, the total LVDC load changes from pole LVDC output voltages are well regulated to maintain
56 kW to about 112 kW. It is observed that the two output voltage balancing, i.e., VLVp = VLVn = 750 V. It is shown
376 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 9, NO. 1, JANUARY 2023

the positive pole current of the LVDC port quickly decreases proposed BiMMDC. The phase shift angles φ1 and φ2 are
while negative pole current remains unchanged. Similar to equal under balanced load and the primary side AC voltage
Matlab simulation results, it can be observed from Fig. 20 vpab and the total secondary-side voltage vpcd produced by
that positive and negative pole currents at MVDC are always two series transformers is a two-level square wave. Phase shift
identical under balanced or unbalanced bipolar LVDC loads, angles φ1 and φ2 change to unequal due to unbalanced loads
i.e., IMVp = IMVn . These results have proved the feature of and total secondary-side voltage vpcd is a three-level square
the self-balancing capability of the proposed BiMMDC due to wave. Besides, phase shift angle φ1 is smaller than φ2 because
the interleaved converters. Then, the proposed BiMMDC can the positive pole load is smaller than the negative pole load.
provide excellent adaptability to imbalanced conditions, which Therefore, it is concluded the proposed BiMMDC can fully
may be caused by unbalanced loads or DG uncertainties. Since realize bipolar MVDC and LVDC operation with a simple
positive and negative pole currents at the MVDC grid always control scheme under balanced or unbalanced load conditions.
keep equal under balanced and unbalanced load conditions, Figure 21 shows the waveforms of the proposed BiMMDC
no DC current would inject into AC system, and the DC under a positive-pole open-circuit fault at the MVDC grid. In
saturation problem of the AC line-frequency transformer at this case III, S2 is closed and S3 is opened, then S1 suddenly
the AC side of the MVDC station can be avoided with the opens to emulate open-circuit fault at the MVDC grid. Usually,

VLVp:100V/div VLVp:100V/div

VLVn:100V/div VLVn:100V/div

ILVp:10A/div ILVp:10A/div

ILVn:10A/div
ILVn:10A/div

IMVp:5A/div
IMVp:5A/div
positive pole open-circuit fault
200 ms
IMVn:5A/div
200 ms IMVn:5A/div
vpab:400V/div vpab:400V/div

vpcd:400V/div vpcd:400V/div

vsp1:200V/div vsp1:200V/div

vsp2:200V/div vsp2:200V/div

iLp:10A/div iLp:10A/div

dφThf dφThf dφThf

dφ1Thf

dφ2Thf

200 us 200 us

Fig. 20. Waveforms of the proposed BiMMDC for varying unbalanced load Fig. 21. Waveforms of the proposed BiMMDC under positive-pole open-
conditions. circuit fault at the MVDC grid.
LAI et al.: ISOLATED BIPOLAR MODULAR MULTILEVEL DC-DC CONVERTER WITH SELF-BALANCING CAPABILITY FOR INTERCONNECTION OF MVDC AND LVDC GRIDS 377

the following several situations can lead to open-circuit at the tralized capacitor on the MVDC bus. However, a conventional
MVDC grid: (1) a monopolar short-circuit grid fault occurs MMDC does not include MVDC and LVDC bipolar operation
and the DC breaker is triggered to cut off the fault; (2) a capability and an extension of the topology is necessary.
single line disconnection occurs; (3) a maintenance plan is Monopolar operation of a conventional MMDC cannot realize
carried out, then one pole of the BiMMDC has to be turned fault ride-through ability and ensure an uninterrupted power
off. It is seen from Fig. 21 the proposed BiMMDC converter supply for LVDC loads when a single line disconnection or
can always maintain the LVDC bipolar voltage at ±750 V pole-to-ground short-circuit fault occurs at the MVDC grid.
due to its interleaved connection and inherent bipolar feature. Besides, a bipolar LVDC interface needs to overcome the
When a positive-pole open-circuit fault occurs at the MVDC voltage/power imbalance between positive and negative poles
grid, the positive-pole current of the MVDC port is changed to caused by an asymmetric load and DG uncertainties.
zero, and the negative-pole current is stepped up to maintain For the proposed BiMMDC, one crucial advantage is signif-
power transferred from the MVDC grid to the LVDC grid. icant controllability. The proposed BiMMDC provides bipolar
During an open-circuit fault at the MVDC grid, the positive- MVDC and LVDC ports, which could provide more flexibility
pole converter is blocked, and the non-fault-side BiMMDC and resilience for loads and DGs due to two different voltage
can provide an uninterrupted power supply to LVDC loads. levels and maintain operation under a line fault. Interleaved
As shown in Fig. 21, it should also be noted that transferred converters combined with two double-winding transformers
power at the non-fault-side BiMMDC will increase because all are proposed to configure a bipolar LVDC interface with
powers at the LVDC grid are delivered by a non-fault pole with self-balancing capability. Power flow control of positive and
the interleaved converter. Thus, attention should be paid to negative poles can be decoupled and self-balanced by the pro-
avoiding overcurrent during the grid fault ride-through period. posed operation strategy, which significantly simplifies control
To conclude, the intrinsic short-circuit or open-circuit fault complexity. Another significant advantage of the proposed
ride-through ability is a significant advantage of the proposed BiMMDC is the intrinsic DC short-circuit fault ride-through
BiMMDC with the designed control scheme. The proposed capability. In our solution, two series-connected MMCs com-
BiMMDC can guarantee high power supply reliability of the bined with the interleaved converters are designed to configure
bipolar system. a bipolar MVDC interface with fault ride-through ability. A
pole-to-ground short circuit fault and open-circuit fault in
VII. C OMPARISONS B ETWEEN THE P ROPOSED B I MMDC
simulation part have proved the fault ride-through ability of
AND E XISTING S OLUTIONS
the proposed BiMMDC.
At present, there are two types of DC-DC converters which When a proposed BiMMDC and a traditional MMDC are
are suitable for interconnection of MVDC and LVDC grids, designed for the same power and voltage ratings, power de-
i.e., ISOP-DAB and MMDC. Table IV gives a comparison vices and passive components employed by the two converters
between the proposed BiMMDC and existing solutions. Both are almost identical. For example, if the MVDC voltage is
of them have the advantages of bidirectional power transmis- ±10 kV and the rated voltage of sub-module is 2 kV, both
sion, modularity, galvanic isolation, high efficiency and high- the proposed BiMMDC and the traditional MMDC need 40
power density. However, as mentioned in the Introduction, SMs at MV stage. Although the proposed BiMMDC employs
a conventional ISOP-DAB needs a concentrated capacitor at four transformers, the total volume of the transformers is
the MVDC side, which is hard to configure to the bipolar approximately the same because the volt-second of each
MVDC port. The existing concentrated capacitor results in double-winding transformer is only one-fourth that of the
difficulty in handling fault ride-through. Another concern of transformer in a conventional MMDC with the same RMS
DAB-ISOP is the insulation level of all transformers of ISOP- currents in the windings. Therefore, total financial costs from
DAB submodules should be designed considering the worst semiconductors, passive components and transformer materials
case. This leads to a significant waste of insulation efforts for are almost identical for the proposed BiMMDC and the
MVDC application. traditional MMDC. However, the proposed BiMMDC provides
TABLE IV more technical benefits than traditional ones. For example,
C OMPARISONS B ETWEEN THE P ROPOSED B I MMDC AND the proposed BiMMDC provides bipolar MVDC and LVDC
E XISTING S OLUTIONS
ports, achieves self-balancing capability and fault ride-through
ISOP-DAB MMDC Proposed ability when the MVDC grid has a pole-to-ground short-circuit
Item
[13], [15] [14], [19]–[21] BiMMDC fault.
Number of submodules 2N 4N + 1 4N + 4
Number of transformers N 1 4
Concentrated capacitor VIII. C ONCLUSION
Yes No No
at MVDC side
Bipolar at MVDC side No No Yes This paper presents a novel isolated bipolar modular mul-
Bipolar at LVDC side No No Yes tilevel DC-DC converter with power self-balancing capability
Fault ride-through ability No No Yes
Self-balancing ability No No Yes for a flexible interconnection of MVDC and LVDC grids. The
Controllability Medium Medium High proposed BiMMDC provides bipolar MVDC and LVDC ports.
Implementation of the proposed BiMMDC offers balanced
MMDC solutions combine the advantages of modular mul- pole currents at the MVDC port under unbalanced loads at
tilevel converter (MMC) and DAB, which eliminates a cen- the bipolar LVDC grid, which realizes voltage balancing at the
378 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 9, NO. 1, JANUARY 2023

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LAI et al.: ISOLATED BIPOLAR MODULAR MULTILEVEL DC-DC CONVERTER WITH SELF-BALANCING CAPABILITY FOR INTERCONNECTION OF MVDC AND LVDC GRIDS 379

[34] Y. J. Luo, Z. X. Li, L. N. Xu, X. F. Xiong, Y. H. Li, and C. Zhao, “An Lin Jiang (M’00) received the B.S. and M.S. de-
adaptive voltage-balancing method for high-power modular multilevel grees in Electrical Engineering from Huazhong Uni-
converters,” IEEE Transactions on Power Electronics, vol. 33, no. 4, versity of Science and Technology, Wuhan, China,
pp. 2901–2912, Apr. 2018. in 1992 and 1996, respectively, and the Ph.D. degree
in Electrical Engineering from the University of
Liverpool, Liverpool, U.K., in 2001. He is presently
working as a Reader of electrical engineering with
the University of Liverpool. His current research in-
Jinmu Lai (M’20) received the B.S. and M.S. terests include control and analysis of power system,
degrees in Electrical Engineering and the Ph.D. smart grid, and renewable energy.
degree from the Huazhong University of Science
and Technology, Wuhan, China, in 2014, 2017, and
2020, respectively. He is currently a Lecturer with
the School of Electrical Engineering, Zhengzhou
University, Zhengzhou, China. His research interests
include electric energy router, power quality control, Zia Ullah received a Ph.D. degree in Electrical
and the application of power electronics in power Engineering from the Huazhong University of Sci-
systems. ence and Technology (HUST), Wuhan, China, in
2020. He is currently working as a Postdoctoral
Research Fellow at the State Key Laboratory of
Advanced Electromagnetic Engineering and Tech-
nology, HUST. His research interests include power
system optimization, intelligent power distribution
Xin Yin (M’16) received the B.Eng. degree in Elec- networks, distribution system planning with renew-
tronic Engineering from the University of Sheffield, able energies, operation and control of distribution
U.K., in 2008, the M.Sc. degree in Telecommunica- networks, and advanced microgrids optimization.
tion from University College London, U.K., in 2009,
and the Ph.D. degree in Electrical and Electronic En-
gineering from the University of Manchester, U.K.,
in 2016. He is presently working as a Postdoctoral
Research Associate of electrical engineering with the Xianggen Yin (M’08–SM’20) received the B.S.,
University of Liverpool. His current research inter- M.S., and Ph.D. degrees in Electrical Engineering
ests include control of micro grid with renewable from Huazhong University of Science and Tech-
energy and demand side response. nology (HUST), Wuhan, China, in 1982, 1985 and
1989, respectively. He is now a Professor in the
School of Electrical and Electronic Engineering,
HUST. His research interests include protective re-
laying, power system stability control and power
Yaoqiang Wang (M’16–SM’21) received the B.Eng. electronics.
degree in Measurement and Control Technology
and Instruments from Hangzhou Dianzi University,
Hangzhou, China, in 2006, and M.Sc. and Ph.D.
degrees in Electrical Engineering from the Harbin
Institute of Technology, Harbin, China, in 2008 and
2013, respectively. He is currently working with the
School of Electrical Engineering, Zhengzhou Uni-
versity, Zhengzhou, China, and also serving as Di-
rectors of the Institute of Power Electronics and En-
ergy Systems of Zhengzhou University, Zhengzhou
Engineering Research Center of Power Control and System, and Henan
Engineering Research Center of Power Electronics and Energy Systems. He
has published over 50 peer-reviewed papers including 40 journal papers,
and authorized more than 10 patents. His research interests include power
electronics, renewable energy generation, flexible power distribution, MVDC,
electric motor drive, and electrified transport.