Low Power Sequential Circuits Using Multi Bit Flip

Flop
Gururaj A Tapashetti Christopher C R Umadevi S
[Link], VLSI DESIGN [Link], VLSI DESIGN Associate Professor (SENSE)
Vellore Institute of Technology Vellore Institute of Technology Vellore Institute of Technology
Chennai, India Chennai, India Chennai, India
gururaj.atapashetti2023@[Link] christopher.cr2023@[Link] umadevi.s@[Link]

Abstract—With the continuous advancement of technology, the single-bit flip-flop design. Multi-bit flip-flops have proven
there is a growing demand for designing devices with low power to be an effective technique for achieving low-power designs.
consumption. The development of smaller and more portable These flip-flops amalgamate single-bit flip-flops, eliminating
devices has prompted designers to focus on minimizing power
usage, particularly in digital circuits where reducing clock power redundant inverters that are typically shared among the flip-
is a significant factor in achieving low-power designs. A notable flops. This reduction in the number of inverters translates to
technique for achieving low-power designs is the utilization of a decrease in power consumption, thereby reducing dynamic
Multi-bit flip-flops, especially when sharing the clock signal power dissipation due to the decreased clock power consump-
among multiple flip-flops. This approach has been successfully tion.
applied to sequential circuits such as Shift Registers and Finite
State Machines (FSMs) to significantly reduce clock power The literature survey showed some of the common tech-
consumption and conserve overall [Link] the course of this niques used by different researchers in reducing power in
research, we have demonstrated the effectiveness of the Multi-bit digital circuits. In[1], the clock gating and MBFF combined
flip-flop approach in practice, using examples of Shift Registers is used to reduce power conception in SoC platforms, without
and FSMs. In both cases, it was empirically confirmed that degrading the delay aspect of the circuit. In this work, they
circuits implemented with Multi-bit flip-flops consume less clock
power compared to traditional flip-flops. Post-layout simulations have merged all the SBFF in the SOC to obtain a set of MBFF
of these circuits further validated these [Link] entire that provide the same working with reduction in power. In[2],
research was conducted using Cadence® Virtuoso, Cadence® a relatively new method for using the MBFF in the circuit.
Layout Editor, and Cadence® Assura, all implemented with Loosely Coupled MBFF (LC-MBFF), through this style of
180nm technology. FFs the placement area and delay of the circuit could be
Index Terms—Low power consumption, clock power, Multi-
bit flip-flops (MBFFs), Sequential circuits, Shift registers, Finite
reduced. The main objective of the work was to reduce the post
state Machine’s (FSM’s), Post-Layout simulation placement power. here a algorithm was developed to efficiently
place the blocks so that power will be reduced. !n[3], an
application perspective of MBFF in IoT systems is done. It
I. I NTRODUCTION
proposes the usage of MBFFs in IoT application to reduce the
In the realm of System-on-Chip (SoC) design, the com- delay and power consumption aspects so that portable IoT
plexity is on a continuous upward trajectory with respect processing devices can be designed with minimum latency
to power domains, gate count, and package densities. The and power dissipation. They have used iterative insertion of
challenges intensify as physical design teams struggle with the MBFF in different stages of implementation. In[4], the power
intricate task of balancing power consumption, performance, consumption in different configurations of network switches
and die area. This becomes especially critical as we migrate are being measured with respect to both SBFF and MBFF.
to ever-smaller technology nodes and increased packaging They came to realise that the power dissipation higher bit
[Link] power consumption emerges as a pivotal factor switches using MBFF was found to be decreasing. Even-
in determining the overall power usage within a single chip. though for low number of bit it does not show any variation but
To mitigate power-related concerns, various techniques have as the number of bits increases the power conception rapidly
been introduced and are currently applied in modern tech- reduces compared with their SBFF counter parts.
nologies. Among these, clock power reduction methods such
II. T HEORETICAL BACKGROUND
as clock gating, Multi Vth concept, and Multi Supply Multi
Voltage (MSMV) have gained considerable [Link] A. Single Bit Flip Flop
we consider designs employing single-bit flip-flops, the total SBFF consist of a master and a slave latch. The latches use
area tends to increase due to the larger number of sequential two different clock phases to perform the operation. The clock
and combinational cells involved. In contrast, the same design signal should use opposite phases, in order to have a better
can be implemented using multi-bit flip-flops, resulting in delay. To implement this property cascaded pair of inverters
reduced area and lower clock power consumption compared to are used. Fig 1 provides an example of SBFF.
 Fig. 1. Single Bit Flip Flop
Fig. 3. Dual Bit Flip Flop cell

B. Multi Bit Flip Flop

In case of MBFF the master and slave latch remains same
but the major difference here is the number of master and slave C. Shift Register
latches driven by the cascaded clock branch. If more than one
pair of master and slave latches are being driven by the clock A shift register is a fundamental digital electronic circuit
branch then it is referred to as MBFF. Here in Fig 2 an example used for the temporary storage and sequential processing of
of dual bit flip flop is given, which has a cascaded clock binary data. It consists of a series of flip-flops interconnected
driving 2 pairs of master and slave latches. When combining in a linear chain. Each flip-flop can store a single bit of data,
and the entire register can hold multiple bits. Shift registers can
perform two primary operations: shifting and loading. In the
shifting operation, data is moved from one flip-flop to the next
in a synchronized manner, either left or right. This allows for
the serial transfer of data. In the loading operation, new data
can be loaded into the register, replacing the existing contents.

D. Sequence Detector
A sequence detector is a digital circuit whose primary func-
tion is to continuously examine incoming data and generate
an output signal when it detects the desired sequence. This
output signal often serves as a trigger for subsequent actions,
decision-making processes, or further data processing. There
in general two types of sequence detectors:-
Fig. 2. Dual Bit Flip Flop 1. Mealy sequence detector:- It is a type of sequence
detector where the output depends not only on the current
one or more Single-Bit Flip-Flop (SBFF) cells with Multi-Bit input but also on the state of the machine. It can generate
Flip-Flop (MBFF) cells,the resulting circuit has the foillowing output signals that change asynchronously with the input and
advantages compared to the former circuit style: [Link] internal state changes, making it suitable for more complex
Clock Sinks. [Link] Power Consumption. [Link] Area sequences.
and Reduced Delay. [Link] Clock Skew. As illustrated in 2. In a Moore sequence detector:- In this type of sequence
Fig 3, a Dual-Bit Flip-Flop includes two data input pins, two detector the output depends only on the current state of the
data output pins, one clock pin, and a reset pin. The truth table machine and does not consider the current input. It’s a simpler
for the dual-bit flip-flop cell Table 1 demonstrates its behavior: and more straightforward type of sequence detector compared
at the positive edge of the clock signal (ck), the values of Q1 to the Mealy type.
and Q2 pass to D1 and D2, while at the negative clock edge,
Q1 and Q2 retain their original values. E. Delay
Propagation Delay (tpd ): Propagation delay (tpd ) is a
TABLE I critical metric for measuring the time it takes for a signal to
T RUTH TABLE OF DBFF
traverse a digital circuit. For combinational logic circuits, it’s
CK D1 Q1 D2 Q2 the time taken for the output to transition from one logical state
L to H L D1 L L to another when the input changes. It is the sum of the low-to-
high transition delay (tplh ) and the high-to-low transition delay
L to H H D1 H H
(tphl ):
H to L L L L D2
H to L H H H D2
tpd = tplh + tphl (1)
 In sequential circuits like flip-flops and registers, tpd in-
cludes the time taken for the signal to pass through the
combinational logic and the clock-to-Q delay, which is the
time it takes for the output to respond to a clock signal.

F. Power
Power Consumption (P): Power consumption in digital Fig. 4. Model OF SISO
circuits can be divided into two main components: static power
(Pstatic ) and dynamic power (Pdynamic ).
• Static Power (Pstatic ): represents the power consumed by B. Series In Parallel Out Shift Register(SIPO)
an IC when it is in a quiescent state, with no clock signal The input is given serially and Output is collected paral-
or input activity. It is primarily due to leakage currents in [Link] extra signal called clear is connected in addition to
transistors and is less dependent on switching activities. clock to reset the [Link] output of present flip-flop will
• Dynamic Power (Pdynamic ): is the power consumed when be the input to next flip-flop and all flip-flops are sharing the
signals transition between logic states and when there clock signal Fig 5 Model of Serial In Parallel [Link] SIPO
is activity within the circuit. It is directly related to the the outputs are collected immediately after the every flip-
switching frequency (f ) and the load capacitance (Cload ) flop .This type of registers are used to covert serial data into
of the circuit. The total power consumption (Ptotal ) is the parallel data, which will be useful in de-multiplexing of a data
sum of static and dynamic power: line in communication lines. In the proposed shift register the
same functionality is implemented using multi-bit flip-flops as
Ptotal = Pstatic + Pdynamic (2) shown Fig 5 where the two single bit flip-flops are replaced
with a 2bit flip-flop so as to consume less power.
The dynamic power consumption can be further calcu-
lated using the equation:

Pdynamic = 0.5 · Cload · Vdd2 · f (3)

Here, Cload represents the total load capacitance of the

circuit, Vdd is the supply voltage, and f is the switching
frequency.
Fig. 5. Model OF SIPO
III. P ROPOSED WORK AND METHADOLOGY
A. Series In Series Out Shift Register(SISO) C. Parallel In Series Out Shift Register(PISO)
In this register the input is given serially bit by bit and the The input to this register is given in parallel i.e. data is
output is collected one after the other [Link] at both the given separately to each flip flop and the output is collected
input and output side transfer of bits is done [Link] data in serial at the output of the end flip flop. For this type
can be shifted towards left or right that is only in one direction of shift registers the data is given in parallel individually
As the data is fed from left as bit by bit, the shift register to each register through a multiplexer. The inputs are given
shifts the data bits to right as shown in Fig 4 A 4-bit SISO parallel to each register and the data is collected serially. The
shift register consists of 4 flip flops which clock as common parallel data input and the present flip-flop output is given
input and Data In will given at the leftmost [Link] left as inputs to the multiplexer and the output of multiplexer is
registers are nothing but registers which will shift the bits connected to the next flip-flop. This type of shift registers
towards left [Link] right registers are nothing but registers convert parallel data into serial data where number of data lines
which will shift the bits towards right side. Among all the are multiplexed into single serial data In the proposed shift
four type of shift registers SISO is the simplest. Here the shift register the same functionality is implemented using multi-bit
of bits will be from left to right as all the 4 flip-flops are flip-flops as shown in Fig 6 where the two single bit flip-flops
connected to each other in such a way that output of present are replaced with a 2-bit flip-flop so as to consume less power.
flop will be the input of next flop and the leftmost flip-flop is
given the input. In Fig 4 the feeding is done at the leftmost
[Link] this shift register serially data is passed when clock D. Parallel In Parallel Out Shift Register(PIPO)
signal is [Link] is used to make a temporary storage while it In this register, the input is given in parallel and the output
is also used as delay element. In the proposed shift register the also collected in parallel. The clear (CLR) signal and clock
same functionality is implemented using multi-bit flip-flops as signals are connected to all the 4 flip flops. Data is given as
shown in Fig 4 where the two single bit flip-flops are replaced input separately for each flip flop and in the same way, output
with a 2-bit flip-flop so as to consume less power. also collected individually from each flip [Link] input is
 Fig. 8. 101 sequence detector using Moore

Fig. 6. Model of PISO IV. R ESULTS AND DISCUSSION

In the context of working with a 180nm technology node in
given parallel and the output is also taken parallelly. The input Cadence, our research conducted a comprehensive compara-
and output are taken individually for every flip-flop. The flip- tive analysis between Single-Bit Flip-Flops (SBFF) and Multi-
flops are independent on the previous or next flip-flops. The Bit Flip-Flops (MBFF) for sequential circuits. This analysis
clock will be shared by all the flip-flops. In the below Fig 7 the encompassed the evaluation of power consumption, delay, and
inputs are D1,D2,D3,D4 are inputs given in parallel and clock Power-Delay Product (PDP).Figure 9 illustrates the power
signal is given to each flip-flop. The outputs are Q1,Q2,Q3,Q4 consumption results, revealing a slight reduction in power
which are not dependent on previous flip-flops. for 4-bit sequential circuits implemented with Dual Bit Flip-
Flops compared to SBFF. However, the difference becomes
more pronounced when examining 8-bit sequential circuits.
Notably, in Figure 10, a similar trend is observed in the
delay characteristics of sequential circuits employing SBFF
and MBFF. An important finding is that the delay remains
consistent in both configurations, regardless of parallel input
or output operations. Figure 11 reinforces our observations
on power consumption, showing that 4-bit Sequential Multi-
Bit Flip-Flops (SMBFF) and Multi-Bit Flip-Flops (MBBF)
implementations exhibit relatively minor variations in their
PDP. In contrast, their 8-bit counterparts exhibit substantial
differences, with MBFF implementations clearly demonstrat-
Fig. 7. Model of PIPO ing a distinct advantage in terms of lower power dissipation.
These findings underscore the potential of MBFF architecture,
particularly in higher-bit applications, as a highly favorable
candidate for digital integrated circuits. This technology holds
E. Moore Sequence Detector (101) promise for significantly reducing both power consumption
and delay, making it a compelling choice for future digital IC
Designing a Moore sequence detector for the sequence designs.
”101” involves a systematic approach to recognizing this
specific pattern within a digital data stream. In this design,
we create a state machine with three distinct states: State 0
(initial state), State 1 (after detecting the first ”1”), and State
2 (after recognizing ”10”). Transitions between these states are
determined by the incoming data: a ”1” in State 0 transitions
to State 1, a ”0” in State 1 leads to State 2, and any other input
resets the detector to the initial State 0. State 2 serves as the
accepting state, indicating the successful detection of the ”101”
sequence. The Moore machine’s output signal, which depends
solely on the current state, can be set to indicate a successful Fig. 9. Power comparison
sequence detection. By implementing this circuit with flip-
flops and combinational logic, we can reliably identify and
respond to the ”101” sequence in the input.
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node using Cadence tools. Our investigation encompassed the
assessment of power consumption, delay, and Power-Delay
Product (PDP) for both 4-bit and 8-bit implementations. The
results have revealed compelling insights into the advantages
of MBFFs, particularly in high-bit applications. Our findings
indicate that the use of MBFFs in sequential circuits can
lead to a significant reduction in power consumption and
delay compared to traditional SBFF implementations. This
highlights the potential for MBFF architecture to be a favor-
able candidate for future digital integrated circuits, offering
substantial improvements in performance and efficiency.
Our research has opened up several promising avenues for
future investigations in the field of digital integrated circuits:
Scaling to Advanced Technology Nodes: Extending this study
to advanced technology nodes (e.g., 45nm, 28nm, or beyond)
is crucial to assess how MBFFs perform in cutting-edge
semiconductor processes. Low-Power Architectures: Explor-
ing the integration of MBFFs within low-power architectures
and assessing their effectiveness in energy-efficient digital
ICs. High-Performance Computing: Investigating the use of
MBFFs in high-performance computing systems, such as
graphics processors and AI accelerators, to determine their
potential in demanding applications.